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Searched refs:phy_offset (Results 1 – 3 of 3) sorted by relevance

/drivers/iio/adc/
Dexynos_adc.c118 int phy_offset; member
192 regmap_write(info->pmu_map, info->data->phy_offset, 1); in exynos_adc_v1_init_hw()
207 regmap_write(info->pmu_map, info->data->phy_offset, 0); in exynos_adc_v1_exit_hw()
234 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
324 regmap_write(info->pmu_map, info->data->phy_offset, 1); in exynos_adc_v2_init_hw()
342 regmap_write(info->pmu_map, info->data->phy_offset, 0); in exynos_adc_v2_exit_hw()
372 .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
385 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
398 regmap_write(info->pmu_map, info->data->phy_offset, 1); in exynos_adc_exynos7_init_hw()
/drivers/net/wireless/b43/
Dphy_lp.c624 u16 phy_offset; member
632 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
633 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
634 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
635 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
636 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
637 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
638 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
639 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
640 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
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/drivers/net/ethernet/intel/ixgbe/
Dixgbe_phy.c1028 u16 phy_offset, control, eword, edata, block_crc; in ixgbe_reset_phy_nl() local
1086 &phy_offset); in ixgbe_reset_phy_nl()
1094 hw->phy.ops.write_reg(hw, phy_offset, in ixgbe_reset_phy_nl()
1097 phy_offset); in ixgbe_reset_phy_nl()
1099 phy_offset++; in ixgbe_reset_phy_nl()