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1 /*******************************************************************************
2 
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2014 Intel Corporation.
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 
33 #include "ixgbe.h"
34 #include "ixgbe_phy.h"
35 
36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
51 
52 /**
53  *  ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54  *  @hw: pointer to the hardware structure
55  *  @byte: byte to send
56  *
57  *  Returns an error code on error.
58  **/
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,u8 byte)59 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
60 {
61 	s32 status;
62 
63 	status = ixgbe_clock_out_i2c_byte(hw, byte);
64 	if (status)
65 		return status;
66 	return ixgbe_get_i2c_ack(hw);
67 }
68 
69 /**
70  *  ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71  *  @hw: pointer to the hardware structure
72  *  @byte: pointer to a u8 to receive the byte
73  *
74  *  Returns an error code on error.
75  **/
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,u8 * byte)76 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
77 {
78 	s32 status;
79 
80 	status = ixgbe_clock_in_i2c_byte(hw, byte);
81 	if (status)
82 		return status;
83 	/* ACK */
84 	return ixgbe_clock_out_i2c_bit(hw, false);
85 }
86 
87 /**
88  *  ixgbe_ones_comp_byte_add - Perform one's complement addition
89  *  @add1: addend 1
90  *  @add2: addend 2
91  *
92  *  Returns one's complement 8-bit sum.
93  **/
ixgbe_ones_comp_byte_add(u8 add1,u8 add2)94 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
95 {
96 	u16 sum = add1 + add2;
97 
98 	sum = (sum & 0xFF) + (sum >> 8);
99 	return sum & 0xFF;
100 }
101 
102 /**
103  *  ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104  *  @hw: pointer to the hardware structure
105  *  @addr: I2C bus address to read from
106  *  @reg: I2C device register to read from
107  *  @val: pointer to location to receive read value
108  *  @lock: true if to take and release semaphore
109  *
110  *  Returns an error code on error.
111  */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val,bool lock)112 static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
113 					       u16 reg, u16 *val, bool lock)
114 {
115 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
116 	int max_retry = 3;
117 	int retry = 0;
118 	u8 csum_byte;
119 	u8 high_bits;
120 	u8 low_bits;
121 	u8 reg_high;
122 	u8 csum;
123 
124 	reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
125 	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
126 	csum = ~csum;
127 	do {
128 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
129 			return IXGBE_ERR_SWFW_SYNC;
130 		ixgbe_i2c_start(hw);
131 		/* Device Address and write indication */
132 		if (ixgbe_out_i2c_byte_ack(hw, addr))
133 			goto fail;
134 		/* Write bits 14:8 */
135 		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
136 			goto fail;
137 		/* Write bits 7:0 */
138 		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
139 			goto fail;
140 		/* Write csum */
141 		if (ixgbe_out_i2c_byte_ack(hw, csum))
142 			goto fail;
143 		/* Re-start condition */
144 		ixgbe_i2c_start(hw);
145 		/* Device Address and read indication */
146 		if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
147 			goto fail;
148 		/* Get upper bits */
149 		if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
150 			goto fail;
151 		/* Get low bits */
152 		if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
153 			goto fail;
154 		/* Get csum */
155 		if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
156 			goto fail;
157 		/* NACK */
158 		if (ixgbe_clock_out_i2c_bit(hw, false))
159 			goto fail;
160 		ixgbe_i2c_stop(hw);
161 		if (lock)
162 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
163 		*val = (high_bits << 8) | low_bits;
164 		return 0;
165 
166 fail:
167 		ixgbe_i2c_bus_clear(hw);
168 		if (lock)
169 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
170 		retry++;
171 		if (retry < max_retry)
172 			hw_dbg(hw, "I2C byte read combined error - Retry.\n");
173 		else
174 			hw_dbg(hw, "I2C byte read combined error.\n");
175 	} while (retry < max_retry);
176 
177 	return IXGBE_ERR_I2C;
178 }
179 
180 /**
181  *  ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
182  *  @hw: pointer to the hardware structure
183  *  @addr: I2C bus address to read from
184  *  @reg: I2C device register to read from
185  *  @val: pointer to location to receive read value
186  *
187  *  Returns an error code on error.
188  */
ixgbe_read_i2c_combined_generic(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val)189 s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
190 				    u16 reg, u16 *val)
191 {
192 	return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
193 }
194 
195 /**
196  *  ixgbe_read_i2c_combined_generic_unlocked - Unlocked I2C read combined
197  *  @hw: pointer to the hardware structure
198  *  @addr: I2C bus address to read from
199  *  @reg: I2C device register to read from
200  *  @val: pointer to location to receive read value
201  *
202  *  Returns an error code on error.
203  */
ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val)204 s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
205 					     u16 reg, u16 *val)
206 {
207 	return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
208 }
209 
210 /**
211  *  ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
212  *  @hw: pointer to the hardware structure
213  *  @addr: I2C bus address to write to
214  *  @reg: I2C device register to write to
215  *  @val: value to write
216  *  @lock: true if to take and release semaphore
217  *
218  *  Returns an error code on error.
219  */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val,bool lock)220 static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
221 						u16 reg, u16 val, bool lock)
222 {
223 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
224 	int max_retry = 1;
225 	int retry = 0;
226 	u8 reg_high;
227 	u8 csum;
228 
229 	reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
230 	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
231 	csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
232 	csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
233 	csum = ~csum;
234 	do {
235 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
236 			return IXGBE_ERR_SWFW_SYNC;
237 		ixgbe_i2c_start(hw);
238 		/* Device Address and write indication */
239 		if (ixgbe_out_i2c_byte_ack(hw, addr))
240 			goto fail;
241 		/* Write bits 14:8 */
242 		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
243 			goto fail;
244 		/* Write bits 7:0 */
245 		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
246 			goto fail;
247 		/* Write data 15:8 */
248 		if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
249 			goto fail;
250 		/* Write data 7:0 */
251 		if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
252 			goto fail;
253 		/* Write csum */
254 		if (ixgbe_out_i2c_byte_ack(hw, csum))
255 			goto fail;
256 		ixgbe_i2c_stop(hw);
257 		if (lock)
258 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
259 		return 0;
260 
261 fail:
262 		ixgbe_i2c_bus_clear(hw);
263 		if (lock)
264 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
265 		retry++;
266 		if (retry < max_retry)
267 			hw_dbg(hw, "I2C byte write combined error - Retry.\n");
268 		else
269 			hw_dbg(hw, "I2C byte write combined error.\n");
270 	} while (retry < max_retry);
271 
272 	return IXGBE_ERR_I2C;
273 }
274 
275 /**
276  *  ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
277  *  @hw: pointer to the hardware structure
278  *  @addr: I2C bus address to write to
279  *  @reg: I2C device register to write to
280  *  @val: value to write
281  *
282  *  Returns an error code on error.
283  */
ixgbe_write_i2c_combined_generic(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val)284 s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
285 				     u8 addr, u16 reg, u16 val)
286 {
287 	return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
288 }
289 
290 /**
291  *  ixgbe_write_i2c_combined_generic_unlocked - Unlocked I2C write combined
292  *  @hw: pointer to the hardware structure
293  *  @addr: I2C bus address to write to
294  *  @reg: I2C device register to write to
295  *  @val: value to write
296  *
297  *  Returns an error code on error.
298  */
ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val)299 s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
300 					      u8 addr, u16 reg, u16 val)
301 {
302 	return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
303 }
304 
305 /**
306  *  ixgbe_identify_phy_generic - Get physical layer module
307  *  @hw: pointer to hardware structure
308  *
309  *  Determines the physical layer module found on the current adapter.
310  **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)311 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
312 {
313 	u32 phy_addr;
314 	u16 ext_ability = 0;
315 
316 	if (!hw->phy.phy_semaphore_mask) {
317 		if (hw->bus.lan_id)
318 			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
319 		else
320 			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
321 	}
322 
323 	if (hw->phy.type == ixgbe_phy_unknown) {
324 		for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
325 			hw->phy.mdio.prtad = phy_addr;
326 			if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
327 				ixgbe_get_phy_id(hw);
328 				hw->phy.type =
329 					ixgbe_get_phy_type_from_id(hw->phy.id);
330 
331 				if (hw->phy.type == ixgbe_phy_unknown) {
332 					hw->phy.ops.read_reg(hw,
333 							     MDIO_PMA_EXTABLE,
334 							     MDIO_MMD_PMAPMD,
335 							     &ext_ability);
336 					if (ext_ability &
337 					    (MDIO_PMA_EXTABLE_10GBT |
338 					     MDIO_PMA_EXTABLE_1000BT))
339 						hw->phy.type =
340 							 ixgbe_phy_cu_unknown;
341 					else
342 						hw->phy.type =
343 							 ixgbe_phy_generic;
344 				}
345 
346 				return 0;
347 			}
348 		}
349 		/* clear value if nothing found */
350 		hw->phy.mdio.prtad = 0;
351 		return IXGBE_ERR_PHY_ADDR_INVALID;
352 	}
353 	return 0;
354 }
355 
356 /**
357  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
358  * @hw: pointer to the hardware structure
359  *
360  * This function checks the MMNGC.MNG_VETO bit to see if there are
361  * any constraints on link from manageability.  For MAC's that don't
362  * have this bit just return false since the link can not be blocked
363  * via this method.
364  **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)365 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
366 {
367 	u32 mmngc;
368 
369 	/* If we don't have this bit, it can't be blocking */
370 	if (hw->mac.type == ixgbe_mac_82598EB)
371 		return false;
372 
373 	mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
374 	if (mmngc & IXGBE_MMNGC_MNG_VETO) {
375 		hw_dbg(hw, "MNG_VETO bit detected.\n");
376 		return true;
377 	}
378 
379 	return false;
380 }
381 
382 /**
383  *  ixgbe_get_phy_id - Get the phy type
384  *  @hw: pointer to hardware structure
385  *
386  **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)387 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
388 {
389 	s32 status;
390 	u16 phy_id_high = 0;
391 	u16 phy_id_low = 0;
392 
393 	status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
394 				      &phy_id_high);
395 
396 	if (!status) {
397 		hw->phy.id = (u32)(phy_id_high << 16);
398 		status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
399 					      &phy_id_low);
400 		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
401 		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
402 	}
403 	return status;
404 }
405 
406 /**
407  *  ixgbe_get_phy_type_from_id - Get the phy type
408  *  @hw: pointer to hardware structure
409  *
410  **/
ixgbe_get_phy_type_from_id(u32 phy_id)411 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
412 {
413 	enum ixgbe_phy_type phy_type;
414 
415 	switch (phy_id) {
416 	case TN1010_PHY_ID:
417 		phy_type = ixgbe_phy_tn;
418 		break;
419 	case X550_PHY_ID:
420 	case X540_PHY_ID:
421 		phy_type = ixgbe_phy_aq;
422 		break;
423 	case QT2022_PHY_ID:
424 		phy_type = ixgbe_phy_qt;
425 		break;
426 	case ATH_PHY_ID:
427 		phy_type = ixgbe_phy_nl;
428 		break;
429 	case X557_PHY_ID:
430 		phy_type = ixgbe_phy_x550em_ext_t;
431 		break;
432 	default:
433 		phy_type = ixgbe_phy_unknown;
434 		break;
435 	}
436 
437 	return phy_type;
438 }
439 
440 /**
441  *  ixgbe_reset_phy_generic - Performs a PHY reset
442  *  @hw: pointer to hardware structure
443  **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)444 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
445 {
446 	u32 i;
447 	u16 ctrl = 0;
448 	s32 status = 0;
449 
450 	if (hw->phy.type == ixgbe_phy_unknown)
451 		status = ixgbe_identify_phy_generic(hw);
452 
453 	if (status != 0 || hw->phy.type == ixgbe_phy_none)
454 		return status;
455 
456 	/* Don't reset PHY if it's shut down due to overtemp. */
457 	if (!hw->phy.reset_if_overtemp &&
458 	    (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
459 		return 0;
460 
461 	/* Blocked by MNG FW so bail */
462 	if (ixgbe_check_reset_blocked(hw))
463 		return 0;
464 
465 	/*
466 	 * Perform soft PHY reset to the PHY_XS.
467 	 * This will cause a soft reset to the PHY
468 	 */
469 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
470 			      MDIO_MMD_PHYXS,
471 			      MDIO_CTRL1_RESET);
472 
473 	/*
474 	 * Poll for reset bit to self-clear indicating reset is complete.
475 	 * Some PHYs could take up to 3 seconds to complete and need about
476 	 * 1.7 usec delay after the reset is complete.
477 	 */
478 	for (i = 0; i < 30; i++) {
479 		msleep(100);
480 		hw->phy.ops.read_reg(hw, MDIO_CTRL1,
481 				     MDIO_MMD_PHYXS, &ctrl);
482 		if (!(ctrl & MDIO_CTRL1_RESET)) {
483 			udelay(2);
484 			break;
485 		}
486 	}
487 
488 	if (ctrl & MDIO_CTRL1_RESET) {
489 		hw_dbg(hw, "PHY reset polling failed to complete.\n");
490 		return IXGBE_ERR_RESET_FAILED;
491 	}
492 
493 	return 0;
494 }
495 
496 /**
497  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
498  *  the SWFW lock
499  *  @hw: pointer to hardware structure
500  *  @reg_addr: 32 bit address of PHY register to read
501  *  @phy_data: Pointer to read data from PHY register
502  **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)503 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
504 		       u16 *phy_data)
505 {
506 	u32 i, data, command;
507 
508 	/* Setup and write the address cycle command */
509 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
510 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
511 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
512 		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
513 
514 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
515 
516 	/* Check every 10 usec to see if the address cycle completed.
517 	 * The MDI Command bit will clear when the operation is
518 	 * complete
519 	 */
520 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
521 		udelay(10);
522 
523 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
524 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
525 				break;
526 	}
527 
528 
529 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
530 		hw_dbg(hw, "PHY address command did not complete.\n");
531 		return IXGBE_ERR_PHY;
532 	}
533 
534 	/* Address cycle complete, setup and write the read
535 	 * command
536 	 */
537 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
538 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
539 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
540 		   (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
541 
542 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
543 
544 	/* Check every 10 usec to see if the address cycle
545 	 * completed. The MDI Command bit will clear when the
546 	 * operation is complete
547 	 */
548 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
549 		udelay(10);
550 
551 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
552 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
553 			break;
554 	}
555 
556 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
557 		hw_dbg(hw, "PHY read command didn't complete\n");
558 		return IXGBE_ERR_PHY;
559 	}
560 
561 	/* Read operation is complete.  Get the data
562 	 * from MSRWD
563 	 */
564 	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
565 	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
566 	*phy_data = (u16)(data);
567 
568 	return 0;
569 }
570 
571 /**
572  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
573  *  using the SWFW lock - this function is needed in most cases
574  *  @hw: pointer to hardware structure
575  *  @reg_addr: 32 bit address of PHY register to read
576  *  @phy_data: Pointer to read data from PHY register
577  **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)578 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
579 			       u32 device_type, u16 *phy_data)
580 {
581 	s32 status;
582 	u32 gssr = hw->phy.phy_semaphore_mask;
583 
584 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
585 		status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
586 						phy_data);
587 		hw->mac.ops.release_swfw_sync(hw, gssr);
588 	} else {
589 		return IXGBE_ERR_SWFW_SYNC;
590 	}
591 
592 	return status;
593 }
594 
595 /**
596  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
597  *  without SWFW lock
598  *  @hw: pointer to hardware structure
599  *  @reg_addr: 32 bit PHY register to write
600  *  @device_type: 5 bit device type
601  *  @phy_data: Data to write to the PHY register
602  **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)603 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
604 				u32 device_type, u16 phy_data)
605 {
606 	u32 i, command;
607 
608 	/* Put the data in the MDI single read and write data register*/
609 	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
610 
611 	/* Setup and write the address cycle command */
612 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
613 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
614 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
615 		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
616 
617 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
618 
619 	/*
620 	 * Check every 10 usec to see if the address cycle completed.
621 	 * The MDI Command bit will clear when the operation is
622 	 * complete
623 	 */
624 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
625 		udelay(10);
626 
627 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
628 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
629 			break;
630 	}
631 
632 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
633 		hw_dbg(hw, "PHY address cmd didn't complete\n");
634 		return IXGBE_ERR_PHY;
635 	}
636 
637 	/*
638 	 * Address cycle complete, setup and write the write
639 	 * command
640 	 */
641 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
642 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
643 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
644 		   (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
645 
646 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
647 
648 	/* Check every 10 usec to see if the address cycle
649 	 * completed. The MDI Command bit will clear when the
650 	 * operation is complete
651 	 */
652 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
653 		udelay(10);
654 
655 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
656 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
657 			break;
658 	}
659 
660 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
661 		hw_dbg(hw, "PHY write cmd didn't complete\n");
662 		return IXGBE_ERR_PHY;
663 	}
664 
665 	return 0;
666 }
667 
668 /**
669  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
670  *  using SWFW lock- this function is needed in most cases
671  *  @hw: pointer to hardware structure
672  *  @reg_addr: 32 bit PHY register to write
673  *  @device_type: 5 bit device type
674  *  @phy_data: Data to write to the PHY register
675  **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)676 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
677 				u32 device_type, u16 phy_data)
678 {
679 	s32 status;
680 	u32 gssr = hw->phy.phy_semaphore_mask;
681 
682 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
683 		status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
684 						 phy_data);
685 		hw->mac.ops.release_swfw_sync(hw, gssr);
686 	} else {
687 		return IXGBE_ERR_SWFW_SYNC;
688 	}
689 
690 	return status;
691 }
692 
693 /**
694  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
695  *  @hw: pointer to hardware structure
696  *
697  *  Restart autonegotiation and PHY and waits for completion.
698  **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)699 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
700 {
701 	s32 status = 0;
702 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
703 	bool autoneg = false;
704 	ixgbe_link_speed speed;
705 
706 	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
707 
708 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
709 		/* Set or unset auto-negotiation 10G advertisement */
710 		hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
711 				     MDIO_MMD_AN,
712 				     &autoneg_reg);
713 
714 		autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
715 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
716 			autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
717 
718 		hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
719 				      MDIO_MMD_AN,
720 				      autoneg_reg);
721 	}
722 
723 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
724 		/* Set or unset auto-negotiation 1G advertisement */
725 		hw->phy.ops.read_reg(hw,
726 				     IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
727 				     MDIO_MMD_AN,
728 				     &autoneg_reg);
729 
730 		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
731 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
732 			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
733 
734 		hw->phy.ops.write_reg(hw,
735 				      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
736 				      MDIO_MMD_AN,
737 				      autoneg_reg);
738 	}
739 
740 	if (speed & IXGBE_LINK_SPEED_100_FULL) {
741 		/* Set or unset auto-negotiation 100M advertisement */
742 		hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
743 				     MDIO_MMD_AN,
744 				     &autoneg_reg);
745 
746 		autoneg_reg &= ~(ADVERTISE_100FULL |
747 				 ADVERTISE_100HALF);
748 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
749 			autoneg_reg |= ADVERTISE_100FULL;
750 
751 		hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
752 				      MDIO_MMD_AN,
753 				      autoneg_reg);
754 	}
755 
756 	/* Blocked by MNG FW so don't reset PHY */
757 	if (ixgbe_check_reset_blocked(hw))
758 		return 0;
759 
760 	/* Restart PHY autonegotiation and wait for completion */
761 	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
762 			     MDIO_MMD_AN, &autoneg_reg);
763 
764 	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
765 
766 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
767 			      MDIO_MMD_AN, autoneg_reg);
768 
769 	return status;
770 }
771 
772 /**
773  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
774  *  @hw: pointer to hardware structure
775  *  @speed: new link speed
776  **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)777 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
778 				       ixgbe_link_speed speed,
779 				       bool autoneg_wait_to_complete)
780 {
781 
782 	/*
783 	 * Clear autoneg_advertised and set new values based on input link
784 	 * speed.
785 	 */
786 	hw->phy.autoneg_advertised = 0;
787 
788 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
789 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
790 
791 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
792 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
793 
794 	if (speed & IXGBE_LINK_SPEED_100_FULL)
795 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
796 
797 	/* Setup link based on the new speed settings */
798 	hw->phy.ops.setup_link(hw);
799 
800 	return 0;
801 }
802 
803 /**
804  * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
805  * @hw: pointer to hardware structure
806  *
807  * Determines the supported link capabilities by reading the PHY auto
808  * negotiation register.
809  */
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)810 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
811 {
812 	u16 speed_ability;
813 	s32 status;
814 
815 	status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
816 				      &speed_ability);
817 	if (status)
818 		return status;
819 
820 	if (speed_ability & MDIO_SPEED_10G)
821 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
822 	if (speed_ability & MDIO_PMA_SPEED_1000)
823 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
824 	if (speed_ability & MDIO_PMA_SPEED_100)
825 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
826 
827 	switch (hw->mac.type) {
828 	case ixgbe_mac_X550:
829 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
830 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
831 		break;
832 	case ixgbe_mac_X550EM_x:
833 		hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
834 		break;
835 	default:
836 		break;
837 	}
838 
839 	return 0;
840 }
841 
842 /**
843  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
844  * @hw: pointer to hardware structure
845  * @speed: pointer to link speed
846  * @autoneg: boolean auto-negotiation value
847  */
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)848 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
849 					       ixgbe_link_speed *speed,
850 					       bool *autoneg)
851 {
852 	s32 status = 0;
853 
854 	*autoneg = true;
855 	if (!hw->phy.speeds_supported)
856 		status = ixgbe_get_copper_speeds_supported(hw);
857 
858 	*speed = hw->phy.speeds_supported;
859 	return status;
860 }
861 
862 /**
863  *  ixgbe_check_phy_link_tnx - Determine link and speed status
864  *  @hw: pointer to hardware structure
865  *
866  *  Reads the VS1 register to determine if link is up and the current speed for
867  *  the PHY.
868  **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)869 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
870 			     bool *link_up)
871 {
872 	s32 status;
873 	u32 time_out;
874 	u32 max_time_out = 10;
875 	u16 phy_link = 0;
876 	u16 phy_speed = 0;
877 	u16 phy_data = 0;
878 
879 	/* Initialize speed and link to default case */
880 	*link_up = false;
881 	*speed = IXGBE_LINK_SPEED_10GB_FULL;
882 
883 	/*
884 	 * Check current speed and link status of the PHY register.
885 	 * This is a vendor specific register and may have to
886 	 * be changed for other copper PHYs.
887 	 */
888 	for (time_out = 0; time_out < max_time_out; time_out++) {
889 		udelay(10);
890 		status = hw->phy.ops.read_reg(hw,
891 					      MDIO_STAT1,
892 					      MDIO_MMD_VEND1,
893 					      &phy_data);
894 		phy_link = phy_data &
895 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
896 		phy_speed = phy_data &
897 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
898 		if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
899 			*link_up = true;
900 			if (phy_speed ==
901 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
902 				*speed = IXGBE_LINK_SPEED_1GB_FULL;
903 			break;
904 		}
905 	}
906 
907 	return status;
908 }
909 
910 /**
911  *	ixgbe_setup_phy_link_tnx - Set and restart autoneg
912  *	@hw: pointer to hardware structure
913  *
914  *	Restart autonegotiation and PHY and waits for completion.
915  *      This function always returns success, this is nessary since
916  *	it is called via a function pointer that could call other
917  *	functions that could return an error.
918  **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)919 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
920 {
921 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
922 	bool autoneg = false;
923 	ixgbe_link_speed speed;
924 
925 	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
926 
927 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
928 		/* Set or unset auto-negotiation 10G advertisement */
929 		hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
930 				     MDIO_MMD_AN,
931 				     &autoneg_reg);
932 
933 		autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
934 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
935 			autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
936 
937 		hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
938 				      MDIO_MMD_AN,
939 				      autoneg_reg);
940 	}
941 
942 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
943 		/* Set or unset auto-negotiation 1G advertisement */
944 		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
945 				     MDIO_MMD_AN,
946 				     &autoneg_reg);
947 
948 		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
949 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
950 			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
951 
952 		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
953 				      MDIO_MMD_AN,
954 				      autoneg_reg);
955 	}
956 
957 	if (speed & IXGBE_LINK_SPEED_100_FULL) {
958 		/* Set or unset auto-negotiation 100M advertisement */
959 		hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
960 				     MDIO_MMD_AN,
961 				     &autoneg_reg);
962 
963 		autoneg_reg &= ~(ADVERTISE_100FULL |
964 				 ADVERTISE_100HALF);
965 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
966 			autoneg_reg |= ADVERTISE_100FULL;
967 
968 		hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
969 				      MDIO_MMD_AN,
970 				      autoneg_reg);
971 	}
972 
973 	/* Blocked by MNG FW so don't reset PHY */
974 	if (ixgbe_check_reset_blocked(hw))
975 		return 0;
976 
977 	/* Restart PHY autonegotiation and wait for completion */
978 	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
979 			     MDIO_MMD_AN, &autoneg_reg);
980 
981 	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
982 
983 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
984 			      MDIO_MMD_AN, autoneg_reg);
985 	return 0;
986 }
987 
988 /**
989  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
990  *  @hw: pointer to hardware structure
991  *  @firmware_version: pointer to the PHY Firmware Version
992  **/
ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw * hw,u16 * firmware_version)993 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
994 				       u16 *firmware_version)
995 {
996 	s32 status;
997 
998 	status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
999 				      MDIO_MMD_VEND1,
1000 				      firmware_version);
1001 
1002 	return status;
1003 }
1004 
1005 /**
1006  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1007  *  @hw: pointer to hardware structure
1008  *  @firmware_version: pointer to the PHY Firmware Version
1009  **/
ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw * hw,u16 * firmware_version)1010 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1011 					   u16 *firmware_version)
1012 {
1013 	s32 status;
1014 
1015 	status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1016 				      MDIO_MMD_VEND1,
1017 				      firmware_version);
1018 
1019 	return status;
1020 }
1021 
1022 /**
1023  *  ixgbe_reset_phy_nl - Performs a PHY reset
1024  *  @hw: pointer to hardware structure
1025  **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1026 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1027 {
1028 	u16 phy_offset, control, eword, edata, block_crc;
1029 	bool end_data = false;
1030 	u16 list_offset, data_offset;
1031 	u16 phy_data = 0;
1032 	s32 ret_val;
1033 	u32 i;
1034 
1035 	/* Blocked by MNG FW so bail */
1036 	if (ixgbe_check_reset_blocked(hw))
1037 		return 0;
1038 
1039 	hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1040 
1041 	/* reset the PHY and poll for completion */
1042 	hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1043 			      (phy_data | MDIO_CTRL1_RESET));
1044 
1045 	for (i = 0; i < 100; i++) {
1046 		hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1047 				     &phy_data);
1048 		if ((phy_data & MDIO_CTRL1_RESET) == 0)
1049 			break;
1050 		usleep_range(10000, 20000);
1051 	}
1052 
1053 	if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1054 		hw_dbg(hw, "PHY reset did not complete.\n");
1055 		return IXGBE_ERR_PHY;
1056 	}
1057 
1058 	/* Get init offsets */
1059 	ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1060 						      &data_offset);
1061 	if (ret_val)
1062 		return ret_val;
1063 
1064 	ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1065 	data_offset++;
1066 	while (!end_data) {
1067 		/*
1068 		 * Read control word from PHY init contents offset
1069 		 */
1070 		ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1071 		if (ret_val)
1072 			goto err_eeprom;
1073 		control = (eword & IXGBE_CONTROL_MASK_NL) >>
1074 			   IXGBE_CONTROL_SHIFT_NL;
1075 		edata = eword & IXGBE_DATA_MASK_NL;
1076 		switch (control) {
1077 		case IXGBE_DELAY_NL:
1078 			data_offset++;
1079 			hw_dbg(hw, "DELAY: %d MS\n", edata);
1080 			usleep_range(edata * 1000, edata * 2000);
1081 			break;
1082 		case IXGBE_DATA_NL:
1083 			hw_dbg(hw, "DATA:\n");
1084 			data_offset++;
1085 			ret_val = hw->eeprom.ops.read(hw, data_offset++,
1086 						      &phy_offset);
1087 			if (ret_val)
1088 				goto err_eeprom;
1089 			for (i = 0; i < edata; i++) {
1090 				ret_val = hw->eeprom.ops.read(hw, data_offset,
1091 							      &eword);
1092 				if (ret_val)
1093 					goto err_eeprom;
1094 				hw->phy.ops.write_reg(hw, phy_offset,
1095 						      MDIO_MMD_PMAPMD, eword);
1096 				hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1097 				       phy_offset);
1098 				data_offset++;
1099 				phy_offset++;
1100 			}
1101 			break;
1102 		case IXGBE_CONTROL_NL:
1103 			data_offset++;
1104 			hw_dbg(hw, "CONTROL:\n");
1105 			if (edata == IXGBE_CONTROL_EOL_NL) {
1106 				hw_dbg(hw, "EOL\n");
1107 				end_data = true;
1108 			} else if (edata == IXGBE_CONTROL_SOL_NL) {
1109 				hw_dbg(hw, "SOL\n");
1110 			} else {
1111 				hw_dbg(hw, "Bad control value\n");
1112 				return IXGBE_ERR_PHY;
1113 			}
1114 			break;
1115 		default:
1116 			hw_dbg(hw, "Bad control type\n");
1117 			return IXGBE_ERR_PHY;
1118 		}
1119 	}
1120 
1121 	return ret_val;
1122 
1123 err_eeprom:
1124 	hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1125 	return IXGBE_ERR_PHY;
1126 }
1127 
1128 /**
1129  *  ixgbe_identify_module_generic - Identifies module type
1130  *  @hw: pointer to hardware structure
1131  *
1132  *  Determines HW type and calls appropriate function.
1133  **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1134 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1135 {
1136 	switch (hw->mac.ops.get_media_type(hw)) {
1137 	case ixgbe_media_type_fiber:
1138 		return ixgbe_identify_sfp_module_generic(hw);
1139 	case ixgbe_media_type_fiber_qsfp:
1140 		return ixgbe_identify_qsfp_module_generic(hw);
1141 	default:
1142 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1143 		return IXGBE_ERR_SFP_NOT_PRESENT;
1144 	}
1145 
1146 	return IXGBE_ERR_SFP_NOT_PRESENT;
1147 }
1148 
1149 /**
1150  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1151  *  @hw: pointer to hardware structure
1152  *
1153  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1154  **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1155 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1156 {
1157 	struct ixgbe_adapter *adapter = hw->back;
1158 	s32 status;
1159 	u32 vendor_oui = 0;
1160 	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1161 	u8 identifier = 0;
1162 	u8 comp_codes_1g = 0;
1163 	u8 comp_codes_10g = 0;
1164 	u8 oui_bytes[3] = {0, 0, 0};
1165 	u8 cable_tech = 0;
1166 	u8 cable_spec = 0;
1167 	u16 enforce_sfp = 0;
1168 
1169 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1170 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1171 		return IXGBE_ERR_SFP_NOT_PRESENT;
1172 	}
1173 
1174 	/* LAN ID is needed for sfp_type determination */
1175 	hw->mac.ops.set_lan_id(hw);
1176 
1177 	status = hw->phy.ops.read_i2c_eeprom(hw,
1178 					     IXGBE_SFF_IDENTIFIER,
1179 					     &identifier);
1180 
1181 	if (status)
1182 		goto err_read_i2c_eeprom;
1183 
1184 	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1185 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1186 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1187 	}
1188 	status = hw->phy.ops.read_i2c_eeprom(hw,
1189 					     IXGBE_SFF_1GBE_COMP_CODES,
1190 					     &comp_codes_1g);
1191 
1192 	if (status)
1193 		goto err_read_i2c_eeprom;
1194 
1195 	status = hw->phy.ops.read_i2c_eeprom(hw,
1196 					     IXGBE_SFF_10GBE_COMP_CODES,
1197 					     &comp_codes_10g);
1198 
1199 	if (status)
1200 		goto err_read_i2c_eeprom;
1201 	status = hw->phy.ops.read_i2c_eeprom(hw,
1202 					     IXGBE_SFF_CABLE_TECHNOLOGY,
1203 					     &cable_tech);
1204 
1205 	if (status)
1206 		goto err_read_i2c_eeprom;
1207 
1208 	 /* ID Module
1209 	  * =========
1210 	  * 0   SFP_DA_CU
1211 	  * 1   SFP_SR
1212 	  * 2   SFP_LR
1213 	  * 3   SFP_DA_CORE0 - 82599-specific
1214 	  * 4   SFP_DA_CORE1 - 82599-specific
1215 	  * 5   SFP_SR/LR_CORE0 - 82599-specific
1216 	  * 6   SFP_SR/LR_CORE1 - 82599-specific
1217 	  * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1218 	  * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1219 	  * 9   SFP_1g_cu_CORE0 - 82599-specific
1220 	  * 10  SFP_1g_cu_CORE1 - 82599-specific
1221 	  * 11  SFP_1g_sx_CORE0 - 82599-specific
1222 	  * 12  SFP_1g_sx_CORE1 - 82599-specific
1223 	  */
1224 	if (hw->mac.type == ixgbe_mac_82598EB) {
1225 		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1226 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1227 		else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1228 			hw->phy.sfp_type = ixgbe_sfp_type_sr;
1229 		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1230 			hw->phy.sfp_type = ixgbe_sfp_type_lr;
1231 		else
1232 			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1233 	} else {
1234 		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1235 			if (hw->bus.lan_id == 0)
1236 				hw->phy.sfp_type =
1237 					     ixgbe_sfp_type_da_cu_core0;
1238 			else
1239 				hw->phy.sfp_type =
1240 					     ixgbe_sfp_type_da_cu_core1;
1241 		} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1242 			hw->phy.ops.read_i2c_eeprom(
1243 					hw, IXGBE_SFF_CABLE_SPEC_COMP,
1244 					&cable_spec);
1245 			if (cable_spec &
1246 			    IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1247 				if (hw->bus.lan_id == 0)
1248 					hw->phy.sfp_type =
1249 					ixgbe_sfp_type_da_act_lmt_core0;
1250 				else
1251 					hw->phy.sfp_type =
1252 					ixgbe_sfp_type_da_act_lmt_core1;
1253 			} else {
1254 				hw->phy.sfp_type =
1255 						ixgbe_sfp_type_unknown;
1256 			}
1257 		} else if (comp_codes_10g &
1258 			   (IXGBE_SFF_10GBASESR_CAPABLE |
1259 			    IXGBE_SFF_10GBASELR_CAPABLE)) {
1260 			if (hw->bus.lan_id == 0)
1261 				hw->phy.sfp_type =
1262 					      ixgbe_sfp_type_srlr_core0;
1263 			else
1264 				hw->phy.sfp_type =
1265 					      ixgbe_sfp_type_srlr_core1;
1266 		} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1267 			if (hw->bus.lan_id == 0)
1268 				hw->phy.sfp_type =
1269 					ixgbe_sfp_type_1g_cu_core0;
1270 			else
1271 				hw->phy.sfp_type =
1272 					ixgbe_sfp_type_1g_cu_core1;
1273 		} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1274 			if (hw->bus.lan_id == 0)
1275 				hw->phy.sfp_type =
1276 					ixgbe_sfp_type_1g_sx_core0;
1277 			else
1278 				hw->phy.sfp_type =
1279 					ixgbe_sfp_type_1g_sx_core1;
1280 		} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1281 			if (hw->bus.lan_id == 0)
1282 				hw->phy.sfp_type =
1283 					ixgbe_sfp_type_1g_lx_core0;
1284 			else
1285 				hw->phy.sfp_type =
1286 					ixgbe_sfp_type_1g_lx_core1;
1287 		} else {
1288 			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1289 		}
1290 	}
1291 
1292 	if (hw->phy.sfp_type != stored_sfp_type)
1293 		hw->phy.sfp_setup_needed = true;
1294 
1295 	/* Determine if the SFP+ PHY is dual speed or not. */
1296 	hw->phy.multispeed_fiber = false;
1297 	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1298 	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1299 	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1300 	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1301 		hw->phy.multispeed_fiber = true;
1302 
1303 	/* Determine PHY vendor */
1304 	if (hw->phy.type != ixgbe_phy_nl) {
1305 		hw->phy.id = identifier;
1306 		status = hw->phy.ops.read_i2c_eeprom(hw,
1307 					    IXGBE_SFF_VENDOR_OUI_BYTE0,
1308 					    &oui_bytes[0]);
1309 
1310 		if (status != 0)
1311 			goto err_read_i2c_eeprom;
1312 
1313 		status = hw->phy.ops.read_i2c_eeprom(hw,
1314 					    IXGBE_SFF_VENDOR_OUI_BYTE1,
1315 					    &oui_bytes[1]);
1316 
1317 		if (status != 0)
1318 			goto err_read_i2c_eeprom;
1319 
1320 		status = hw->phy.ops.read_i2c_eeprom(hw,
1321 					    IXGBE_SFF_VENDOR_OUI_BYTE2,
1322 					    &oui_bytes[2]);
1323 
1324 		if (status != 0)
1325 			goto err_read_i2c_eeprom;
1326 
1327 		vendor_oui =
1328 		  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1329 		   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1330 		   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1331 
1332 		switch (vendor_oui) {
1333 		case IXGBE_SFF_VENDOR_OUI_TYCO:
1334 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1335 				hw->phy.type =
1336 					    ixgbe_phy_sfp_passive_tyco;
1337 			break;
1338 		case IXGBE_SFF_VENDOR_OUI_FTL:
1339 			if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1340 				hw->phy.type = ixgbe_phy_sfp_ftl_active;
1341 			else
1342 				hw->phy.type = ixgbe_phy_sfp_ftl;
1343 			break;
1344 		case IXGBE_SFF_VENDOR_OUI_AVAGO:
1345 			hw->phy.type = ixgbe_phy_sfp_avago;
1346 			break;
1347 		case IXGBE_SFF_VENDOR_OUI_INTEL:
1348 			hw->phy.type = ixgbe_phy_sfp_intel;
1349 			break;
1350 		default:
1351 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1352 				hw->phy.type =
1353 					 ixgbe_phy_sfp_passive_unknown;
1354 			else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1355 				hw->phy.type =
1356 					ixgbe_phy_sfp_active_unknown;
1357 			else
1358 				hw->phy.type = ixgbe_phy_sfp_unknown;
1359 			break;
1360 		}
1361 	}
1362 
1363 	/* Allow any DA cable vendor */
1364 	if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1365 	    IXGBE_SFF_DA_ACTIVE_CABLE))
1366 		return 0;
1367 
1368 	/* Verify supported 1G SFP modules */
1369 	if (comp_codes_10g == 0 &&
1370 	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1371 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1372 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1373 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1374 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1375 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1376 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1377 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1378 	}
1379 
1380 	/* Anything else 82598-based is supported */
1381 	if (hw->mac.type == ixgbe_mac_82598EB)
1382 		return 0;
1383 
1384 	hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1385 	if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1386 	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1387 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1388 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1389 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1390 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1391 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1392 		/* Make sure we're a supported PHY type */
1393 		if (hw->phy.type == ixgbe_phy_sfp_intel)
1394 			return 0;
1395 		if (hw->allow_unsupported_sfp) {
1396 			e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1397 			return 0;
1398 		}
1399 		hw_dbg(hw, "SFP+ module not supported\n");
1400 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1401 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1402 	}
1403 	return 0;
1404 
1405 err_read_i2c_eeprom:
1406 	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1407 	if (hw->phy.type != ixgbe_phy_nl) {
1408 		hw->phy.id = 0;
1409 		hw->phy.type = ixgbe_phy_unknown;
1410 	}
1411 	return IXGBE_ERR_SFP_NOT_PRESENT;
1412 }
1413 
1414 /**
1415  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1416  * @hw: pointer to hardware structure
1417  *
1418  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1419  **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1420 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1421 {
1422 	struct ixgbe_adapter *adapter = hw->back;
1423 	s32 status;
1424 	u32 vendor_oui = 0;
1425 	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1426 	u8 identifier = 0;
1427 	u8 comp_codes_1g = 0;
1428 	u8 comp_codes_10g = 0;
1429 	u8 oui_bytes[3] = {0, 0, 0};
1430 	u16 enforce_sfp = 0;
1431 	u8 connector = 0;
1432 	u8 cable_length = 0;
1433 	u8 device_tech = 0;
1434 	bool active_cable = false;
1435 
1436 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1437 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1438 		return IXGBE_ERR_SFP_NOT_PRESENT;
1439 	}
1440 
1441 	/* LAN ID is needed for sfp_type determination */
1442 	hw->mac.ops.set_lan_id(hw);
1443 
1444 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1445 					     &identifier);
1446 
1447 	if (status != 0)
1448 		goto err_read_i2c_eeprom;
1449 
1450 	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1451 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1452 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1453 	}
1454 
1455 	hw->phy.id = identifier;
1456 
1457 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1458 					     &comp_codes_10g);
1459 
1460 	if (status != 0)
1461 		goto err_read_i2c_eeprom;
1462 
1463 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1464 					     &comp_codes_1g);
1465 
1466 	if (status != 0)
1467 		goto err_read_i2c_eeprom;
1468 
1469 	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1470 		hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1471 		if (hw->bus.lan_id == 0)
1472 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1473 		else
1474 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1475 	} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1476 				     IXGBE_SFF_10GBASELR_CAPABLE)) {
1477 		if (hw->bus.lan_id == 0)
1478 			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1479 		else
1480 			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1481 	} else {
1482 		if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1483 			active_cable = true;
1484 
1485 		if (!active_cable) {
1486 			/* check for active DA cables that pre-date
1487 			 * SFF-8436 v3.6
1488 			 */
1489 			hw->phy.ops.read_i2c_eeprom(hw,
1490 					IXGBE_SFF_QSFP_CONNECTOR,
1491 					&connector);
1492 
1493 			hw->phy.ops.read_i2c_eeprom(hw,
1494 					IXGBE_SFF_QSFP_CABLE_LENGTH,
1495 					&cable_length);
1496 
1497 			hw->phy.ops.read_i2c_eeprom(hw,
1498 					IXGBE_SFF_QSFP_DEVICE_TECH,
1499 					&device_tech);
1500 
1501 			if ((connector ==
1502 				     IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1503 			    (cable_length > 0) &&
1504 			    ((device_tech >> 4) ==
1505 				     IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1506 				active_cable = true;
1507 		}
1508 
1509 		if (active_cable) {
1510 			hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1511 			if (hw->bus.lan_id == 0)
1512 				hw->phy.sfp_type =
1513 						ixgbe_sfp_type_da_act_lmt_core0;
1514 			else
1515 				hw->phy.sfp_type =
1516 						ixgbe_sfp_type_da_act_lmt_core1;
1517 		} else {
1518 			/* unsupported module type */
1519 			hw->phy.type = ixgbe_phy_sfp_unsupported;
1520 			return IXGBE_ERR_SFP_NOT_SUPPORTED;
1521 		}
1522 	}
1523 
1524 	if (hw->phy.sfp_type != stored_sfp_type)
1525 		hw->phy.sfp_setup_needed = true;
1526 
1527 	/* Determine if the QSFP+ PHY is dual speed or not. */
1528 	hw->phy.multispeed_fiber = false;
1529 	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1530 	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1531 	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1532 	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1533 		hw->phy.multispeed_fiber = true;
1534 
1535 	/* Determine PHY vendor for optical modules */
1536 	if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1537 			      IXGBE_SFF_10GBASELR_CAPABLE)) {
1538 		status = hw->phy.ops.read_i2c_eeprom(hw,
1539 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1540 					&oui_bytes[0]);
1541 
1542 		if (status != 0)
1543 			goto err_read_i2c_eeprom;
1544 
1545 		status = hw->phy.ops.read_i2c_eeprom(hw,
1546 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1547 					&oui_bytes[1]);
1548 
1549 		if (status != 0)
1550 			goto err_read_i2c_eeprom;
1551 
1552 		status = hw->phy.ops.read_i2c_eeprom(hw,
1553 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1554 					&oui_bytes[2]);
1555 
1556 		if (status != 0)
1557 			goto err_read_i2c_eeprom;
1558 
1559 		vendor_oui =
1560 			((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1561 			 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1562 			 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1563 
1564 		if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1565 			hw->phy.type = ixgbe_phy_qsfp_intel;
1566 		else
1567 			hw->phy.type = ixgbe_phy_qsfp_unknown;
1568 
1569 		hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1570 		if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1571 			/* Make sure we're a supported PHY type */
1572 			if (hw->phy.type == ixgbe_phy_qsfp_intel)
1573 				return 0;
1574 			if (hw->allow_unsupported_sfp) {
1575 				e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1576 				return 0;
1577 			}
1578 			hw_dbg(hw, "QSFP module not supported\n");
1579 			hw->phy.type = ixgbe_phy_sfp_unsupported;
1580 			return IXGBE_ERR_SFP_NOT_SUPPORTED;
1581 		}
1582 		return 0;
1583 	}
1584 	return 0;
1585 
1586 err_read_i2c_eeprom:
1587 	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1588 	hw->phy.id = 0;
1589 	hw->phy.type = ixgbe_phy_unknown;
1590 
1591 	return IXGBE_ERR_SFP_NOT_PRESENT;
1592 }
1593 
1594 /**
1595  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1596  *  @hw: pointer to hardware structure
1597  *  @list_offset: offset to the SFP ID list
1598  *  @data_offset: offset to the SFP data block
1599  *
1600  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1601  *  so it returns the offsets to the phy init sequence block.
1602  **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,u16 * list_offset,u16 * data_offset)1603 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1604 					u16 *list_offset,
1605 					u16 *data_offset)
1606 {
1607 	u16 sfp_id;
1608 	u16 sfp_type = hw->phy.sfp_type;
1609 
1610 	if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1611 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1612 
1613 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1614 		return IXGBE_ERR_SFP_NOT_PRESENT;
1615 
1616 	if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1617 	    (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1618 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1619 
1620 	/*
1621 	 * Limiting active cables and 1G Phys must be initialized as
1622 	 * SR modules
1623 	 */
1624 	if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1625 	    sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1626 	    sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1627 	    sfp_type == ixgbe_sfp_type_1g_sx_core0)
1628 		sfp_type = ixgbe_sfp_type_srlr_core0;
1629 	else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1630 		 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1631 		 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1632 		 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1633 		sfp_type = ixgbe_sfp_type_srlr_core1;
1634 
1635 	/* Read offset to PHY init contents */
1636 	if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1637 		hw_err(hw, "eeprom read at %d failed\n",
1638 		       IXGBE_PHY_INIT_OFFSET_NL);
1639 		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1640 	}
1641 
1642 	if ((!*list_offset) || (*list_offset == 0xFFFF))
1643 		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1644 
1645 	/* Shift offset to first ID word */
1646 	(*list_offset)++;
1647 
1648 	/*
1649 	 * Find the matching SFP ID in the EEPROM
1650 	 * and program the init sequence
1651 	 */
1652 	if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1653 		goto err_phy;
1654 
1655 	while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1656 		if (sfp_id == sfp_type) {
1657 			(*list_offset)++;
1658 			if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1659 				goto err_phy;
1660 			if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1661 				hw_dbg(hw, "SFP+ module not supported\n");
1662 				return IXGBE_ERR_SFP_NOT_SUPPORTED;
1663 			} else {
1664 				break;
1665 			}
1666 		} else {
1667 			(*list_offset) += 2;
1668 			if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1669 				goto err_phy;
1670 		}
1671 	}
1672 
1673 	if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1674 		hw_dbg(hw, "No matching SFP+ module found\n");
1675 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1676 	}
1677 
1678 	return 0;
1679 
1680 err_phy:
1681 	hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1682 	return IXGBE_ERR_PHY;
1683 }
1684 
1685 /**
1686  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1687  *  @hw: pointer to hardware structure
1688  *  @byte_offset: EEPROM byte offset to read
1689  *  @eeprom_data: value read
1690  *
1691  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1692  **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1693 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1694 				  u8 *eeprom_data)
1695 {
1696 	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1697 					 IXGBE_I2C_EEPROM_DEV_ADDR,
1698 					 eeprom_data);
1699 }
1700 
1701 /**
1702  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1703  *  @hw: pointer to hardware structure
1704  *  @byte_offset: byte offset at address 0xA2
1705  *  @eeprom_data: value read
1706  *
1707  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1708  **/
ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1709 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1710 				   u8 *sff8472_data)
1711 {
1712 	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1713 					 IXGBE_I2C_EEPROM_DEV_ADDR2,
1714 					 sff8472_data);
1715 }
1716 
1717 /**
1718  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1719  *  @hw: pointer to hardware structure
1720  *  @byte_offset: EEPROM byte offset to write
1721  *  @eeprom_data: value to write
1722  *
1723  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1724  **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1725 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1726 				   u8 eeprom_data)
1727 {
1728 	return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1729 					  IXGBE_I2C_EEPROM_DEV_ADDR,
1730 					  eeprom_data);
1731 }
1732 
1733 /**
1734  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1735  * @hw: pointer to hardware structure
1736  * @offset: eeprom offset to be read
1737  * @addr: I2C address to be read
1738  */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,u8 offset,u8 addr)1739 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1740 {
1741 	if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1742 	    offset == IXGBE_SFF_IDENTIFIER &&
1743 	    hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1744 		return true;
1745 	return false;
1746 }
1747 
1748 /**
1749  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1750  *  @hw: pointer to hardware structure
1751  *  @byte_offset: byte offset to read
1752  *  @data: value read
1753  *  @lock: true if to take and release semaphore
1754  *
1755  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1756  *  a specified device address.
1757  */
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data,bool lock)1758 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1759 					   u8 dev_addr, u8 *data, bool lock)
1760 {
1761 	s32 status;
1762 	u32 max_retry = 10;
1763 	u32 retry = 0;
1764 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
1765 	bool nack = true;
1766 
1767 	if (hw->mac.type >= ixgbe_mac_X550)
1768 		max_retry = 3;
1769 	if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1770 		max_retry = IXGBE_SFP_DETECT_RETRIES;
1771 
1772 	*data = 0;
1773 
1774 	do {
1775 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1776 			return IXGBE_ERR_SWFW_SYNC;
1777 
1778 		ixgbe_i2c_start(hw);
1779 
1780 		/* Device Address and write indication */
1781 		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1782 		if (status != 0)
1783 			goto fail;
1784 
1785 		status = ixgbe_get_i2c_ack(hw);
1786 		if (status != 0)
1787 			goto fail;
1788 
1789 		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1790 		if (status != 0)
1791 			goto fail;
1792 
1793 		status = ixgbe_get_i2c_ack(hw);
1794 		if (status != 0)
1795 			goto fail;
1796 
1797 		ixgbe_i2c_start(hw);
1798 
1799 		/* Device Address and read indication */
1800 		status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1801 		if (status != 0)
1802 			goto fail;
1803 
1804 		status = ixgbe_get_i2c_ack(hw);
1805 		if (status != 0)
1806 			goto fail;
1807 
1808 		status = ixgbe_clock_in_i2c_byte(hw, data);
1809 		if (status != 0)
1810 			goto fail;
1811 
1812 		status = ixgbe_clock_out_i2c_bit(hw, nack);
1813 		if (status != 0)
1814 			goto fail;
1815 
1816 		ixgbe_i2c_stop(hw);
1817 		if (lock)
1818 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1819 		return 0;
1820 
1821 fail:
1822 		ixgbe_i2c_bus_clear(hw);
1823 		if (lock) {
1824 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1825 			msleep(100);
1826 		}
1827 		retry++;
1828 		if (retry < max_retry)
1829 			hw_dbg(hw, "I2C byte read error - Retrying.\n");
1830 		else
1831 			hw_dbg(hw, "I2C byte read error.\n");
1832 
1833 	} while (retry < max_retry);
1834 
1835 	return status;
1836 }
1837 
1838 /**
1839  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1840  *  @hw: pointer to hardware structure
1841  *  @byte_offset: byte offset to read
1842  *  @data: value read
1843  *
1844  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1845  *  a specified device address.
1846  */
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)1847 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1848 				u8 dev_addr, u8 *data)
1849 {
1850 	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1851 					       data, true);
1852 }
1853 
1854 /**
1855  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
1856  *  @hw: pointer to hardware structure
1857  *  @byte_offset: byte offset to read
1858  *  @data: value read
1859  *
1860  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1861  *  a specified device address.
1862  */
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)1863 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1864 					 u8 dev_addr, u8 *data)
1865 {
1866 	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1867 					       data, false);
1868 }
1869 
1870 /**
1871  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
1872  *  @hw: pointer to hardware structure
1873  *  @byte_offset: byte offset to write
1874  *  @data: value to write
1875  *  @lock: true if to take and release semaphore
1876  *
1877  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1878  *  a specified device address.
1879  */
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data,bool lock)1880 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1881 					    u8 dev_addr, u8 data, bool lock)
1882 {
1883 	s32 status;
1884 	u32 max_retry = 1;
1885 	u32 retry = 0;
1886 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
1887 
1888 	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1889 		return IXGBE_ERR_SWFW_SYNC;
1890 
1891 	do {
1892 		ixgbe_i2c_start(hw);
1893 
1894 		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1895 		if (status != 0)
1896 			goto fail;
1897 
1898 		status = ixgbe_get_i2c_ack(hw);
1899 		if (status != 0)
1900 			goto fail;
1901 
1902 		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1903 		if (status != 0)
1904 			goto fail;
1905 
1906 		status = ixgbe_get_i2c_ack(hw);
1907 		if (status != 0)
1908 			goto fail;
1909 
1910 		status = ixgbe_clock_out_i2c_byte(hw, data);
1911 		if (status != 0)
1912 			goto fail;
1913 
1914 		status = ixgbe_get_i2c_ack(hw);
1915 		if (status != 0)
1916 			goto fail;
1917 
1918 		ixgbe_i2c_stop(hw);
1919 		if (lock)
1920 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1921 		return 0;
1922 
1923 fail:
1924 		ixgbe_i2c_bus_clear(hw);
1925 		retry++;
1926 		if (retry < max_retry)
1927 			hw_dbg(hw, "I2C byte write error - Retrying.\n");
1928 		else
1929 			hw_dbg(hw, "I2C byte write error.\n");
1930 	} while (retry < max_retry);
1931 
1932 	if (lock)
1933 		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1934 
1935 	return status;
1936 }
1937 
1938 /**
1939  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1940  *  @hw: pointer to hardware structure
1941  *  @byte_offset: byte offset to write
1942  *  @data: value to write
1943  *
1944  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1945  *  a specified device address.
1946  */
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)1947 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1948 				 u8 dev_addr, u8 data)
1949 {
1950 	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1951 						data, true);
1952 }
1953 
1954 /**
1955  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
1956  *  @hw: pointer to hardware structure
1957  *  @byte_offset: byte offset to write
1958  *  @data: value to write
1959  *
1960  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1961  *  a specified device address.
1962  */
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)1963 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1964 					  u8 dev_addr, u8 data)
1965 {
1966 	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1967 						data, false);
1968 }
1969 
1970 /**
1971  *  ixgbe_i2c_start - Sets I2C start condition
1972  *  @hw: pointer to hardware structure
1973  *
1974  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1975  *  Set bit-bang mode on X550 hardware.
1976  **/
ixgbe_i2c_start(struct ixgbe_hw * hw)1977 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1978 {
1979 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
1980 
1981 	i2cctl |= IXGBE_I2C_BB_EN(hw);
1982 
1983 	/* Start condition must begin with data and clock high */
1984 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
1985 	ixgbe_raise_i2c_clk(hw, &i2cctl);
1986 
1987 	/* Setup time for start condition (4.7us) */
1988 	udelay(IXGBE_I2C_T_SU_STA);
1989 
1990 	ixgbe_set_i2c_data(hw, &i2cctl, 0);
1991 
1992 	/* Hold time for start condition (4us) */
1993 	udelay(IXGBE_I2C_T_HD_STA);
1994 
1995 	ixgbe_lower_i2c_clk(hw, &i2cctl);
1996 
1997 	/* Minimum low period of clock is 4.7 us */
1998 	udelay(IXGBE_I2C_T_LOW);
1999 
2000 }
2001 
2002 /**
2003  *  ixgbe_i2c_stop - Sets I2C stop condition
2004  *  @hw: pointer to hardware structure
2005  *
2006  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2007  *  Disables bit-bang mode and negates data output enable on X550
2008  *  hardware.
2009  **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2010 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2011 {
2012 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2013 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2014 	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2015 	u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2016 
2017 	/* Stop condition must begin with data low and clock high */
2018 	ixgbe_set_i2c_data(hw, &i2cctl, 0);
2019 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2020 
2021 	/* Setup time for stop condition (4us) */
2022 	udelay(IXGBE_I2C_T_SU_STO);
2023 
2024 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2025 
2026 	/* bus free time between stop and start (4.7us)*/
2027 	udelay(IXGBE_I2C_T_BUF);
2028 
2029 	if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2030 		i2cctl &= ~bb_en_bit;
2031 		i2cctl |= data_oe_bit | clk_oe_bit;
2032 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2033 		IXGBE_WRITE_FLUSH(hw);
2034 	}
2035 }
2036 
2037 /**
2038  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2039  *  @hw: pointer to hardware structure
2040  *  @data: data byte to clock in
2041  *
2042  *  Clocks in one byte data via I2C data/clock
2043  **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,u8 * data)2044 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2045 {
2046 	s32 i;
2047 	bool bit = false;
2048 
2049 	*data = 0;
2050 	for (i = 7; i >= 0; i--) {
2051 		ixgbe_clock_in_i2c_bit(hw, &bit);
2052 		*data |= bit << i;
2053 	}
2054 
2055 	return 0;
2056 }
2057 
2058 /**
2059  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2060  *  @hw: pointer to hardware structure
2061  *  @data: data byte clocked out
2062  *
2063  *  Clocks out one byte data via I2C data/clock
2064  **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,u8 data)2065 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2066 {
2067 	s32 status;
2068 	s32 i;
2069 	u32 i2cctl;
2070 	bool bit = false;
2071 
2072 	for (i = 7; i >= 0; i--) {
2073 		bit = (data >> i) & 0x1;
2074 		status = ixgbe_clock_out_i2c_bit(hw, bit);
2075 
2076 		if (status != 0)
2077 			break;
2078 	}
2079 
2080 	/* Release SDA line (set high) */
2081 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2082 	i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2083 	i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2084 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2085 	IXGBE_WRITE_FLUSH(hw);
2086 
2087 	return status;
2088 }
2089 
2090 /**
2091  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2092  *  @hw: pointer to hardware structure
2093  *
2094  *  Clocks in/out one bit via I2C data/clock
2095  **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2096 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2097 {
2098 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2099 	s32 status = 0;
2100 	u32 i = 0;
2101 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2102 	u32 timeout = 10;
2103 	bool ack = true;
2104 
2105 	if (data_oe_bit) {
2106 		i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2107 		i2cctl |= data_oe_bit;
2108 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2109 		IXGBE_WRITE_FLUSH(hw);
2110 	}
2111 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2112 
2113 	/* Minimum high period of clock is 4us */
2114 	udelay(IXGBE_I2C_T_HIGH);
2115 
2116 	/* Poll for ACK.  Note that ACK in I2C spec is
2117 	 * transition from 1 to 0 */
2118 	for (i = 0; i < timeout; i++) {
2119 		i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2120 		ack = ixgbe_get_i2c_data(hw, &i2cctl);
2121 
2122 		udelay(1);
2123 		if (ack == 0)
2124 			break;
2125 	}
2126 
2127 	if (ack == 1) {
2128 		hw_dbg(hw, "I2C ack was not received.\n");
2129 		status = IXGBE_ERR_I2C;
2130 	}
2131 
2132 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2133 
2134 	/* Minimum low period of clock is 4.7 us */
2135 	udelay(IXGBE_I2C_T_LOW);
2136 
2137 	return status;
2138 }
2139 
2140 /**
2141  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2142  *  @hw: pointer to hardware structure
2143  *  @data: read data value
2144  *
2145  *  Clocks in one bit via I2C data/clock
2146  **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2147 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2148 {
2149 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2150 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2151 
2152 	if (data_oe_bit) {
2153 		i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2154 		i2cctl |= data_oe_bit;
2155 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2156 		IXGBE_WRITE_FLUSH(hw);
2157 	}
2158 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2159 
2160 	/* Minimum high period of clock is 4us */
2161 	udelay(IXGBE_I2C_T_HIGH);
2162 
2163 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2164 	*data = ixgbe_get_i2c_data(hw, &i2cctl);
2165 
2166 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2167 
2168 	/* Minimum low period of clock is 4.7 us */
2169 	udelay(IXGBE_I2C_T_LOW);
2170 
2171 	return 0;
2172 }
2173 
2174 /**
2175  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2176  *  @hw: pointer to hardware structure
2177  *  @data: data value to write
2178  *
2179  *  Clocks out one bit via I2C data/clock
2180  **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2181 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2182 {
2183 	s32 status;
2184 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2185 
2186 	status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2187 	if (status == 0) {
2188 		ixgbe_raise_i2c_clk(hw, &i2cctl);
2189 
2190 		/* Minimum high period of clock is 4us */
2191 		udelay(IXGBE_I2C_T_HIGH);
2192 
2193 		ixgbe_lower_i2c_clk(hw, &i2cctl);
2194 
2195 		/* Minimum low period of clock is 4.7 us.
2196 		 * This also takes care of the data hold time.
2197 		 */
2198 		udelay(IXGBE_I2C_T_LOW);
2199 	} else {
2200 		hw_dbg(hw, "I2C data was not set to %X\n", data);
2201 		return IXGBE_ERR_I2C;
2202 	}
2203 
2204 	return 0;
2205 }
2206 /**
2207  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2208  *  @hw: pointer to hardware structure
2209  *  @i2cctl: Current value of I2CCTL register
2210  *
2211  *  Raises the I2C clock line '0'->'1'
2212  *  Negates the I2C clock output enable on X550 hardware.
2213  **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2214 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2215 {
2216 	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2217 	u32 i = 0;
2218 	u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2219 	u32 i2cctl_r = 0;
2220 
2221 	if (clk_oe_bit) {
2222 		*i2cctl |= clk_oe_bit;
2223 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2224 	}
2225 
2226 	for (i = 0; i < timeout; i++) {
2227 		*i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2228 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2229 		IXGBE_WRITE_FLUSH(hw);
2230 		/* SCL rise time (1000ns) */
2231 		udelay(IXGBE_I2C_T_RISE);
2232 
2233 		i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2234 		if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2235 			break;
2236 	}
2237 }
2238 
2239 /**
2240  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2241  *  @hw: pointer to hardware structure
2242  *  @i2cctl: Current value of I2CCTL register
2243  *
2244  *  Lowers the I2C clock line '1'->'0'
2245  *  Asserts the I2C clock output enable on X550 hardware.
2246  **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2247 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2248 {
2249 
2250 	*i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2251 	*i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2252 
2253 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2254 	IXGBE_WRITE_FLUSH(hw);
2255 
2256 	/* SCL fall time (300ns) */
2257 	udelay(IXGBE_I2C_T_FALL);
2258 }
2259 
2260 /**
2261  *  ixgbe_set_i2c_data - Sets the I2C data bit
2262  *  @hw: pointer to hardware structure
2263  *  @i2cctl: Current value of I2CCTL register
2264  *  @data: I2C data value (0 or 1) to set
2265  *
2266  *  Sets the I2C data bit
2267  *  Asserts the I2C data output enable on X550 hardware.
2268  **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl,bool data)2269 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2270 {
2271 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2272 
2273 	if (data)
2274 		*i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2275 	else
2276 		*i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2277 	*i2cctl &= ~data_oe_bit;
2278 
2279 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2280 	IXGBE_WRITE_FLUSH(hw);
2281 
2282 	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2283 	udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2284 
2285 	if (!data)	/* Can't verify data in this case */
2286 		return 0;
2287 	if (data_oe_bit) {
2288 		*i2cctl |= data_oe_bit;
2289 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2290 		IXGBE_WRITE_FLUSH(hw);
2291 	}
2292 
2293 	/* Verify data was set correctly */
2294 	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2295 	if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2296 		hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2297 		return IXGBE_ERR_I2C;
2298 	}
2299 
2300 	return 0;
2301 }
2302 
2303 /**
2304  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2305  *  @hw: pointer to hardware structure
2306  *  @i2cctl: Current value of I2CCTL register
2307  *
2308  *  Returns the I2C data bit value
2309  *  Negates the I2C data output enable on X550 hardware.
2310  **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl)2311 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2312 {
2313 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2314 
2315 	if (data_oe_bit) {
2316 		*i2cctl |= data_oe_bit;
2317 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2318 		IXGBE_WRITE_FLUSH(hw);
2319 		udelay(IXGBE_I2C_T_FALL);
2320 	}
2321 
2322 	if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2323 		return true;
2324 	return false;
2325 }
2326 
2327 /**
2328  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2329  *  @hw: pointer to hardware structure
2330  *
2331  *  Clears the I2C bus by sending nine clock pulses.
2332  *  Used when data line is stuck low.
2333  **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2334 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2335 {
2336 	u32 i2cctl;
2337 	u32 i;
2338 
2339 	ixgbe_i2c_start(hw);
2340 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2341 
2342 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2343 
2344 	for (i = 0; i < 9; i++) {
2345 		ixgbe_raise_i2c_clk(hw, &i2cctl);
2346 
2347 		/* Min high period of clock is 4us */
2348 		udelay(IXGBE_I2C_T_HIGH);
2349 
2350 		ixgbe_lower_i2c_clk(hw, &i2cctl);
2351 
2352 		/* Min low period of clock is 4.7us*/
2353 		udelay(IXGBE_I2C_T_LOW);
2354 	}
2355 
2356 	ixgbe_i2c_start(hw);
2357 
2358 	/* Put the i2c bus back to default state */
2359 	ixgbe_i2c_stop(hw);
2360 }
2361 
2362 /**
2363  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2364  *  @hw: pointer to hardware structure
2365  *
2366  *  Checks if the LASI temp alarm status was triggered due to overtemp
2367  **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2368 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2369 {
2370 	u16 phy_data = 0;
2371 
2372 	if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2373 		return 0;
2374 
2375 	/* Check that the LASI temp alarm status was triggered */
2376 	hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2377 			     MDIO_MMD_PMAPMD, &phy_data);
2378 
2379 	if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2380 		return 0;
2381 
2382 	return IXGBE_ERR_OVERTEMP;
2383 }
2384 
2385 /** ixgbe_set_copper_phy_power - Control power for copper phy
2386  *  @hw: pointer to hardware structure
2387  *  @on: true for on, false for off
2388  **/
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2389 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2390 {
2391 	u32 status;
2392 	u16 reg;
2393 
2394 	/* Bail if we don't have copper phy */
2395 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2396 		return 0;
2397 
2398 	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2399 				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2400 				      &reg);
2401 	if (status)
2402 		return status;
2403 
2404 	if (on) {
2405 		reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2406 	} else {
2407 		if (ixgbe_check_reset_blocked(hw))
2408 			return 0;
2409 		reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2410 	}
2411 
2412 	status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2413 				       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2414 				       reg);
2415 	return status;
2416 }
2417