| /drivers/gpu/drm/i915/ |
| D | intel_dp_mst.c | 34 struct intel_crtc_state *pipe_config) in intel_dp_mst_compute_config() argument
43 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_mst_compute_config()
49 pipe_config->dp_encoder_is_mst = true; in intel_dp_mst_compute_config()
50 pipe_config->has_pch_encoder = false; in intel_dp_mst_compute_config()
51 pipe_config->has_dp_encoder = true; in intel_dp_mst_compute_config()
60 pipe_config->lane_count = lane_count; in intel_dp_mst_compute_config()
62 pipe_config->pipe_bpp = 24; in intel_dp_mst_compute_config()
63 pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); in intel_dp_mst_compute_config()
65 state = pipe_config->base.state; in intel_dp_mst_compute_config()
83 pipe_config->pbn = mst_pbn; in intel_dp_mst_compute_config()
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| D | intel_display.c | 89 struct intel_crtc_state *pipe_config);
91 struct intel_crtc_state *pipe_config);
106 const struct intel_crtc_state *pipe_config);
108 const struct intel_crtc_state *pipe_config);
1599 const struct intel_crtc_state *pipe_config) in vlv_enable_pll() argument
1604 u32 dpll = pipe_config->dpll_hw_state.dpll; in vlv_enable_pll()
1622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1638 const struct intel_crtc_state *pipe_config) in chv_enable_pll() argument
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1672 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
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| D | intel_crt.c | 114 struct intel_crtc_state *pipe_config) in intel_crt_get_config() argument
119 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
121 dotclock = pipe_config->port_clock; in intel_crt_get_config()
124 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_crt_get_config()
126 pipe_config->base.adjusted_mode.crtc_clock = dotclock; in intel_crt_get_config()
130 struct intel_crtc_state *pipe_config) in hsw_crt_get_config() argument
132 intel_ddi_get_config(encoder, pipe_config); in hsw_crt_get_config()
134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
243 struct intel_crtc_state *pipe_config) in intel_crt_compute_config() argument
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| D | intel_panel.c | 105 struct intel_crtc_state *pipe_config, in intel_pch_panel_fitting() argument
108 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_pch_panel_fitting()
112 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && in intel_pch_panel_fitting()
113 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) in intel_pch_panel_fitting()
118 width = pipe_config->pipe_src_w; in intel_pch_panel_fitting()
119 height = pipe_config->pipe_src_h; in intel_pch_panel_fitting()
128 * pipe_config->pipe_src_h; in intel_pch_panel_fitting()
129 u32 scaled_height = pipe_config->pipe_src_w in intel_pch_panel_fitting()
132 width = scaled_height / pipe_config->pipe_src_h; in intel_pch_panel_fitting()
139 height = scaled_width / pipe_config->pipe_src_w; in intel_pch_panel_fitting()
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| D | intel_ddi.c | 1035 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) in ddi_dotclock_get() argument
1039 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
1040 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1041 &pipe_config->fdi_m_n); in ddi_dotclock_get()
1042 else if (pipe_config->has_dp_encoder) in ddi_dotclock_get()
1043 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1044 &pipe_config->dp_m_n); in ddi_dotclock_get()
1045 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) in ddi_dotclock_get()
1046 dotclock = pipe_config->port_clock * 2 / 3; in ddi_dotclock_get()
1048 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
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| D | intel_lvds.c | 97 struct intel_crtc_state *pipe_config) in intel_lvds_get_config() argument
115 pipe_config->base.adjusted_mode.flags |= flags; in intel_lvds_get_config()
121 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
124 dotclock = pipe_config->port_clock; in intel_lvds_get_config()
127 ironlake_check_encoder_dotclock(pipe_config, dotclock); in intel_lvds_get_config()
129 pipe_config->base.adjusted_mode.crtc_clock = dotclock; in intel_lvds_get_config()
300 struct intel_crtc_state *pipe_config) in intel_lvds_compute_config() argument
307 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_lvds_compute_config()
308 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); in intel_lvds_compute_config()
322 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
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| D | intel_hdmi.c | 905 struct intel_crtc_state *pipe_config) in intel_hdmi_get_config() argument
926 pipe_config->has_hdmi_sink = true; in intel_hdmi_get_config()
929 pipe_config->has_infoframe = true; in intel_hdmi_get_config()
932 pipe_config->has_audio = true; in intel_hdmi_get_config()
936 pipe_config->limited_color_range = true; in intel_hdmi_get_config()
938 pipe_config->base.adjusted_mode.flags |= flags; in intel_hdmi_get_config()
941 dotclock = pipe_config->port_clock * 2 / 3; in intel_hdmi_get_config()
943 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
945 if (pipe_config->pixel_multiplier) in intel_hdmi_get_config()
946 dotclock /= pipe_config->pixel_multiplier; in intel_hdmi_get_config()
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| D | intel_dp.c | 1112 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) in skl_edp_set_pll_config() argument
1116 memset(&pipe_config->dpll_hw_state, 0, in skl_edp_set_pll_config()
1117 sizeof(pipe_config->dpll_hw_state)); in skl_edp_set_pll_config()
1119 pipe_config->ddi_pll_sel = SKL_DPLL0; in skl_edp_set_pll_config()
1120 pipe_config->dpll_hw_state.cfgcr1 = 0; in skl_edp_set_pll_config()
1121 pipe_config->dpll_hw_state.cfgcr2 = 0; in skl_edp_set_pll_config()
1124 switch (pipe_config->port_clock / 2) { in skl_edp_set_pll_config()
1154 pipe_config->dpll_hw_state.ctrl1 = ctrl1; in skl_edp_set_pll_config()
1158 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) in hsw_dp_set_ddi_pll_sel() argument
1160 memset(&pipe_config->dpll_hw_state, 0, in hsw_dp_set_ddi_pll_sel()
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| D | intel_sdvo.c | 1102 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) in i9xx_adjust_sdvo_tv_clock() argument
1104 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1105 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
1125 pipe_config->clock_set = true; in i9xx_adjust_sdvo_tv_clock()
1129 struct intel_crtc_state *pipe_config) in intel_sdvo_compute_config() argument
1132 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_sdvo_compute_config()
1133 struct drm_display_mode *mode = &pipe_config->base.mode; in intel_sdvo_compute_config()
1136 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
1139 pipe_config->has_pch_encoder = true; in intel_sdvo_compute_config()
1153 pipe_config->sdvo_tv_clock = true; in intel_sdvo_compute_config()
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| D | intel_dvo.c | 149 struct intel_crtc_state *pipe_config) in intel_dvo_get_config() argument
165 pipe_config->base.adjusted_mode.flags |= flags; in intel_dvo_get_config()
167 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
231 struct intel_crtc_state *pipe_config) in intel_dvo_compute_config() argument
236 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dvo_compute_config()
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| D | intel_drv.h | 155 struct intel_crtc_state *pipe_config);
993 struct intel_crtc_state *pipe_config);
999 struct intel_crtc_state *pipe_config);
1155 struct intel_crtc_state *pipe_config);
1159 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1173 struct intel_crtc_state *pipe_config);
1202 const struct intel_crtc_state *pipe_config);
1211 struct intel_crtc_state *pipe_config);
1234 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1298 struct intel_crtc_state *pipe_config);
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| D | intel_tv.c | 912 struct intel_crtc_state *pipe_config) in intel_tv_get_config() argument
914 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_tv_get_config()
919 struct intel_crtc_state *pipe_config) in intel_tv_compute_config() argument
927 pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock; in intel_tv_compute_config()
929 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
932 pipe_config->base.adjusted_mode.flags = 0; in intel_tv_compute_config()
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| D | intel_dsi.c | 696 struct intel_crtc_state *pipe_config) in intel_dsi_get_config() argument
705 pipe_config->dpll_hw_state.dpll_md = 0; in intel_dsi_get_config()
708 pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); in intel_dsi_get_config()
710 pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); in intel_dsi_get_config()
715 pipe_config->base.adjusted_mode.crtc_clock = pclk; in intel_dsi_get_config()
716 pipe_config->port_clock = pclk; in intel_dsi_get_config()
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| D | i915_debugfs.c | 2963 struct intel_crtc_state *pipe_config; in i915_display_info() local
2966 pipe_config = to_intel_crtc_state(crtc->base.state); in i915_display_info()
2970 yesno(pipe_config->base.active), in i915_display_info()
2971 pipe_config->pipe_src_w, pipe_config->pipe_src_h); in i915_display_info()
2972 if (pipe_config->base.active) { in i915_display_info()
3807 struct intel_crtc_state *pipe_config; in hsw_trans_edp_pipe_A_crc_wa() local
3819 pipe_config = intel_atomic_get_crtc_state(state, crtc); in hsw_trans_edp_pipe_A_crc_wa()
3820 if (IS_ERR(pipe_config)) { in hsw_trans_edp_pipe_A_crc_wa()
3821 ret = PTR_ERR(pipe_config); in hsw_trans_edp_pipe_A_crc_wa()
3825 pipe_config->pch_pfit.force_thru = enable; in hsw_trans_edp_pipe_A_crc_wa()
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| D | intel_pm.c | 1652 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) in ilk_pipe_pixel_rate() argument
1656 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; in ilk_pipe_pixel_rate()
1661 if (pipe_config->pch_pfit.enabled) { in ilk_pipe_pixel_rate()
1663 uint32_t pfit_size = pipe_config->pch_pfit.size; in ilk_pipe_pixel_rate()
1665 pipe_w = pipe_config->pipe_src_w; in ilk_pipe_pixel_rate()
1666 pipe_h = pipe_config->pipe_src_h; in ilk_pipe_pixel_rate()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v8_0.c | 2007 u32 pipe_config; in dce_v8_0_crtc_do_set_base() local
2049 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
2141 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); in dce_v8_0_crtc_do_set_base()
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| D | dce_v10_0.c | 2043 u32 pipe_config; in dce_v10_0_crtc_do_set_base() local
2085 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
2190 pipe_config); in dce_v10_0_crtc_do_set_base()
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| D | dce_v11_0.c | 2031 u32 pipe_config; in dce_v11_0_crtc_do_set_base() local
2073 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2178 pipe_config); in dce_v11_0_crtc_do_set_base()
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| /drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1343 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base() local
1345 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); in dce4_crtc_do_set_base()
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