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Searched refs:read_csr (Results 1 – 16 of 16) sorted by relevance

/drivers/staging/rdma/hfi1/
Deprom.c110 read_csr(dd, ASIC_GPIO_OUT) | EPROM_WP_N); in write_enable()
113 read_csr(dd, ASIC_GPIO_OE) | EPROM_WP_N); in write_enable()
123 read_csr(dd, ASIC_GPIO_OUT) & ~EPROM_WP_N); in write_disable()
126 read_csr(dd, ASIC_GPIO_OE) & ~EPROM_WP_N); in write_disable()
145 reg = read_csr(dd, ASIC_EEP_DATA); in wait_for_not_busy()
169 return (u32)read_csr(dd, ASIC_EEP_DATA); in read_device_id()
234 result[i] = (u32)read_csr(dd, ASIC_EEP_DATA); in read_page()
Dfirmware.c258 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in __read_8051_data()
270 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); in __read_8051_data()
343 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) in write_8051()
703 status = (read_csr(dd, MISC_CFG_FW_CTRL) in run_rsa()
738 status = (read_csr(dd, MISC_CFG_FW_CTRL) in run_rsa()
785 reg = read_csr(dd, MISC_ERR_STATUS); in run_rsa()
814 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); in get_firmware_state()
1010 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); in sbus_request_slow()
1014 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS); in sbus_request_slow()
1027 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); in sbus_request_slow()
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Dintr.c139 read_csr(dd, in handle_linkup_change()
142 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) & in handle_linkup_change()
145 read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) & in handle_linkup_change()
Dchip.c1250 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) in read_csr() function
1281 ret = read_csr(dd, csr); in read_write_csr()
2312 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ in handle_send_egress_err_info()
2313 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); in handle_send_egress_err_info()
2831 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); in handle_8051_request()
2960 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); in lcb_shutdown()
2961 reg = read_csr(dd, DCC_CFG_RESET); in lcb_shutdown()
2966 (void) read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ in lcb_shutdown()
3180 rcvctrl = read_csr(dd, RCV_CTRL); in adjust_rcvctrl()
3248 reg = read_csr(dd, CCE_STATUS); in wait_for_freeze_status()
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Dpcie.c211 dd->chip_rcv_array_count = read_csr(dd, RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
865 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); in arm_gasket_logic()
942 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); in do_pcie_gen3_transition()
1133 (void) read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ in do_pcie_gen3_transition()
1135 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); in do_pcie_gen3_transition()
1192 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); in do_pcie_gen3_transition()
Dchip.h552 u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
564 return read_csr(dd, offset0 + (0x100 * ctxt)); in read_kctxt_csr()
599 return read_csr(dd, offset0 + (0x1000 * ctxt)); in read_uctxt_csr()
Dpio.c73 sendctrl = read_csr(dd, SEND_CTRL); in __cm_reset()
97 reg = read_csr(dd, SEND_CTRL); in pio_send_control()
133 (void) read_csr(dd, SEND_CTRL); /* flush write */ in pio_send_control()
931 reg = read_csr(dd, sc->hw_context * 8 + in sc_wait_for_packet_egress()
1125 reg = read_csr(dd, SEND_PIO_INIT_CTXT); in pio_init_wait_progress()
Dqsfp.c409 reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN); in qsfp_mod_present()
Dmad.c1443 *val++ = read_csr(dd, SEND_SC2VLT0); in get_sc2vlt_tables()
1444 *val++ = read_csr(dd, SEND_SC2VLT1); in get_sc2vlt_tables()
1445 *val++ = read_csr(dd, SEND_SC2VLT2); in get_sc2vlt_tables()
1446 *val++ = read_csr(dd, SEND_SC2VLT3); in get_sc2vlt_tables()
2893 reg = read_csr(dd, RCV_ERR_INFO); in pma_get_opa_errorinfo()
3466 reg = read_csr(dd, DCC_CFG_LED_CNTRL); in __subn_get_opa_led_info()
Dsdma.c317 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); in sdma_wait_for_packet_egress()
1758 csr = read_csr(sde->dd, reg); \
1769 csr = read_csr(sde->dd, reg + (8 * i)); \
Ddiag.c708 dd->hfi1_snoop.dcc_cfg = read_csr(dd, DCC_CFG_PORT_CONFIG1); in hfi1_snoop_open()
/drivers/net/ethernet/amd/
Dpcnet32.c246 u16 (*read_csr) (unsigned long, int); member
383 .read_csr = pcnet32_wio_read_csr,
438 .read_csr = pcnet32_dwio_read_csr,
463 val = lp->a->read_csr(ioaddr, CSR3); in pcnet32_netif_start()
957 x = a->read_csr(ioaddr, CSR15) & 0xfffc; in pcnet32_loopback_test()
1015 x = a->read_csr(ioaddr, CSR15); in pcnet32_loopback_test()
1087 csr5 = a->read_csr(ioaddr, CSR5); in pcnet32_suspend()
1092 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { in pcnet32_suspend()
1359 val = lp->a->read_csr(ioaddr, CSR3); in pcnet32_poll()
1393 csr0 = a->read_csr(ioaddr, CSR0); in pcnet32_get_regs()
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/drivers/firewire/
Dcore.h90 u32 (*read_csr)(struct fw_card *card, int csr_offset); member
Dcore-transaction.c1118 *data = cpu_to_be32(card->driver->read_csr(card, reg)); in handle_registers()
Dcore-cdev.c1214 cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME); in ioctl_get_cycle_timer2()
Dohci.c3524 .read_csr = ohci_read_csr,