1 /*
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2015 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2015 Intel Corporation.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 *
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
32 * distribution.
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50 #include <linux/delay.h>
51 #include "hfi.h"
52 #include "common.h"
53 #include "eprom.h"
54
55 /*
56 * The EPROM is logically divided into two partitions:
57 * partition 0: the first 128K, visible from PCI ROM BAR
58 * partition 1: the rest
59 */
60 #define P0_SIZE (128 * 1024)
61 #define P1_START P0_SIZE
62
63 /* largest erase size supported by the controller */
64 #define SIZE_32KB (32 * 1024)
65 #define MASK_32KB (SIZE_32KB - 1)
66
67 /* controller page size, in bytes */
68 #define EP_PAGE_SIZE 256
69 #define EEP_PAGE_MASK (EP_PAGE_SIZE - 1)
70
71 /* controller commands */
72 #define CMD_SHIFT 24
73 #define CMD_NOP (0)
74 #define CMD_PAGE_PROGRAM(addr) ((0x02 << CMD_SHIFT) | addr)
75 #define CMD_READ_DATA(addr) ((0x03 << CMD_SHIFT) | addr)
76 #define CMD_READ_SR1 ((0x05 << CMD_SHIFT))
77 #define CMD_WRITE_ENABLE ((0x06 << CMD_SHIFT))
78 #define CMD_SECTOR_ERASE_32KB(addr) ((0x52 << CMD_SHIFT) | addr)
79 #define CMD_CHIP_ERASE ((0x60 << CMD_SHIFT))
80 #define CMD_READ_MANUF_DEV_ID ((0x90 << CMD_SHIFT))
81 #define CMD_RELEASE_POWERDOWN_NOID ((0xab << CMD_SHIFT))
82
83 /* controller interface speeds */
84 #define EP_SPEED_FULL 0x2 /* full speed */
85
86 /* controller status register 1 bits */
87 #define SR1_BUSY 0x1ull /* the BUSY bit in SR1 */
88
89 /* sleep length while waiting for controller */
90 #define WAIT_SLEEP_US 100 /* must be larger than 5 (see usage) */
91 #define COUNT_DELAY_SEC(n) ((n) * (1000000/WAIT_SLEEP_US))
92
93 /* GPIO pins */
94 #define EPROM_WP_N (1ull << 14) /* EPROM write line */
95
96 /*
97 * Use the EP mutex to guard against other callers from within the driver.
98 * Also covers usage of eprom_available.
99 */
100 static DEFINE_MUTEX(eprom_mutex);
101 static int eprom_available; /* default: not available */
102
103 /*
104 * Turn on external enable line that allows writing on the flash.
105 */
write_enable(struct hfi1_devdata * dd)106 static void write_enable(struct hfi1_devdata *dd)
107 {
108 /* raise signal */
109 write_csr(dd, ASIC_GPIO_OUT,
110 read_csr(dd, ASIC_GPIO_OUT) | EPROM_WP_N);
111 /* raise enable */
112 write_csr(dd, ASIC_GPIO_OE,
113 read_csr(dd, ASIC_GPIO_OE) | EPROM_WP_N);
114 }
115
116 /*
117 * Turn off external enable line that allows writing on the flash.
118 */
write_disable(struct hfi1_devdata * dd)119 static void write_disable(struct hfi1_devdata *dd)
120 {
121 /* lower signal */
122 write_csr(dd, ASIC_GPIO_OUT,
123 read_csr(dd, ASIC_GPIO_OUT) & ~EPROM_WP_N);
124 /* lower enable */
125 write_csr(dd, ASIC_GPIO_OE,
126 read_csr(dd, ASIC_GPIO_OE) & ~EPROM_WP_N);
127 }
128
129 /*
130 * Wait for the device to become not busy. Must be called after all
131 * write or erase operations.
132 */
wait_for_not_busy(struct hfi1_devdata * dd)133 static int wait_for_not_busy(struct hfi1_devdata *dd)
134 {
135 unsigned long count = 0;
136 u64 reg;
137 int ret = 0;
138
139 /* starts page mode */
140 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_SR1);
141 while (1) {
142 udelay(WAIT_SLEEP_US);
143 usleep_range(WAIT_SLEEP_US - 5, WAIT_SLEEP_US + 5);
144 count++;
145 reg = read_csr(dd, ASIC_EEP_DATA);
146 if ((reg & SR1_BUSY) == 0)
147 break;
148 /* 200s is the largest time for a 128Mb device */
149 if (count > COUNT_DELAY_SEC(200)) {
150 dd_dev_err(dd, "waited too long for SPI FLASH busy to clear - failing\n");
151 ret = -ETIMEDOUT;
152 break; /* break, not goto - must stop page mode */
153 }
154 }
155
156 /* stop page mode with a NOP */
157 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP);
158
159 return ret;
160 }
161
162 /*
163 * Read the device ID from the SPI controller.
164 */
read_device_id(struct hfi1_devdata * dd)165 static u32 read_device_id(struct hfi1_devdata *dd)
166 {
167 /* read the Manufacture Device ID */
168 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_MANUF_DEV_ID);
169 return (u32)read_csr(dd, ASIC_EEP_DATA);
170 }
171
172 /*
173 * Erase the whole flash.
174 */
erase_chip(struct hfi1_devdata * dd)175 static int erase_chip(struct hfi1_devdata *dd)
176 {
177 int ret;
178
179 write_enable(dd);
180
181 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
182 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_CHIP_ERASE);
183 ret = wait_for_not_busy(dd);
184
185 write_disable(dd);
186
187 return ret;
188 }
189
190 /*
191 * Erase a range using the 32KB erase command.
192 */
erase_32kb_range(struct hfi1_devdata * dd,u32 start,u32 end)193 static int erase_32kb_range(struct hfi1_devdata *dd, u32 start, u32 end)
194 {
195 int ret = 0;
196
197 if (end < start)
198 return -EINVAL;
199
200 if ((start & MASK_32KB) || (end & MASK_32KB)) {
201 dd_dev_err(dd,
202 "%s: non-aligned range (0x%x,0x%x) for a 32KB erase\n",
203 __func__, start, end);
204 return -EINVAL;
205 }
206
207 write_enable(dd);
208
209 for (; start < end; start += SIZE_32KB) {
210 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
211 write_csr(dd, ASIC_EEP_ADDR_CMD,
212 CMD_SECTOR_ERASE_32KB(start));
213 ret = wait_for_not_busy(dd);
214 if (ret)
215 goto done;
216 }
217
218 done:
219 write_disable(dd);
220
221 return ret;
222 }
223
224 /*
225 * Read a 256 byte (64 dword) EPROM page.
226 * All callers have verified the offset is at a page boundary.
227 */
read_page(struct hfi1_devdata * dd,u32 offset,u32 * result)228 static void read_page(struct hfi1_devdata *dd, u32 offset, u32 *result)
229 {
230 int i;
231
232 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset));
233 for (i = 0; i < EP_PAGE_SIZE/sizeof(u32); i++)
234 result[i] = (u32)read_csr(dd, ASIC_EEP_DATA);
235 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */
236 }
237
238 /*
239 * Read length bytes starting at offset. Copy to user address addr.
240 */
read_length(struct hfi1_devdata * dd,u32 start,u32 len,u64 addr)241 static int read_length(struct hfi1_devdata *dd, u32 start, u32 len, u64 addr)
242 {
243 u32 offset;
244 u32 buffer[EP_PAGE_SIZE/sizeof(u32)];
245 int ret = 0;
246
247 /* reject anything not on an EPROM page boundary */
248 if ((start & EEP_PAGE_MASK) || (len & EEP_PAGE_MASK))
249 return -EINVAL;
250
251 for (offset = 0; offset < len; offset += EP_PAGE_SIZE) {
252 read_page(dd, start + offset, buffer);
253 if (copy_to_user((void __user *)(addr + offset),
254 buffer, EP_PAGE_SIZE)) {
255 ret = -EFAULT;
256 goto done;
257 }
258 }
259
260 done:
261 return ret;
262 }
263
264 /*
265 * Write a 256 byte (64 dword) EPROM page.
266 * All callers have verified the offset is at a page boundary.
267 */
write_page(struct hfi1_devdata * dd,u32 offset,u32 * data)268 static int write_page(struct hfi1_devdata *dd, u32 offset, u32 *data)
269 {
270 int i;
271
272 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE);
273 write_csr(dd, ASIC_EEP_DATA, data[0]);
274 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_PAGE_PROGRAM(offset));
275 for (i = 1; i < EP_PAGE_SIZE/sizeof(u32); i++)
276 write_csr(dd, ASIC_EEP_DATA, data[i]);
277 /* will close the open page */
278 return wait_for_not_busy(dd);
279 }
280
281 /*
282 * Write length bytes starting at offset. Read from user address addr.
283 */
write_length(struct hfi1_devdata * dd,u32 start,u32 len,u64 addr)284 static int write_length(struct hfi1_devdata *dd, u32 start, u32 len, u64 addr)
285 {
286 u32 offset;
287 u32 buffer[EP_PAGE_SIZE/sizeof(u32)];
288 int ret = 0;
289
290 /* reject anything not on an EPROM page boundary */
291 if ((start & EEP_PAGE_MASK) || (len & EEP_PAGE_MASK))
292 return -EINVAL;
293
294 write_enable(dd);
295
296 for (offset = 0; offset < len; offset += EP_PAGE_SIZE) {
297 if (copy_from_user(buffer, (void __user *)(addr + offset),
298 EP_PAGE_SIZE)) {
299 ret = -EFAULT;
300 goto done;
301 }
302 ret = write_page(dd, start + offset, buffer);
303 if (ret)
304 goto done;
305 }
306
307 done:
308 write_disable(dd);
309 return ret;
310 }
311
312 /*
313 * Perform the given operation on the EPROM. Called from user space. The
314 * user credentials have already been checked.
315 *
316 * Return 0 on success, -ERRNO on error
317 */
handle_eprom_command(const struct hfi1_cmd * cmd)318 int handle_eprom_command(const struct hfi1_cmd *cmd)
319 {
320 struct hfi1_devdata *dd;
321 u32 dev_id;
322 int ret = 0;
323
324 /*
325 * The EPROM is per-device, so use unit 0 as that will always
326 * exist.
327 */
328 dd = hfi1_lookup(0);
329 if (!dd) {
330 pr_err("%s: cannot find unit 0!\n", __func__);
331 return -EINVAL;
332 }
333
334 /* lock against other callers touching the ASIC block */
335 mutex_lock(&eprom_mutex);
336
337 /* some platforms do not have an EPROM */
338 if (!eprom_available) {
339 ret = -ENOSYS;
340 goto done_asic;
341 }
342
343 /* lock against the other HFI on another OS */
344 ret = acquire_hw_mutex(dd);
345 if (ret) {
346 dd_dev_err(dd,
347 "%s: unable to acquire hw mutex, no EPROM support\n",
348 __func__);
349 goto done_asic;
350 }
351
352 dd_dev_info(dd, "%s: cmd: type %d, len 0x%x, addr 0x%016llx\n",
353 __func__, cmd->type, cmd->len, cmd->addr);
354
355 switch (cmd->type) {
356 case HFI1_CMD_EP_INFO:
357 if (cmd->len != sizeof(u32)) {
358 ret = -ERANGE;
359 break;
360 }
361 dev_id = read_device_id(dd);
362 /* addr points to a u32 user buffer */
363 if (copy_to_user((void __user *)cmd->addr, &dev_id,
364 sizeof(u32)))
365 ret = -EFAULT;
366 break;
367 case HFI1_CMD_EP_ERASE_CHIP:
368 ret = erase_chip(dd);
369 break;
370 case HFI1_CMD_EP_ERASE_P0:
371 if (cmd->len != P0_SIZE) {
372 ret = -ERANGE;
373 break;
374 }
375 ret = erase_32kb_range(dd, 0, cmd->len);
376 break;
377 case HFI1_CMD_EP_ERASE_P1:
378 /* check for overflow */
379 if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
380 ret = -ERANGE;
381 break;
382 }
383 ret = erase_32kb_range(dd, P1_START, P1_START + cmd->len);
384 break;
385 case HFI1_CMD_EP_READ_P0:
386 if (cmd->len != P0_SIZE) {
387 ret = -ERANGE;
388 break;
389 }
390 ret = read_length(dd, 0, cmd->len, cmd->addr);
391 break;
392 case HFI1_CMD_EP_READ_P1:
393 /* check for overflow */
394 if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
395 ret = -ERANGE;
396 break;
397 }
398 ret = read_length(dd, P1_START, cmd->len, cmd->addr);
399 break;
400 case HFI1_CMD_EP_WRITE_P0:
401 if (cmd->len > P0_SIZE) {
402 ret = -ERANGE;
403 break;
404 }
405 ret = write_length(dd, 0, cmd->len, cmd->addr);
406 break;
407 case HFI1_CMD_EP_WRITE_P1:
408 /* check for overflow */
409 if (P1_START + cmd->len > ASIC_EEP_ADDR_CMD_EP_ADDR_MASK) {
410 ret = -ERANGE;
411 break;
412 }
413 ret = write_length(dd, P1_START, cmd->len, cmd->addr);
414 break;
415 default:
416 dd_dev_err(dd, "%s: unexpected command %d\n",
417 __func__, cmd->type);
418 ret = -EINVAL;
419 break;
420 }
421
422 release_hw_mutex(dd);
423 done_asic:
424 mutex_unlock(&eprom_mutex);
425 return ret;
426 }
427
428 /*
429 * Initialize the EPROM handler.
430 */
eprom_init(struct hfi1_devdata * dd)431 int eprom_init(struct hfi1_devdata *dd)
432 {
433 int ret = 0;
434
435 /* only the discrete chip has an EPROM, nothing to do */
436 if (dd->pcidev->device != PCI_DEVICE_ID_INTEL0)
437 return 0;
438
439 /* lock against other callers */
440 mutex_lock(&eprom_mutex);
441 if (eprom_available) /* already initialized */
442 goto done_asic;
443
444 /*
445 * Lock against the other HFI on another OS - the mutex above
446 * would have caught anything in this driver. It is OK if
447 * both OSes reset the EPROM - as long as they don't do it at
448 * the same time.
449 */
450 ret = acquire_hw_mutex(dd);
451 if (ret) {
452 dd_dev_err(dd,
453 "%s: unable to acquire hw mutex, no EPROM support\n",
454 __func__);
455 goto done_asic;
456 }
457
458 /* reset EPROM to be sure it is in a good state */
459
460 /* set reset */
461 write_csr(dd, ASIC_EEP_CTL_STAT,
462 ASIC_EEP_CTL_STAT_EP_RESET_SMASK);
463 /* clear reset, set speed */
464 write_csr(dd, ASIC_EEP_CTL_STAT,
465 EP_SPEED_FULL << ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT);
466
467 /* wake the device with command "release powerdown NoID" */
468 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID);
469
470 eprom_available = 1;
471 release_hw_mutex(dd);
472 done_asic:
473 mutex_unlock(&eprom_mutex);
474 return ret;
475 }
476