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Searched refs:reg_write (Results 1 – 25 of 46) sorted by relevance

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/drivers/media/i2c/soc_camera/
Dimx074.c105 static int reg_write(struct i2c_client *client, const u16 addr, const u8 data) in reg_write() function
256 return reg_write(client, MODE_SELECT, !!enable); in imx074_s_stream()
333 reg_write(client, PLL_MULTIPLIER, 0x2D); in imx074_video_probe()
334 reg_write(client, PRE_PLL_CLK_DIV, 0x02); in imx074_video_probe()
335 reg_write(client, PLSTATIM, 0x4B); in imx074_video_probe()
338 reg_write(client, 0x3024, 0x00); in imx074_video_probe()
340 reg_write(client, IMAGE_ORIENTATION, 0x00); in imx074_video_probe()
347 reg_write(client, 0x0112, 0x08); in imx074_video_probe()
348 reg_write(client, 0x0113, 0x08); in imx074_video_probe()
351 reg_write(client, VNDMY_ABLMGSHLMT, 0x80); in imx074_video_probe()
[all …]
Drj54n1cb0c.c444 static int reg_write(struct i2c_client *client, const u16 reg, in reg_write() function
470 return reg_write(client, reg, (ret & ~mask) | (data & mask)); in reg_set()
479 ret = reg_write(client, rv->reg, rv->val); in reg_write_multiple()
513 ret = reg_write(client, reg_xy, in rj54n1_set_rect()
518 ret = reg_write(client, reg_x, width & 0xff); in rj54n1_set_rect()
520 ret = reg_write(client, reg_y, height & 0xff); in rj54n1_set_rect()
531 int ret = reg_write(client, RJ54N1_INIT_START, 1); in rj54n1_commit()
534 ret = reg_write(client, RJ54N1_INIT_START, 0); in rj54n1_commit()
718 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff); in rj54n1_sensor_scale()
720 ret = reg_write(client, RJ54N1_RESIZE_HOLD_H, resize >> 8); in rj54n1_sensor_scale()
[all …]
Dmt9v022.c178 static int reg_write(struct i2c_client *client, const u8 reg, in reg_write() function
192 return reg_write(client, reg, ret | data); in reg_set()
203 return reg_write(client, reg, ret & ~data); in reg_clear()
217 ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control); in mt9v022_init()
219 ret = reg_write(client, MT9V022_READ_MODE, 0x300); in mt9v022_init()
226 ret = reg_write(client, MT9V022_ANALOG_GAIN, 16); in mt9v022_init()
228 ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, 480); in mt9v022_init()
230 ret = reg_write(client, mt9v022->reg->max_total_shutter_width, 480); in mt9v022_init()
235 ret = reg_write(client, MT9V022_DIGITAL_TEST_PATTERN, 0); in mt9v022_init()
274 if (reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control) < 0) in mt9v022_s_stream()
[all …]
Dmt9m001.c115 static int reg_write(struct i2c_client *client, const u8 reg, in reg_write() function
129 return reg_write(client, reg, ret | data); in reg_set()
140 return reg_write(client, reg, ret & ~data); in reg_clear()
153 ret = reg_write(client, MT9M001_RESET, 1); in mt9m001_init()
155 ret = reg_write(client, MT9M001_RESET, 0); in mt9m001_init()
159 ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 0); in mt9m001_init()
169 if (reg_write(client, MT9M001_OUTPUT_CONTROL, enable ? 2 : 0) < 0) in mt9m001_s_stream()
202 ret = reg_write(client, MT9M001_HORIZONTAL_BLANKING, hblank); in mt9m001_s_crop()
204 ret = reg_write(client, MT9M001_VERTICAL_BLANKING, vblank); in mt9m001_s_crop()
211 ret = reg_write(client, MT9M001_COLUMN_START, rect.left); in mt9m001_s_crop()
[all …]
Dmt9t031.c96 static int reg_write(struct i2c_client *client, const u8 reg, in reg_write() function
110 return reg_write(client, reg, ret | data); in reg_set()
121 return reg_write(client, reg, ret & ~data); in reg_clear()
128 ret = reg_write(client, MT9T031_SHUTTER_WIDTH_UPPER, data >> 16); in set_shutter()
131 ret = reg_write(client, MT9T031_SHUTTER_WIDTH, data & 0xffff); in set_shutter()
155 ret = reg_write(client, MT9T031_RESET, 1); in mt9t031_idle()
157 ret = reg_write(client, MT9T031_RESET, 0); in mt9t031_idle()
249 ret = reg_write(client, MT9T031_HORIZONTAL_BLANKING, hblank); in mt9t031_set_params()
251 ret = reg_write(client, MT9T031_VERTICAL_BLANKING, vblank); in mt9t031_set_params()
256 ret = reg_write(client, MT9T031_COLUMN_ADDRESS_MODE, in mt9t031_set_params()
[all …]
Dov5642.c664 static int reg_write(struct i2c_client *client, u16 reg, u8 val) in reg_write() function
687 ret = reg_write(client, reg, val16 >> 8); in reg_write16()
690 return reg_write(client, reg + 1, val16 & 0x00ff); in reg_write16()
719 return reg_write(client, reg->reg, reg->val); in ov5642_set_register()
727 int ret = reg_write(client, vals->reg_num, vals->value); in ov5642_write_array()
Dmt9m111.c132 #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) macro
315 return reg_write(CONTEXT_CONTROL, ctx->control); in mt9m111_set_context()
339 ret = reg_write(COLUMN_START, rect->left); in mt9m111_setup_geometry()
341 ret = reg_write(ROW_START, rect->top); in mt9m111_setup_geometry()
344 ret = reg_write(WINDOW_WIDTH, rect->width); in mt9m111_setup_geometry()
346 ret = reg_write(WINDOW_HEIGHT, rect->height); in mt9m111_setup_geometry()
368 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE); in mt9m111_enable()
678 return reg_write(GLOBAL_GAIN, val); in mt9m111_set_global_gain()
/drivers/firewire/
Dinit_ohci1394_dma.c53 static inline void reg_write(const struct ohci *ohci, int offset, u32 data) in reg_write() function
71 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); in get_phy_reg()
88 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); in set_phy_reg()
102 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); in init_ohci1394_soft_reset()
127 reg_write(ohci, OHCI1394_BusOptions, bus_options); in init_ohci1394_initialize()
130 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); in init_ohci1394_initialize()
133 reg_write(ohci, OHCI1394_HCControlSet, in init_ohci1394_initialize()
137 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); in init_ohci1394_initialize()
140 reg_write(ohci, OHCI1394_LinkControlSet, in init_ohci1394_initialize()
144 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400); in init_ohci1394_initialize()
[all …]
Dohci.c540 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) in reg_write() function
567 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); in read_phy_reg()
593 reg_write(ohci, OHCI1394_PhyControl, in write_phy_reg()
685 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); in ar_context_link_page()
708 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); in ar_context_abort()
1050 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); in ar_context_run()
1051 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); in ar_context_run()
1229 reg_write(ohci, COMMAND_PTR(ctx->regs), in context_run()
1231 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); in context_run()
1232 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); in context_run()
[all …]
Dnosy.c226 reg_write(struct pcilynx *lynx, int offset, u32 data) in reg_write() function
240 reg_write(lynx, offset, (reg_read(lynx, offset) | mask)); in reg_set_bits()
251 reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20, pcl_bus); in run_pcl()
252 reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20, in run_pcl()
269 reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | in set_phy_reg()
484 reg_write(lynx, LINK_INT_STATUS, link_int_status); in irq_handler()
494 reg_write(lynx, PCI_INT_STATUS, pci_int_status); in irq_handler()
515 reg_write(lynx, PCI_INT_ENABLE, 0); in remove_card()
603 reg_write(lynx, DMA0_CHAN_CTRL, 0); in add_card()
604 reg_write(lynx, DMA_GLOBAL_REGISTER, 0x00 << 24); in add_card()
[all …]
/drivers/media/tuners/
Dqm1d1c0042.c63 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) in reg_write() function
106 return reg_write(state, 0x03, state->regs[0x03]); in qm1d1c0042_set_srch_mode()
116 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_wakeup()
118 ret = reg_write(state, 0x05, state->regs[0x05]); in qm1d1c0042_wakeup()
204 ret = reg_write(state, 0x02, val); in qm1d1c0042_set_params()
212 ret = reg_write(state, 0x06, state->regs[0x06]); in qm1d1c0042_set_params()
218 ret = reg_write(state, 0x07, state->regs[0x07]); in qm1d1c0042_set_params()
229 ret = reg_write(state, 0x08, val); in qm1d1c0042_set_params()
250 ret = reg_write(state, 0x09, state->regs[0x09]); in qm1d1c0042_set_params()
252 ret = reg_write(state, 0x0a, state->regs[0x0a]); in qm1d1c0042_set_params()
[all …]
Dmxl301rf.c54 static int reg_write(struct mxl301rf_state *state, u8 reg, u8 val) in reg_write() function
92 ret = reg_write(state, 0x14, 0x01); in mxl301rf_get_rf_strength()
224 ret = reg_write(state, 0x1a, 0x0d); in mxl301rf_set_params()
268 ret = reg_write(state, 0x01, 0x01); in mxl301rf_init()
/drivers/gpu/drm/i2c/
Dtda998x_drv.c476 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) in reg_write() function
520 reg_write(priv, reg, old_val | val); in reg_set()
530 reg_write(priv, reg, old_val & ~val); in reg_clear()
537 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); in tda998x_reset()
539 reg_write(priv, REG_SOFTRESET, 0); in tda998x_reset()
547 reg_write(priv, REG_PLL_SERIAL_1, 0x00); in tda998x_reset()
548 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); in tda998x_reset()
549 reg_write(priv, REG_PLL_SERIAL_3, 0x00); in tda998x_reset()
550 reg_write(priv, REG_SERIALIZER, 0x00); in tda998x_reset()
551 reg_write(priv, REG_BUFFER_OUT, 0x00); in tda998x_reset()
[all …]
/drivers/media/usb/gspca/
Dspca505.c547 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function
591 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector()
633 reg_write(gspca_dev, 0x05, 0x00, (255 - brightness) >> 6); in setbrightness()
634 reg_write(gspca_dev, 0x05, 0x01, (255 - brightness) << 2); in setbrightness()
665 ret = reg_write(gspca_dev, 0x06, 0x16, 0x0a); in sd_start()
668 reg_write(gspca_dev, 0x05, 0xc2, 0x12); in sd_start()
673 reg_write(gspca_dev, 0x02, 0x00, 0x00); in sd_start()
676 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x00, mode_tb[mode][0]); in sd_start()
677 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x06, mode_tb[mode][1]); in sd_start()
678 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x07, mode_tb[mode][2]); in sd_start()
[all …]
Dspca508.c1244 static int reg_write(struct gspca_dev *gspca_dev, u16 index, u16 value) in reg_write() function
1291 ret = reg_write(gspca_dev, 0x8802, reg >> 8); in ssi_w()
1294 ret = reg_write(gspca_dev, 0x8801, reg & 0x00ff); in ssi_w()
1298 ret = reg_write(gspca_dev, 0x8805, val & 0x00ff); in ssi_w()
1303 ret = reg_write(gspca_dev, 0x8800, val); in ssi_w()
1337 ret = reg_write(gspca_dev, (*data)[1], in write_vector()
1402 reg_write(gspca_dev, 0x8500, mode); in sd_start()
1406 reg_write(gspca_dev, 0x8700, 0x28); /* clock */ in sd_start()
1411 reg_write(gspca_dev, 0x8700, 0x23); /* clock */ in sd_start()
1414 reg_write(gspca_dev, 0x8112, 0x10 | 0x20); in sd_start()
[all …]
Dspca501.c1759 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function
1783 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector()
1797 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x12, val); in setbrightness()
1802 reg_write(gspca_dev, 0x00, 0x00, (val >> 8) & 0xff); in setcontrast()
1803 reg_write(gspca_dev, 0x00, 0x01, val & 0xff); in setcontrast()
1808 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x0c, val); in setcolors()
1813 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x11, val); in setblue_balance()
1818 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x13, val); in setred_balance()
1894 reg_write(gspca_dev, SPCA50X_REG_USB, 0x6, 0x94); in sd_start()
1897 reg_write(gspca_dev, SPCA50X_REG_USB, 0x07, 0x004a); in sd_start()
[all …]
/drivers/media/pci/sta2x11/
Dsta2x11_vip.c219 static inline void reg_write(struct sta2x11_vip *vip, unsigned int reg, u32 val) in reg_write() function
238 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) | DVP_CTL_ENA); in start_dma()
240 reg_write(vip, DVP_VTP, (u32)vip_buf->dma); in start_dma()
241 reg_write(vip, DVP_VBP, (u32)vip_buf->dma + offset); in start_dma()
354 reg_write(vip, DVP_ITM, DVP_IT_VSB | DVP_IT_VST); in start_streaming()
370 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) & ~DVP_CTL_ENA); in stop_streaming()
372 reg_write(vip, DVP_ITM, 0); in stop_streaming()
703 reg_write(vip, DVP_TFO, 0); in vidioc_s_fmt_vid_cap()
705 reg_write(vip, DVP_BFO, 0); in vidioc_s_fmt_vid_cap()
707 reg_write(vip, DVP_TFS, t_stop); in vidioc_s_fmt_vid_cap()
[all …]
/drivers/media/i2c/
Dak881x.c43 static int reg_write(struct i2c_client *client, const u8 reg, in reg_write() function
55 return reg_write(client, reg, (ret & ~mask) | (data & mask)); in reg_set()
89 if (reg_write(client, reg->reg, reg->val) < 0) in ak881x_s_register()
189 reg_write(client, AK881X_DAC_MODE, dac); in ak881x_s_stream()
194 reg_write(client, AK881X_DAC_MODE, 0); in ak881x_s_stream()
286 reg_write(client, AK881X_INTERFACE_MODE, ifmode | (20 << 3)); in ak881x_probe()
/drivers/i2c/busses/
Di2c-pasemi.c60 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) in reg_write() function
76 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
84 reg_write(smbus, REG_SMSTA, status); in pasemi_smb_clear()
105 reg_write(smbus, REG_SMSTA, status); in pasemi_smb_waitready()
110 reg_write(smbus, REG_SMSTA, SMSTA_XEN); in pasemi_smb_waitready()
153 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | in pasemi_i2c_xfer_msg()
320 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | in pasemi_smb_xfer()
373 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | in pasemi_smb_probe()
/drivers/net/wireless/brcm80211/brcmfmac/
Dbtcoex.c118 } reg_write; in brcmf_btcoex_params_write() local
120 reg_write.addr = cpu_to_le32(addr); in brcmf_btcoex_params_write()
121 reg_write.data = cpu_to_le32(data); in brcmf_btcoex_params_write()
123 &reg_write, sizeof(reg_write)); in brcmf_btcoex_params_write()
/drivers/media/dvb-frontends/
Dtc90522.c55 reg_write(struct tc90522_state *state, const struct reg_val *regs, int num) in reg_write() function
116 return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid)); in tc90522s_set_tsid()
128 return reg_write(fe->demodulator_priv, &rv, 1); in tc90522t_set_layers()
506 ret = reg_write(state, &reset_sat, 1); in tc90522_set_frontend()
511 ret = reg_write(state, &reset_ter, 1); in tc90522_set_frontend()
570 return reg_write(state, rv, num); in tc90522_set_if_agc()
583 ret = reg_write(state, &sleep_sat, 1); in tc90522_sleep()
585 ret = reg_write(state, &sleep_ter, 1); in tc90522_sleep()
616 ret = reg_write(state, &wakeup_sat, 1); in tc90522_init()
618 ret = reg_write(state, &wakeup_ter, 1); in tc90522_init()
/drivers/net/dsa/
Dmv88e6060.c41 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) in reg_write() function
55 __ret = reg_write(ds, addr, reg, val); \
232 return reg_write(ds, addr, regnum, val); in mv88e6060_phy_write()
/drivers/base/regmap/
Dregmap-i2c.c51 .reg_write = regmap_smbus_byte_reg_write,
87 .reg_write = regmap_smbus_word_reg_write,
123 .reg_write = regmap_smbus_word_write_swapped,
Dregmap-ac97.c77 .reg_write = regmap_ac97_reg_write,
/drivers/atm/
Dlanai.c488 static inline void reg_write(const struct lanai_dev *lanai, u32 val, in reg_write() function
498 reg_write(lanai, lanai->conf1, Config1_Reg); in conf1_write()
503 reg_write(lanai, lanai->conf2, Config2_Reg); in conf2_write()
519 reg_write(lanai, 0, Reset_Reg); in reset_board()
1063 reg_write(lanai, i, IntControlEna_Reg); in intr_enable()
1068 reg_write(lanai, i, IntControlDis_Reg); in intr_disable()
1274 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg); in lanai_endtx()
1574 reg_write(lanai, INT_ALL, IntAck_Reg); in lanai_reset()
1594 reg_write(lanai, 0, ServWrite_Reg); in service_buffer_allocate()
1596 reg_write(lanai, in service_buffer_allocate()
[all …]

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