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Searched refs:rf3wireOffset (Results 1 – 9 of 9) sorted by relevance

/drivers/staging/rtl8192u/
Dr819xU_phy.c163 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialRead()
172 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialRead()
204 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, in rtl8192_phy_RFSerialRead()
244 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialWrite()
251 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialWrite()
268 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); in rtl8192_phy_RFSerialWrite()
278 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, in rtl8192_phy_RFSerialWrite()
612 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; in rtl8192_InitBBRFRegDef()
613 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in rtl8192_InitBBRFRegDef()
614 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; in rtl8192_InitBBRFRegDef()
[all …]
Dr8192U.h669 u32 rf3wireOffset; member
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c116 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_read()
123 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_read()
148 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, in _rtl92e_phy_rf_read()
173 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_write()
180 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_write()
194 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); in _rtl92e_phy_rf_write()
202 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, in _rtl92e_phy_rf_write()
415 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; in _rtl92e_init_bb_rf_reg_def()
416 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in _rtl92e_init_bb_rf_reg_def()
417 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; in _rtl92e_init_bb_rf_reg_def()
[all …]
Dr8190P_def.h119 u32 rf3wireOffset; member
/drivers/staging/rtl8188eu/hal/
Dbb_cfg.c620 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter; in rtl88e_phy_init_bb_rf_register_definition()
621 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter; in rtl88e_phy_init_bb_rf_register_definition()
Dphy.c123 phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr); in rf_serial_write()
/drivers/staging/rtl8723au/hal/
Drtl8723a_phycfg.c318 rtl8723au_write32(Adapter, pPhyReg->rf3wireOffset, DataAndAddr); in phy_RFSerialWrite()
474 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; in phy_InitBBRFRegisterDefinition()
475 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in phy_InitBBRFRegisterDefinition()
/drivers/staging/rtl8188eu/include/
DHal8188EPhyCfg.h129 u32 rf3wireOffset; /* LSSI data: */ member
/drivers/staging/rtl8723au/include/
DHal8723APhyCfg.h48 u32 rf3wireOffset; /* LSSI data: */ member