1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20
21 #include "odm_precomp.h"
22
23 #include <phy.h>
24
25 /* AGC_TAB_1T.TXT */
26
27 static u32 array_agc_tab_1t_8188e[] = {
28 0xC78, 0xFB000001,
29 0xC78, 0xFB010001,
30 0xC78, 0xFB020001,
31 0xC78, 0xFB030001,
32 0xC78, 0xFB040001,
33 0xC78, 0xFB050001,
34 0xC78, 0xFA060001,
35 0xC78, 0xF9070001,
36 0xC78, 0xF8080001,
37 0xC78, 0xF7090001,
38 0xC78, 0xF60A0001,
39 0xC78, 0xF50B0001,
40 0xC78, 0xF40C0001,
41 0xC78, 0xF30D0001,
42 0xC78, 0xF20E0001,
43 0xC78, 0xF10F0001,
44 0xC78, 0xF0100001,
45 0xC78, 0xEF110001,
46 0xC78, 0xEE120001,
47 0xC78, 0xED130001,
48 0xC78, 0xEC140001,
49 0xC78, 0xEB150001,
50 0xC78, 0xEA160001,
51 0xC78, 0xE9170001,
52 0xC78, 0xE8180001,
53 0xC78, 0xE7190001,
54 0xC78, 0xE61A0001,
55 0xC78, 0xE51B0001,
56 0xC78, 0xE41C0001,
57 0xC78, 0xE31D0001,
58 0xC78, 0xE21E0001,
59 0xC78, 0xE11F0001,
60 0xC78, 0x8A200001,
61 0xC78, 0x89210001,
62 0xC78, 0x88220001,
63 0xC78, 0x87230001,
64 0xC78, 0x86240001,
65 0xC78, 0x85250001,
66 0xC78, 0x84260001,
67 0xC78, 0x83270001,
68 0xC78, 0x82280001,
69 0xC78, 0x6B290001,
70 0xC78, 0x6A2A0001,
71 0xC78, 0x692B0001,
72 0xC78, 0x682C0001,
73 0xC78, 0x672D0001,
74 0xC78, 0x662E0001,
75 0xC78, 0x652F0001,
76 0xC78, 0x64300001,
77 0xC78, 0x63310001,
78 0xC78, 0x62320001,
79 0xC78, 0x61330001,
80 0xC78, 0x46340001,
81 0xC78, 0x45350001,
82 0xC78, 0x44360001,
83 0xC78, 0x43370001,
84 0xC78, 0x42380001,
85 0xC78, 0x41390001,
86 0xC78, 0x403A0001,
87 0xC78, 0x403B0001,
88 0xC78, 0x403C0001,
89 0xC78, 0x403D0001,
90 0xC78, 0x403E0001,
91 0xC78, 0x403F0001,
92 0xC78, 0xFB400001,
93 0xC78, 0xFB410001,
94 0xC78, 0xFB420001,
95 0xC78, 0xFB430001,
96 0xC78, 0xFB440001,
97 0xC78, 0xFB450001,
98 0xC78, 0xFB460001,
99 0xC78, 0xFB470001,
100 0xC78, 0xFB480001,
101 0xC78, 0xFA490001,
102 0xC78, 0xF94A0001,
103 0xC78, 0xF84B0001,
104 0xC78, 0xF74C0001,
105 0xC78, 0xF64D0001,
106 0xC78, 0xF54E0001,
107 0xC78, 0xF44F0001,
108 0xC78, 0xF3500001,
109 0xC78, 0xF2510001,
110 0xC78, 0xF1520001,
111 0xC78, 0xF0530001,
112 0xC78, 0xEF540001,
113 0xC78, 0xEE550001,
114 0xC78, 0xED560001,
115 0xC78, 0xEC570001,
116 0xC78, 0xEB580001,
117 0xC78, 0xEA590001,
118 0xC78, 0xE95A0001,
119 0xC78, 0xE85B0001,
120 0xC78, 0xE75C0001,
121 0xC78, 0xE65D0001,
122 0xC78, 0xE55E0001,
123 0xC78, 0xE45F0001,
124 0xC78, 0xE3600001,
125 0xC78, 0xE2610001,
126 0xC78, 0xC3620001,
127 0xC78, 0xC2630001,
128 0xC78, 0xC1640001,
129 0xC78, 0x8B650001,
130 0xC78, 0x8A660001,
131 0xC78, 0x89670001,
132 0xC78, 0x88680001,
133 0xC78, 0x87690001,
134 0xC78, 0x866A0001,
135 0xC78, 0x856B0001,
136 0xC78, 0x846C0001,
137 0xC78, 0x676D0001,
138 0xC78, 0x666E0001,
139 0xC78, 0x656F0001,
140 0xC78, 0x64700001,
141 0xC78, 0x63710001,
142 0xC78, 0x62720001,
143 0xC78, 0x61730001,
144 0xC78, 0x60740001,
145 0xC78, 0x46750001,
146 0xC78, 0x45760001,
147 0xC78, 0x44770001,
148 0xC78, 0x43780001,
149 0xC78, 0x42790001,
150 0xC78, 0x417A0001,
151 0xC78, 0x407B0001,
152 0xC78, 0x407C0001,
153 0xC78, 0x407D0001,
154 0xC78, 0x407E0001,
155 0xC78, 0x407F0001,
156 };
157
set_baseband_agc_config(struct adapter * adapt)158 static bool set_baseband_agc_config(struct adapter *adapt)
159 {
160 u32 i;
161 const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
162 u32 *array = array_agc_tab_1t_8188e;
163
164 for (i = 0; i < arraylen; i += 2) {
165 u32 v1 = array[i];
166 u32 v2 = array[i + 1];
167
168 if (v1 < 0xCDCDCDCD) {
169 phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
170 udelay(1);
171 }
172 }
173 return true;
174 }
175
176 /* PHY_REG_1T.TXT */
177
178 static u32 array_phy_reg_1t_8188e[] = {
179 0x800, 0x80040000,
180 0x804, 0x00000003,
181 0x808, 0x0000FC00,
182 0x80C, 0x0000000A,
183 0x810, 0x10001331,
184 0x814, 0x020C3D10,
185 0x818, 0x02200385,
186 0x81C, 0x00000000,
187 0x820, 0x01000100,
188 0x824, 0x00390204,
189 0x828, 0x00000000,
190 0x82C, 0x00000000,
191 0x830, 0x00000000,
192 0x834, 0x00000000,
193 0x838, 0x00000000,
194 0x83C, 0x00000000,
195 0x840, 0x00010000,
196 0x844, 0x00000000,
197 0x848, 0x00000000,
198 0x84C, 0x00000000,
199 0x850, 0x00000000,
200 0x854, 0x00000000,
201 0x858, 0x569A11A9,
202 0x85C, 0x01000014,
203 0x860, 0x66F60110,
204 0x864, 0x061F0649,
205 0x868, 0x00000000,
206 0x86C, 0x27272700,
207 0x870, 0x07000760,
208 0x874, 0x25004000,
209 0x878, 0x00000808,
210 0x87C, 0x00000000,
211 0x880, 0xB0000C1C,
212 0x884, 0x00000001,
213 0x888, 0x00000000,
214 0x88C, 0xCCC000C0,
215 0x890, 0x00000800,
216 0x894, 0xFFFFFFFE,
217 0x898, 0x40302010,
218 0x89C, 0x00706050,
219 0x900, 0x00000000,
220 0x904, 0x00000023,
221 0x908, 0x00000000,
222 0x90C, 0x81121111,
223 0x910, 0x00000002,
224 0x914, 0x00000201,
225 0xA00, 0x00D047C8,
226 0xA04, 0x80FF000C,
227 0xA08, 0x8C838300,
228 0xA0C, 0x2E7F120F,
229 0xA10, 0x9500BB78,
230 0xA14, 0x1114D028,
231 0xA18, 0x00881117,
232 0xA1C, 0x89140F00,
233 0xA20, 0x1A1B0000,
234 0xA24, 0x090E1317,
235 0xA28, 0x00000204,
236 0xA2C, 0x00D30000,
237 0xA70, 0x101FBF00,
238 0xA74, 0x00000007,
239 0xA78, 0x00000900,
240 0xA7C, 0x225B0606,
241 0xA80, 0x218075B1,
242 0xB2C, 0x80000000,
243 0xC00, 0x48071D40,
244 0xC04, 0x03A05611,
245 0xC08, 0x000000E4,
246 0xC0C, 0x6C6C6C6C,
247 0xC10, 0x08800000,
248 0xC14, 0x40000100,
249 0xC18, 0x08800000,
250 0xC1C, 0x40000100,
251 0xC20, 0x00000000,
252 0xC24, 0x00000000,
253 0xC28, 0x00000000,
254 0xC2C, 0x00000000,
255 0xC30, 0x69E9AC47,
256 0xC34, 0x469652AF,
257 0xC38, 0x49795994,
258 0xC3C, 0x0A97971C,
259 0xC40, 0x1F7C403F,
260 0xC44, 0x000100B7,
261 0xC48, 0xEC020107,
262 0xC4C, 0x007F037F,
263 0xC50, 0x69553420,
264 0xC54, 0x43BC0094,
265 0xC58, 0x00013169,
266 0xC5C, 0x00250492,
267 0xC60, 0x00000000,
268 0xC64, 0x7112848B,
269 0xC68, 0x47C00BFF,
270 0xC6C, 0x00000036,
271 0xC70, 0x2C7F000D,
272 0xC74, 0x020610DB,
273 0xC78, 0x0000001F,
274 0xC7C, 0x00B91612,
275 0xC80, 0x390000E4,
276 0xC84, 0x20F60000,
277 0xC88, 0x40000100,
278 0xC8C, 0x20200000,
279 0xC90, 0x00091521,
280 0xC94, 0x00000000,
281 0xC98, 0x00121820,
282 0xC9C, 0x00007F7F,
283 0xCA0, 0x00000000,
284 0xCA4, 0x000300A0,
285 0xCA8, 0x00000000,
286 0xCAC, 0x00000000,
287 0xCB0, 0x00000000,
288 0xCB4, 0x00000000,
289 0xCB8, 0x00000000,
290 0xCBC, 0x28000000,
291 0xCC0, 0x00000000,
292 0xCC4, 0x00000000,
293 0xCC8, 0x00000000,
294 0xCCC, 0x00000000,
295 0xCD0, 0x00000000,
296 0xCD4, 0x00000000,
297 0xCD8, 0x64B22427,
298 0xCDC, 0x00766932,
299 0xCE0, 0x00222222,
300 0xCE4, 0x00000000,
301 0xCE8, 0x37644302,
302 0xCEC, 0x2F97D40C,
303 0xD00, 0x00000740,
304 0xD04, 0x00020401,
305 0xD08, 0x0000907F,
306 0xD0C, 0x20010201,
307 0xD10, 0xA0633333,
308 0xD14, 0x3333BC43,
309 0xD18, 0x7A8F5B6F,
310 0xD2C, 0xCC979975,
311 0xD30, 0x00000000,
312 0xD34, 0x80608000,
313 0xD38, 0x00000000,
314 0xD3C, 0x00127353,
315 0xD40, 0x00000000,
316 0xD44, 0x00000000,
317 0xD48, 0x00000000,
318 0xD4C, 0x00000000,
319 0xD50, 0x6437140A,
320 0xD54, 0x00000000,
321 0xD58, 0x00000282,
322 0xD5C, 0x30032064,
323 0xD60, 0x4653DE68,
324 0xD64, 0x04518A3C,
325 0xD68, 0x00002101,
326 0xD6C, 0x2A201C16,
327 0xD70, 0x1812362E,
328 0xD74, 0x322C2220,
329 0xD78, 0x000E3C24,
330 0xE00, 0x2D2D2D2D,
331 0xE04, 0x2D2D2D2D,
332 0xE08, 0x0390272D,
333 0xE10, 0x2D2D2D2D,
334 0xE14, 0x2D2D2D2D,
335 0xE18, 0x2D2D2D2D,
336 0xE1C, 0x2D2D2D2D,
337 0xE28, 0x00000000,
338 0xE30, 0x1000DC1F,
339 0xE34, 0x10008C1F,
340 0xE38, 0x02140102,
341 0xE3C, 0x681604C2,
342 0xE40, 0x01007C00,
343 0xE44, 0x01004800,
344 0xE48, 0xFB000000,
345 0xE4C, 0x000028D1,
346 0xE50, 0x1000DC1F,
347 0xE54, 0x10008C1F,
348 0xE58, 0x02140102,
349 0xE5C, 0x28160D05,
350 0xE60, 0x00000008,
351 0xE68, 0x001B25A4,
352 0xE6C, 0x00C00014,
353 0xE70, 0x00C00014,
354 0xE74, 0x01000014,
355 0xE78, 0x01000014,
356 0xE7C, 0x01000014,
357 0xE80, 0x01000014,
358 0xE84, 0x00C00014,
359 0xE88, 0x01000014,
360 0xE8C, 0x00C00014,
361 0xED0, 0x00C00014,
362 0xED4, 0x00C00014,
363 0xED8, 0x00C00014,
364 0xEDC, 0x00000014,
365 0xEE0, 0x00000014,
366 0xEEC, 0x01C00014,
367 0xF14, 0x00000003,
368 0xF4C, 0x00000000,
369 0xF00, 0x00000300,
370 };
371
rtl_bb_delay(struct adapter * adapt,u32 addr,u32 data)372 static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
373 {
374 if (addr == 0xfe) {
375 msleep(50);
376 } else if (addr == 0xfd) {
377 mdelay(5);
378 } else if (addr == 0xfc) {
379 mdelay(1);
380 } else if (addr == 0xfb) {
381 udelay(50);
382 } else if (addr == 0xfa) {
383 udelay(5);
384 } else if (addr == 0xf9) {
385 udelay(1);
386 } else {
387 phy_set_bb_reg(adapt, addr, bMaskDWord, data);
388 /* Add 1us delay between BB/RF register setting. */
389 udelay(1);
390 }
391 }
392
set_baseband_phy_config(struct adapter * adapt)393 static bool set_baseband_phy_config(struct adapter *adapt)
394 {
395 u32 i;
396 const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
397 u32 *array = array_phy_reg_1t_8188e;
398
399 for (i = 0; i < arraylen; i += 2) {
400 u32 v1 = array[i];
401 u32 v2 = array[i + 1];
402
403 if (v1 < 0xCDCDCDCD)
404 rtl_bb_delay(adapt, v1, v2);
405 }
406 return true;
407 }
408
409 /* PHY_REG_PG.TXT */
410
411 static u32 array_phy_reg_pg_8188e[] = {
412 0xE00, 0xFFFFFFFF, 0x06070809,
413 0xE04, 0xFFFFFFFF, 0x02020405,
414 0xE08, 0x0000FF00, 0x00000006,
415 0x86C, 0xFFFFFF00, 0x00020400,
416 0xE10, 0xFFFFFFFF, 0x08090A0B,
417 0xE14, 0xFFFFFFFF, 0x01030607,
418 0xE18, 0xFFFFFFFF, 0x08090A0B,
419 0xE1C, 0xFFFFFFFF, 0x01030607,
420 0xE00, 0xFFFFFFFF, 0x00000000,
421 0xE04, 0xFFFFFFFF, 0x00000000,
422 0xE08, 0x0000FF00, 0x00000000,
423 0x86C, 0xFFFFFF00, 0x00000000,
424 0xE10, 0xFFFFFFFF, 0x00000000,
425 0xE14, 0xFFFFFFFF, 0x00000000,
426 0xE18, 0xFFFFFFFF, 0x00000000,
427 0xE1C, 0xFFFFFFFF, 0x00000000,
428 0xE00, 0xFFFFFFFF, 0x02020202,
429 0xE04, 0xFFFFFFFF, 0x00020202,
430 0xE08, 0x0000FF00, 0x00000000,
431 0x86C, 0xFFFFFF00, 0x00000000,
432 0xE10, 0xFFFFFFFF, 0x04040404,
433 0xE14, 0xFFFFFFFF, 0x00020404,
434 0xE18, 0xFFFFFFFF, 0x00000000,
435 0xE1C, 0xFFFFFFFF, 0x00000000,
436 0xE00, 0xFFFFFFFF, 0x02020202,
437 0xE04, 0xFFFFFFFF, 0x00020202,
438 0xE08, 0x0000FF00, 0x00000000,
439 0x86C, 0xFFFFFF00, 0x00000000,
440 0xE10, 0xFFFFFFFF, 0x04040404,
441 0xE14, 0xFFFFFFFF, 0x00020404,
442 0xE18, 0xFFFFFFFF, 0x00000000,
443 0xE1C, 0xFFFFFFFF, 0x00000000,
444 0xE00, 0xFFFFFFFF, 0x00000000,
445 0xE04, 0xFFFFFFFF, 0x00000000,
446 0xE08, 0x0000FF00, 0x00000000,
447 0x86C, 0xFFFFFF00, 0x00000000,
448 0xE10, 0xFFFFFFFF, 0x00000000,
449 0xE14, 0xFFFFFFFF, 0x00000000,
450 0xE18, 0xFFFFFFFF, 0x00000000,
451 0xE1C, 0xFFFFFFFF, 0x00000000,
452 0xE00, 0xFFFFFFFF, 0x02020202,
453 0xE04, 0xFFFFFFFF, 0x00020202,
454 0xE08, 0x0000FF00, 0x00000000,
455 0x86C, 0xFFFFFF00, 0x00000000,
456 0xE10, 0xFFFFFFFF, 0x04040404,
457 0xE14, 0xFFFFFFFF, 0x00020404,
458 0xE18, 0xFFFFFFFF, 0x00000000,
459 0xE1C, 0xFFFFFFFF, 0x00000000,
460 0xE00, 0xFFFFFFFF, 0x00000000,
461 0xE04, 0xFFFFFFFF, 0x00000000,
462 0xE08, 0x0000FF00, 0x00000000,
463 0x86C, 0xFFFFFF00, 0x00000000,
464 0xE10, 0xFFFFFFFF, 0x00000000,
465 0xE14, 0xFFFFFFFF, 0x00000000,
466 0xE18, 0xFFFFFFFF, 0x00000000,
467 0xE1C, 0xFFFFFFFF, 0x00000000,
468 0xE00, 0xFFFFFFFF, 0x00000000,
469 0xE04, 0xFFFFFFFF, 0x00000000,
470 0xE08, 0x0000FF00, 0x00000000,
471 0x86C, 0xFFFFFF00, 0x00000000,
472 0xE10, 0xFFFFFFFF, 0x00000000,
473 0xE14, 0xFFFFFFFF, 0x00000000,
474 0xE18, 0xFFFFFFFF, 0x00000000,
475 0xE1C, 0xFFFFFFFF, 0x00000000,
476 0xE00, 0xFFFFFFFF, 0x00000000,
477 0xE04, 0xFFFFFFFF, 0x00000000,
478 0xE08, 0x0000FF00, 0x00000000,
479 0x86C, 0xFFFFFF00, 0x00000000,
480 0xE10, 0xFFFFFFFF, 0x00000000,
481 0xE14, 0xFFFFFFFF, 0x00000000,
482 0xE18, 0xFFFFFFFF, 0x00000000,
483 0xE1C, 0xFFFFFFFF, 0x00000000,
484 0xE00, 0xFFFFFFFF, 0x00000000,
485 0xE04, 0xFFFFFFFF, 0x00000000,
486 0xE08, 0x0000FF00, 0x00000000,
487 0x86C, 0xFFFFFF00, 0x00000000,
488 0xE10, 0xFFFFFFFF, 0x00000000,
489 0xE14, 0xFFFFFFFF, 0x00000000,
490 0xE18, 0xFFFFFFFF, 0x00000000,
491 0xE1C, 0xFFFFFFFF, 0x00000000,
492 0xE00, 0xFFFFFFFF, 0x00000000,
493 0xE04, 0xFFFFFFFF, 0x00000000,
494 0xE08, 0x0000FF00, 0x00000000,
495 0x86C, 0xFFFFFF00, 0x00000000,
496 0xE10, 0xFFFFFFFF, 0x00000000,
497 0xE14, 0xFFFFFFFF, 0x00000000,
498 0xE18, 0xFFFFFFFF, 0x00000000,
499 0xE1C, 0xFFFFFFFF, 0x00000000,
500
501 };
502
store_pwrindex_offset(struct adapter * adapter,u32 regaddr,u32 bitmask,u32 data)503 static void store_pwrindex_offset(struct adapter *adapter,
504 u32 regaddr, u32 bitmask, u32 data)
505 {
506 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapter);
507 u32 * const power_level_offset =
508 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt];
509
510 if (regaddr == rTxAGC_A_Rate18_06)
511 power_level_offset[0] = data;
512 if (regaddr == rTxAGC_A_Rate54_24)
513 power_level_offset[1] = data;
514 if (regaddr == rTxAGC_A_CCK1_Mcs32)
515 power_level_offset[6] = data;
516 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
517 power_level_offset[7] = data;
518 if (regaddr == rTxAGC_A_Mcs03_Mcs00)
519 power_level_offset[2] = data;
520 if (regaddr == rTxAGC_A_Mcs07_Mcs04)
521 power_level_offset[3] = data;
522 if (regaddr == rTxAGC_A_Mcs11_Mcs08)
523 power_level_offset[4] = data;
524 if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
525 power_level_offset[5] = data;
526 if (hal_data->rf_type == RF_1T1R)
527 hal_data->pwrGroupCnt++;
528 }
529 if (regaddr == rTxAGC_B_Rate18_06)
530 power_level_offset[8] = data;
531 if (regaddr == rTxAGC_B_Rate54_24)
532 power_level_offset[9] = data;
533 if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
534 power_level_offset[14] = data;
535 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
536 power_level_offset[15] = data;
537 if (regaddr == rTxAGC_B_Mcs03_Mcs00)
538 power_level_offset[10] = data;
539 if (regaddr == rTxAGC_B_Mcs07_Mcs04)
540 power_level_offset[11] = data;
541 if (regaddr == rTxAGC_B_Mcs11_Mcs08)
542 power_level_offset[12] = data;
543 if (regaddr == rTxAGC_B_Mcs15_Mcs12) {
544 power_level_offset[13] = data;
545 if (hal_data->rf_type != RF_1T1R)
546 hal_data->pwrGroupCnt++;
547 }
548 }
549
rtl_addr_delay(struct adapter * adapt,u32 addr,u32 bit_mask,u32 data)550 static void rtl_addr_delay(struct adapter *adapt,
551 u32 addr, u32 bit_mask, u32 data)
552 {
553 switch (addr) {
554 case 0xfe:
555 msleep(50);
556 break;
557 case 0xfd:
558 mdelay(5);
559 break;
560 case 0xfc:
561 mdelay(1);
562 break;
563 case 0xfb:
564 udelay(50);
565 break;
566 case 0xfa:
567 udelay(5);
568 break;
569 case 0xf9:
570 udelay(1);
571 break;
572 default:
573 store_pwrindex_offset(adapt, addr, bit_mask, data);
574 }
575 }
576
config_bb_with_pgheader(struct adapter * adapt)577 static bool config_bb_with_pgheader(struct adapter *adapt)
578 {
579 u32 i;
580 const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
581 u32 *array = array_phy_reg_pg_8188e;
582
583 for (i = 0; i < arraylen; i += 3) {
584 u32 v1 = array[i];
585 u32 v2 = array[i + 1];
586 u32 v3 = array[i + 2];
587
588 if (v1 < 0xCDCDCDCD)
589 rtl_addr_delay(adapt, v1, v2, v3);
590 }
591 return true;
592 }
593
rtl88e_phy_init_bb_rf_register_definition(struct adapter * adapter)594 static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *adapter)
595 {
596 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapter);
597 struct bb_reg_def *reg[4];
598
599 reg[RF_PATH_A] = &hal_data->PHYRegDef[RF_PATH_A];
600 reg[RF_PATH_B] = &hal_data->PHYRegDef[RF_PATH_B];
601 reg[RF_PATH_C] = &hal_data->PHYRegDef[RF_PATH_C];
602 reg[RF_PATH_D] = &hal_data->PHYRegDef[RF_PATH_D];
603
604 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
605 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
606 reg[RF_PATH_C]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
607 reg[RF_PATH_D]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
608
609 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
610 reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
611 reg[RF_PATH_C]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
612 reg[RF_PATH_D]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
613
614 reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
615 reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
616
617 reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE;
618 reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE;
619
620 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
621 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
622
623 reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
624 reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
625 reg[RF_PATH_C]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
626 reg[RF_PATH_D]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
627
628 reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
629 reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
630 reg[RF_PATH_C]->rfTxGainStage = rFPGA0_TxGainStage;
631 reg[RF_PATH_D]->rfTxGainStage = rFPGA0_TxGainStage;
632
633 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
634 reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
635
636 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
637 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
638
639 reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
640 reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
641 reg[RF_PATH_C]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
642 reg[RF_PATH_D]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
643
644 reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
645 reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
646 reg[RF_PATH_C]->rfAGCControl1 = rOFDM0_XCAGCCore1;
647 reg[RF_PATH_D]->rfAGCControl1 = rOFDM0_XDAGCCore1;
648
649 reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
650 reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
651 reg[RF_PATH_C]->rfAGCControl2 = rOFDM0_XCAGCCore2;
652 reg[RF_PATH_D]->rfAGCControl2 = rOFDM0_XDAGCCore2;
653
654 reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
655 reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
656 reg[RF_PATH_C]->rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
657 reg[RF_PATH_D]->rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
658
659 reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
660 reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
661 reg[RF_PATH_C]->rfRxAFE = rOFDM0_XCRxAFE;
662 reg[RF_PATH_D]->rfRxAFE = rOFDM0_XDRxAFE;
663
664 reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
665 reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
666 reg[RF_PATH_C]->rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
667 reg[RF_PATH_D]->rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
668
669 reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
670 reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
671 reg[RF_PATH_C]->rfTxAFE = rOFDM0_XCTxAFE;
672 reg[RF_PATH_D]->rfTxAFE = rOFDM0_XDTxAFE;
673
674 reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
675 reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
676 reg[RF_PATH_C]->rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
677 reg[RF_PATH_D]->rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
678
679 reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
680 reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
681 }
682
config_parafile(struct adapter * adapt)683 static bool config_parafile(struct adapter *adapt)
684 {
685 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
686 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
687
688 set_baseband_phy_config(adapt);
689
690 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
691 if (!eeprom->bautoload_fail_flag) {
692 hal_data->pwrGroupCnt = 0;
693 config_bb_with_pgheader(adapt);
694 }
695 set_baseband_agc_config(adapt);
696 return true;
697 }
698
rtl88eu_phy_bb_config(struct adapter * adapt)699 bool rtl88eu_phy_bb_config(struct adapter *adapt)
700 {
701 int rtstatus = true;
702 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
703 u32 regval;
704 u8 crystal_cap;
705
706 rtl88e_phy_init_bb_rf_register_definition(adapt);
707
708 /* Enable BB and RF */
709 regval = usb_read16(adapt, REG_SYS_FUNC_EN);
710 usb_write16(adapt, REG_SYS_FUNC_EN,
711 (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
712
713 usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
714
715 usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA |
716 FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
717
718 /* Config BB and AGC */
719 rtstatus = config_parafile(adapt);
720
721 /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
722 crystal_cap = hal_data->CrystalCap & 0x3F;
723 phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800,
724 (crystal_cap | (crystal_cap << 6)));
725
726 return rtstatus;
727 }
728