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Searched refs:src_offset (Results 1 – 25 of 40) sorted by relevance

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/drivers/misc/mic/scif/
Dscif_dma.c65 s64 src_offset; member
921 offset = work->src_offset; in scif_rma_list_dma_copy_unaligned()
1134 s64 src_offset = work->src_offset, dst_offset = work->dst_offset; in _scif_rma_list_dma_copy_aligned() local
1149 if (src_offset == end_src_offset) { in _scif_rma_list_dma_copy_aligned()
1163 src_dma_addr = scif_off_to_dma_addr(src_window, src_offset, in _scif_rma_list_dma_copy_aligned()
1191 src_offset += (loop_len - 1); in _scif_rma_list_dma_copy_aligned()
1224 src_offset += loop_len; in _scif_rma_list_dma_copy_aligned()
1254 s64 src_offset = work->src_offset, dst_offset = work->dst_offset; in scif_rma_list_dma_copy_aligned() local
1264 src_cache_off = src_offset & (L1_CACHE_BYTES - 1); in scif_rma_list_dma_copy_aligned()
1269 src_dma_addr = __scif_off_to_dma_addr(src_window, src_offset); in scif_rma_list_dma_copy_aligned()
[all …]
Dscif_rma.h384 static inline bool scif_unaligned(off_t src_offset, off_t dst_offset) in scif_unaligned() argument
386 src_offset = src_offset & (L1_CACHE_BYTES - 1); in scif_unaligned()
388 return !(src_offset == dst_offset); in scif_unaligned()
/drivers/gpu/drm/radeon/
Drv770_dma.c43 uint64_t src_offset, uint64_t dst_offset, in rv770_copy_dma() argument
76 radeon_ring_write(ring, src_offset & 0xfffffffc); in rv770_copy_dma()
78 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in rv770_copy_dma()
79 src_offset += cur_size_in_dw * 4; in rv770_copy_dma()
Devergreen_dma.c108 uint64_t src_offset, in evergreen_copy_dma() argument
142 radeon_ring_write(ring, src_offset & 0xfffffffc); in evergreen_copy_dma()
144 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
145 src_offset += cur_size_in_dw * 4; in evergreen_copy_dma()
Devergreen_cs.c2753 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2818 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2819 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2822 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2824 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2843 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2844 src_offset <<= 8; in evergreen_dma_cs_parse()
2853 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2854 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2862 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
[all …]
Dsi_dma.c232 uint64_t src_offset, uint64_t dst_offset, in si_copy_dma() argument
265 radeon_ring_write(ring, lower_32_bits(src_offset)); in si_copy_dma()
267 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
268 src_offset += cur_size_in_bytes; in si_copy_dma()
Dr600_dma.c440 uint64_t src_offset, uint64_t dst_offset, in r600_copy_dma() argument
473 radeon_ring_write(ring, src_offset & 0xfffffffc); in r600_copy_dma()
475 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
476 src_offset += cur_size_in_dw * 4; in r600_copy_dma()
Dradeon_asic.h86 uint64_t src_offset,
157 uint64_t src_offset,
348 uint64_t src_offset, uint64_t dst_offset,
352 uint64_t src_offset, uint64_t dst_offset,
473 uint64_t src_offset, uint64_t dst_offset,
547 uint64_t src_offset, uint64_t dst_offset,
725 uint64_t src_offset, uint64_t dst_offset,
796 uint64_t src_offset, uint64_t dst_offset,
800 uint64_t src_offset, uint64_t dst_offset,
Dr200.c84 uint64_t src_offset, in r200_copy_dma() argument
114 radeon_ring_write(ring, src_offset); in r200_copy_dma()
117 src_offset += cur_size; in r200_copy_dma()
Dcik_sdma.c580 uint64_t src_offset, uint64_t dst_offset, in cik_copy_dma() argument
614 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_dma()
615 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
618 src_offset += cur_size_in_bytes; in cik_copy_dma()
Dr600_cs.c2480 u64 src_offset, dst_offset; in r600_dma_cs_parse() local
2538 src_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2539 src_offset <<= 8; in r600_dma_cs_parse()
2548 src_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2549 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2560 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2561 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_dma_cs_parse()
2571 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2572 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2583 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in r600_dma_cs_parse()
[all …]
/drivers/gpu/drm/nouveau/
Dnouveau_bo.c725 u64 src_offset = node->vma[0].offset; in nvc0_bo_move_copy() local
739 OUT_RING (chan, upper_32_bits(src_offset)); in nvc0_bo_move_copy()
740 OUT_RING (chan, lower_32_bits(src_offset)); in nvc0_bo_move_copy()
751 src_offset += (PAGE_SIZE * line_count); in nvc0_bo_move_copy()
763 u64 src_offset = node->vma[0].offset; in nvc0_bo_move_m2mf() local
780 OUT_RING (chan, upper_32_bits(src_offset)); in nvc0_bo_move_m2mf()
781 OUT_RING (chan, lower_32_bits(src_offset)); in nvc0_bo_move_m2mf()
790 src_offset += (PAGE_SIZE * line_count); in nvc0_bo_move_m2mf()
802 u64 src_offset = node->vma[0].offset; in nva3_bo_move_copy() local
816 OUT_RING (chan, upper_32_bits(src_offset)); in nva3_bo_move_copy()
[all …]
/drivers/gpu/drm/qxl/
Dqxl_ioctl.c76 int src_offset; member
91 info->src_offset); in apply_reloc()
241 reloc_info[i].src_offset = reloc.src_offset; in qxl_process_single_command()
244 reloc_info[i].src_offset = 0; in qxl_process_single_command()
/drivers/gpu/drm/mgag200/
Dmgag200_fb.c28 int src_offset, dst_offset; in mga_dirty_update() local
90 src_offset = dst_offset = i * mfbdev->mfb.base.pitches[0] + (x * bpp); in mga_dirty_update()
91 memcpy_toio(bo->kmap.virtual + src_offset, mfbdev->sysram + src_offset, (x2 - x + 1) * bpp); in mga_dirty_update()
/drivers/gpu/drm/cirrus/
Dcirrus_fbdev.c26 int src_offset, dst_offset; in cirrus_dirty_update() local
87 src_offset = dst_offset = i * afbdev->gfb.base.pitches[0] + (x * bpp); in cirrus_dirty_update()
88 memcpy_toio(bo->kmap.virtual + src_offset, afbdev->sysram + src_offset, width * bpp); in cirrus_dirty_update()
/drivers/clk/sirf/
Dclk-atlas7.c223 u16 src_offset; /* dto src offset */ member
492 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_is_enabled()
502 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_enable()
514 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_disable()
526 …u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC… in dto_clk_recalc_rate()
557 clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC); in dto_clk_set_rate()
567 return clkc_readl(clk->src_offset); in dto_clk_get_parent()
577 clkc_writel(index, clk->src_offset); in dto_clk_set_parent()
608 .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC,
629 .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC,
[all …]
/drivers/gpu/drm/ast/
Dast_fb.c52 int src_offset, dst_offset; in ast_dirty_update() local
114 src_offset = dst_offset = i * afbdev->afb.base.pitches[0] + (x * bpp); in ast_dirty_update()
115 memcpy_toio(bo->kmap.virtual + src_offset, afbdev->sysram + src_offset, (x2 - x + 1) * bpp); in ast_dirty_update()
/drivers/video/fbdev/
Dfb-puv3.c140 int src_offset = src_y0 * src_pitch + src_x0 * (m_iBpp / 8); in unifb_prim_fillrect() local
167 writel(src_offset, UGE_SRCSTART); in unifb_prim_fillrect()
230 int src_offset = src_y0 * src_pitch + src_x0 * (m_iBpp / 8); in unifb_prim_copyarea() local
250 src_offset = (src_y0 + aheight) * src_pitch + in unifb_prim_copyarea()
272 writel(src_offset, UGE_SRCSTART); in unifb_prim_copyarea()
Dps3fb.c441 u64 dst_offset, u64 src_offset, u32 width, in ps3fb_sync_image() argument
452 src_offset += GPU_FB_START; in ps3fb_sync_image()
456 GPU_IOIF + src_offset, in ps3fb_sync_image()
/drivers/gpu/drm/gma500/
Daccel_2d.c173 uint32_t src_offset, uint32_t src_stride, in psb_accel_2d_copy() argument
216 *buf++ = src_offset; in psb_accel_2d_copy()
/drivers/block/
Dps3vram.c251 unsigned int src_offset, unsigned int dst_offset, in ps3vram_upload() argument
258 ps3vram_out_ring(priv, XDR_IOIF + src_offset); in ps3vram_upload()
283 unsigned int src_offset, unsigned int dst_offset, in ps3vram_download() argument
290 ps3vram_out_ring(priv, src_offset); in ps3vram_download()
/drivers/usb/isp1760/
Disp1760-hcd.c185 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, in bank_reads8() argument
193 src = src_base + (bank_addr | src_offset); in bank_reads8()
195 if (src_offset < PAYLOAD_OFFSET) { in bank_reads8()
217 if (src_offset < PAYLOAD_OFFSET) in bank_reads8()
232 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, in mem_reads8() argument
235 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); in mem_reads8()
237 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); in mem_reads8()
/drivers/staging/lustre/include/linux/lnet/
Dtypes.h158 __u32 src_offset; member
/drivers/crypto/qce/
Dsha.c268 unsigned int src_offset = req->nbytes - hash_later; in qce_ahash_update() local
269 scatterwalk_map_and_copy(rctx->buf, req->src, src_offset, in qce_ahash_update()
/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c1345 uint64_t src_offset, in cik_sdma_emit_copy_buffer() argument
1352 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in cik_sdma_emit_copy_buffer()
1353 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); in cik_sdma_emit_copy_buffer()

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