| /drivers/gpu/drm/nouveau/nvkm/core/ |
| D | ioctl.c | 35 struct nvif_ioctl_nop_v0 v0; in nvkm_ioctl_nop() member
40 if (nvif_unpack(args->v0, 0, 0, false)) { in nvkm_ioctl_nop()
41 nvif_ioctl(object, "nop vers %lld\n", args->v0.version); in nvkm_ioctl_nop()
42 args->v0.version = NVIF_VERSION_LATEST; in nvkm_ioctl_nop()
52 struct nvif_ioctl_sclass_v0 v0; in nvkm_ioctl_sclass() member
58 if (nvif_unpack(args->v0, 0, 0, true)) { in nvkm_ioctl_sclass()
60 args->v0.version, args->v0.count); in nvkm_ioctl_sclass()
61 if (size != args->v0.count * sizeof(args->v0.oclass[0])) in nvkm_ioctl_sclass()
66 if (i < args->v0.count) { in nvkm_ioctl_sclass()
67 args->v0.oclass[i].oclass = oclass.base.oclass; in nvkm_ioctl_sclass()
[all …]
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| D | client.c | 39 struct nvif_notify_rep_v0 v0; member
96 struct nvif_notify_req_v0 v0; in nvkm_client_notify_new() member
114 if (nvif_unpack(req->v0, 0, 0, true)) { in nvkm_client_notify_new()
116 "token %llx\n", req->v0.version, in nvkm_client_notify_new()
117 req->v0.reply, req->v0.route, req->v0.token); in nvkm_client_notify_new()
118 notify->version = req->v0.version; in nvkm_client_notify_new()
119 notify->size = sizeof(notify->rep.v0); in nvkm_client_notify_new()
120 notify->rep.v0.version = req->v0.version; in nvkm_client_notify_new()
121 notify->rep.v0.route = req->v0.route; in nvkm_client_notify_new()
122 notify->rep.v0.token = req->v0.token; in nvkm_client_notify_new()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/device/ |
| D | ctrl.c | 37 struct nvif_control_pstate_info_v0 v0; in nvkm_control_mthd_pstate_info() member
43 if (nvif_unpack(args->v0, 0, 0, false)) { in nvkm_control_mthd_pstate_info()
45 args->v0.version); in nvkm_control_mthd_pstate_info()
50 args->v0.count = clk->state_nr; in nvkm_control_mthd_pstate_info()
51 args->v0.ustate_ac = clk->ustate_ac; in nvkm_control_mthd_pstate_info()
52 args->v0.ustate_dc = clk->ustate_dc; in nvkm_control_mthd_pstate_info()
53 args->v0.pwrsrc = clk->pwrsrc; in nvkm_control_mthd_pstate_info()
54 args->v0.pstate = clk->pstate; in nvkm_control_mthd_pstate_info()
56 args->v0.count = 0; in nvkm_control_mthd_pstate_info()
57 args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE; in nvkm_control_mthd_pstate_info()
[all …]
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| D | user.c | 49 struct nv_device_info_v0 v0; in nvkm_udevice_info() member
54 if (nvif_unpack(args->v0, 0, 0, false)) { in nvkm_udevice_info()
55 nvif_ioctl(object, "device info vers %d\n", args->v0.version); in nvkm_udevice_info()
70 args->v0.platform = NV_DEVICE_INFO_V0_IGP; in nvkm_udevice_info()
75 args->v0.platform = NV_DEVICE_INFO_V0_PCI; in nvkm_udevice_info()
78 args->v0.platform = NV_DEVICE_INFO_V0_AGP; in nvkm_udevice_info()
81 args->v0.platform = NV_DEVICE_INFO_V0_PCIE; in nvkm_udevice_info()
84 args->v0.platform = NV_DEVICE_INFO_V0_SOC; in nvkm_udevice_info()
94 case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break; in nvkm_udevice_info()
96 case NV_11: args->v0.family = NV_DEVICE_INFO_V0_CELSIUS; break; in nvkm_udevice_info()
[all …]
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_usif.c | 77 struct nvif_notify_rep_v0 v0; in usif_notify() member
83 if (length == sizeof(rep->v0) && rep->v0.version == 0) { in usif_notify()
84 if (WARN_ON(!(ntfy = (void *)(unsigned long)rep->v0.token))) in usif_notify()
86 BUG_ON(rep->v0.route != NVDRM_NOTIFY_USIF); in usif_notify()
98 switch (rep->v0.version) { in usif_notify()
127 struct nvif_ioctl_ntfy_new_v0 v0; in usif_notify_new() member
130 struct nvif_notify_req_v0 v0; in usif_notify_new() member
135 if (nvif_unpack(args->v0, 0, 0, true)) { in usif_notify_new()
136 if (usif_notify_find(f, args->v0.index)) in usif_notify_new()
146 if (nvif_unpack(req->v0, 0, 0, true)) { in usif_notify_new()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | rootnv04.c | 45 struct nv04_disp_scanoutpos_v0 v0; in nv04_disp_scanoutpos() member
51 if (nvif_unpack(args->v0, 0, 0, false)) { in nv04_disp_scanoutpos()
53 args->v0.version); in nv04_disp_scanoutpos()
54 args->v0.vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0xffff; in nv04_disp_scanoutpos()
55 args->v0.vtotal = nvkm_rd32(device, 0x680804 + hoff) & 0xffff; in nv04_disp_scanoutpos()
56 args->v0.vblanke = args->v0.vtotal - 1; in nv04_disp_scanoutpos()
58 args->v0.hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0xffff; in nv04_disp_scanoutpos()
59 args->v0.htotal = nvkm_rd32(device, 0x680824 + hoff) & 0xffff; in nv04_disp_scanoutpos()
60 args->v0.hblanke = args->v0.htotal - 1; in nv04_disp_scanoutpos()
67 if (!args->v0.vtotal || !args->v0.htotal) in nv04_disp_scanoutpos()
[all …]
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| D | dacnv50.c | 39 struct nv50_disp_dac_pwr_v0 v0; in nv50_dac_power() member
45 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_dac_power()
48 args->v0.version, args->v0.state, args->v0.data, in nv50_dac_power()
49 args->v0.vsync, args->v0.hsync); in nv50_dac_power()
50 stat = 0x00000040 * !args->v0.state; in nv50_dac_power()
51 stat |= 0x00000010 * !args->v0.data; in nv50_dac_power()
52 stat |= 0x00000004 * !args->v0.vsync; in nv50_dac_power()
53 stat |= 0x00000001 * !args->v0.hsync; in nv50_dac_power()
75 struct nv50_disp_dac_load_v0 v0; in nv50_dac_sense() member
82 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_dac_sense()
[all …]
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| D | rootnv50.c | 42 struct nv04_disp_scanoutpos_v0 v0; in nv50_disp_root_scanoutpos() member
47 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_disp_root_scanoutpos()
49 args->v0.version); in nv50_disp_root_scanoutpos()
50 args->v0.vblanke = (blanke & 0xffff0000) >> 16; in nv50_disp_root_scanoutpos()
51 args->v0.hblanke = (blanke & 0x0000ffff); in nv50_disp_root_scanoutpos()
52 args->v0.vblanks = (blanks & 0xffff0000) >> 16; in nv50_disp_root_scanoutpos()
53 args->v0.hblanks = (blanks & 0x0000ffff); in nv50_disp_root_scanoutpos()
54 args->v0.vtotal = ( total & 0xffff0000) >> 16; in nv50_disp_root_scanoutpos()
55 args->v0.htotal = ( total & 0x0000ffff); in nv50_disp_root_scanoutpos()
56 args->v0.time[0] = ktime_to_ns(ktime_get()); in nv50_disp_root_scanoutpos()
[all …]
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| D | hdmigf119.c | 37 struct nv50_disp_sor_hdmi_pwr_v0 v0; in gf119_hdmi_ctrl() member
43 if (nvif_unpack(args->v0, 0, 0, false)) { in gf119_hdmi_ctrl()
46 args->v0.version, args->v0.state, in gf119_hdmi_ctrl()
47 args->v0.max_ac_packet, args->v0.rekey); in gf119_hdmi_ctrl()
48 if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) in gf119_hdmi_ctrl()
50 ctrl = 0x40000000 * !!args->v0.state; in gf119_hdmi_ctrl()
51 ctrl |= args->v0.max_ac_packet << 16; in gf119_hdmi_ctrl()
52 ctrl |= args->v0.rekey; in gf119_hdmi_ctrl()
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| D | hdmigk104.c | 38 struct nv50_disp_sor_hdmi_pwr_v0 v0; in gk104_hdmi_ctrl() member
44 if (nvif_unpack(args->v0, 0, 0, false)) { in gk104_hdmi_ctrl()
47 args->v0.version, args->v0.state, in gk104_hdmi_ctrl()
48 args->v0.max_ac_packet, args->v0.rekey); in gk104_hdmi_ctrl()
49 if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) in gk104_hdmi_ctrl()
51 ctrl = 0x40000000 * !!args->v0.state; in gk104_hdmi_ctrl()
52 ctrl |= args->v0.max_ac_packet << 16; in gk104_hdmi_ctrl()
53 ctrl |= args->v0.rekey; in gk104_hdmi_ctrl()
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| D | hdmig84.c | 37 struct nv50_disp_sor_hdmi_pwr_v0 v0; in g84_hdmi_ctrl() member
43 if (nvif_unpack(args->v0, 0, 0, false)) { in g84_hdmi_ctrl()
46 args->v0.version, args->v0.state, in g84_hdmi_ctrl()
47 args->v0.max_ac_packet, args->v0.rekey); in g84_hdmi_ctrl()
48 if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) in g84_hdmi_ctrl()
50 ctrl = 0x40000000 * !!args->v0.state; in g84_hdmi_ctrl()
51 ctrl |= args->v0.max_ac_packet << 16; in g84_hdmi_ctrl()
52 ctrl |= args->v0.rekey; in g84_hdmi_ctrl()
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| D | hdmigt215.c | 38 struct nv50_disp_sor_hdmi_pwr_v0 v0; in gt215_hdmi_ctrl() member
44 if (nvif_unpack(args->v0, 0, 0, false)) { in gt215_hdmi_ctrl()
47 args->v0.version, args->v0.state, in gt215_hdmi_ctrl()
48 args->v0.max_ac_packet, args->v0.rekey); in gt215_hdmi_ctrl()
49 if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) in gt215_hdmi_ctrl()
51 ctrl = 0x40000000 * !!args->v0.state; in gt215_hdmi_ctrl()
52 ctrl |= args->v0.max_ac_packet << 16; in gt215_hdmi_ctrl()
53 ctrl |= args->v0.rekey; in gt215_hdmi_ctrl()
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| D | rootgf119.c | 42 struct nv04_disp_scanoutpos_v0 v0; in gf119_disp_root_scanoutpos() member
47 if (nvif_unpack(args->v0, 0, 0, false)) { in gf119_disp_root_scanoutpos()
49 args->v0.version); in gf119_disp_root_scanoutpos()
50 args->v0.vblanke = (blanke & 0xffff0000) >> 16; in gf119_disp_root_scanoutpos()
51 args->v0.hblanke = (blanke & 0x0000ffff); in gf119_disp_root_scanoutpos()
52 args->v0.vblanks = (blanks & 0xffff0000) >> 16; in gf119_disp_root_scanoutpos()
53 args->v0.hblanks = (blanks & 0x0000ffff); in gf119_disp_root_scanoutpos()
54 args->v0.vtotal = ( total & 0xffff0000) >> 16; in gf119_disp_root_scanoutpos()
55 args->v0.htotal = ( total & 0x0000ffff); in gf119_disp_root_scanoutpos()
56 args->v0.time[0] = ktime_to_ns(ktime_get()); in gf119_disp_root_scanoutpos()
[all …]
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| D | ovlynv50.c | 40 struct nv50_disp_overlay_channel_dma_v0 v0; in nv50_disp_ovly_new() member
48 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_disp_ovly_new()
51 args->v0.version, args->v0.pushbuf, args->v0.head); in nv50_disp_ovly_new()
52 if (args->v0.head > disp->base.head.nr) in nv50_disp_ovly_new()
54 push = args->v0.pushbuf; in nv50_disp_ovly_new()
55 head = args->v0.head; in nv50_disp_ovly_new()
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| D | basenv50.c | 40 struct nv50_disp_base_channel_dma_v0 v0; in nv50_disp_base_new() member
48 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_disp_base_new()
51 args->v0.version, args->v0.pushbuf, args->v0.head); in nv50_disp_base_new()
52 if (args->v0.head > disp->base.head.nr) in nv50_disp_base_new()
54 push = args->v0.pushbuf; in nv50_disp_base_new()
55 head = args->v0.head; in nv50_disp_base_new()
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| D | piornv50.c | 40 struct nv50_disp_pior_pwr_v0 v0; in nv50_pior_power() member
46 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_pior_power()
48 args->v0.version, args->v0.state, args->v0.type); in nv50_pior_power()
49 if (args->v0.type > 0x0f) in nv50_pior_power()
51 ctrl = !!args->v0.state; in nv50_pior_power()
52 type = args->v0.type; in nv50_pior_power()
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| /drivers/gpu/drm/nouveau/nvkm/engine/pm/ |
| D | base.c | 263 struct nvif_perfdom_read_v0 v0; in nvkm_perfdom_read() member
270 if (nvif_unpack(args->v0, 0, 0, false)) { in nvkm_perfdom_read()
271 nvif_ioctl(object, "perfdom read vers %d\n", args->v0.version); in nvkm_perfdom_read()
285 args->v0.ctr[i] = dom->ctr[i]->ctr; in nvkm_perfdom_read()
286 args->v0.clk = dom->clk; in nvkm_perfdom_read()
369 struct nvif_perfdom_v0 v0; in nvkm_perfdom_new_() member
380 if (nvif_unpack(args->v0, 0, 0, false)) { in nvkm_perfdom_new_()
382 args->v0.version, args->v0.domain, args->v0.mode); in nvkm_perfdom_new_()
386 for (c = 0; c < ARRAY_SIZE(args->v0.ctr); c++) { in nvkm_perfdom_new_()
390 for (s = 0; s < ARRAY_SIZE(args->v0.ctr[c].signal); s++) { in nvkm_perfdom_new_()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | dmanv50.c | 38 struct nv50_channel_dma_v0 v0; in nv50_fifo_dma_new() member
45 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_fifo_dma_new()
48 args->v0.version, args->v0.vm, args->v0.pushbuf, in nv50_fifo_dma_new()
49 args->v0.offset); in nv50_fifo_dma_new()
50 if (!args->v0.pushbuf) in nv50_fifo_dma_new()
59 ret = nv50_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, in nv50_fifo_dma_new()
64 args->v0.chid = chan->base.chid; in nv50_fifo_dma_new()
67 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
68 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
[all …]
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| D | dmag84.c | 38 struct nv50_channel_dma_v0 v0; in g84_fifo_dma_new() member
45 if (nvif_unpack(args->v0, 0, 0, false)) { in g84_fifo_dma_new()
48 args->v0.version, args->v0.vm, args->v0.pushbuf, in g84_fifo_dma_new()
49 args->v0.offset); in g84_fifo_dma_new()
50 if (!args->v0.pushbuf) in g84_fifo_dma_new()
59 ret = g84_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, in g84_fifo_dma_new()
64 args->v0.chid = chan->base.chid; in g84_fifo_dma_new()
67 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); in g84_fifo_dma_new()
68 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in g84_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); in g84_fifo_dma_new()
[all …]
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| D | gpfifonv50.c | 38 struct nv50_channel_gpfifo_v0 v0; in nv50_fifo_gpfifo_new() member
46 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_fifo_gpfifo_new()
50 args->v0.version, args->v0.vm, args->v0.pushbuf, in nv50_fifo_gpfifo_new()
51 args->v0.ioffset, args->v0.ilength); in nv50_fifo_gpfifo_new()
52 if (!args->v0.pushbuf) in nv50_fifo_gpfifo_new()
61 ret = nv50_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, in nv50_fifo_gpfifo_new()
66 args->v0.chid = chan->base.chid; in nv50_fifo_gpfifo_new()
67 ioffset = args->v0.ioffset; in nv50_fifo_gpfifo_new()
68 ilength = order_base_2(args->v0.ilength / 8); in nv50_fifo_gpfifo_new()
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| D | gpfifog84.c | 38 struct nv50_channel_gpfifo_v0 v0; in g84_fifo_gpfifo_new() member
46 if (nvif_unpack(args->v0, 0, 0, false)) { in g84_fifo_gpfifo_new()
50 args->v0.version, args->v0.vm, args->v0.pushbuf, in g84_fifo_gpfifo_new()
51 args->v0.ioffset, args->v0.ilength); in g84_fifo_gpfifo_new()
52 if (!args->v0.pushbuf) in g84_fifo_gpfifo_new()
61 ret = g84_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, in g84_fifo_gpfifo_new()
66 args->v0.chid = chan->base.chid; in g84_fifo_gpfifo_new()
67 ioffset = args->v0.ioffset; in g84_fifo_gpfifo_new()
68 ilength = order_base_2(args->v0.ilength / 8); in g84_fifo_gpfifo_new()
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| D | dmanv10.c | 40 struct nv03_channel_dma_v0 v0; in nv10_fifo_dma_new() member
49 if (nvif_unpack(args->v0, 0, 0, false)) { in nv10_fifo_dma_new()
51 "offset %08x\n", args->v0.version, in nv10_fifo_dma_new()
52 args->v0.pushbuf, args->v0.offset); in nv10_fifo_dma_new()
53 if (!args->v0.pushbuf) in nv10_fifo_dma_new()
63 0x1000, 0x1000, false, 0, args->v0.pushbuf, in nv10_fifo_dma_new()
72 args->v0.chid = chan->base.chid; in nv10_fifo_dma_new()
76 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv10_fifo_dma_new()
77 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv10_fifo_dma_new()
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| D | dmanv17.c | 40 struct nv03_channel_dma_v0 v0; in nv17_fifo_dma_new() member
49 if (nvif_unpack(args->v0, 0, 0, false)) { in nv17_fifo_dma_new()
51 "offset %08x\n", args->v0.version, in nv17_fifo_dma_new()
52 args->v0.pushbuf, args->v0.offset); in nv17_fifo_dma_new()
53 if (!args->v0.pushbuf) in nv17_fifo_dma_new()
63 0x1000, 0x1000, false, 0, args->v0.pushbuf, in nv17_fifo_dma_new()
73 args->v0.chid = chan->base.chid; in nv17_fifo_dma_new()
77 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv17_fifo_dma_new()
78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv17_fifo_dma_new()
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| /drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| D | user.c | 63 struct nv_dma_v0 v0; in nvkm_dmaobj_ctor() member
80 if (nvif_unpack(args->v0, 0, 0, true)) { in nvkm_dmaobj_ctor()
83 args->v0.version, args->v0.target, args->v0.access, in nvkm_dmaobj_ctor()
84 args->v0.start, args->v0.limit); in nvkm_dmaobj_ctor()
85 dmaobj->target = args->v0.target; in nvkm_dmaobj_ctor()
86 dmaobj->access = args->v0.access; in nvkm_dmaobj_ctor()
87 dmaobj->start = args->v0.start; in nvkm_dmaobj_ctor()
88 dmaobj->limit = args->v0.limit; in nvkm_dmaobj_ctor()
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| D | usernv50.c | 74 struct nv50_dma_v0 v0; in nv50_dmaobj_new() member
93 if (nvif_unpack(args->v0, 0, 0, false)) { in nv50_dmaobj_new()
95 "comp %d kind %02x\n", args->v0.version, in nv50_dmaobj_new()
96 args->v0.priv, args->v0.part, args->v0.comp, in nv50_dmaobj_new()
97 args->v0.kind); in nv50_dmaobj_new()
98 user = args->v0.priv; in nv50_dmaobj_new()
99 part = args->v0.part; in nv50_dmaobj_new()
100 comp = args->v0.comp; in nv50_dmaobj_new()
101 kind = args->v0.kind; in nv50_dmaobj_new()
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