1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "rootnv50.h"
25 #include "dmacnv50.h"
26
27 #include <core/client.h>
28 #include <core/ramht.h>
29 #include <subdev/timer.h>
30
31 #include <nvif/class.h>
32 #include <nvif/unpack.h>
33
34 int
gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0)35 gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0)
36 {
37 struct nvkm_device *device = disp->base.engine.subdev.device;
38 const u32 total = nvkm_rd32(device, 0x640414 + (head * 0x300));
39 const u32 blanke = nvkm_rd32(device, 0x64041c + (head * 0x300));
40 const u32 blanks = nvkm_rd32(device, 0x640420 + (head * 0x300));
41 union {
42 struct nv04_disp_scanoutpos_v0 v0;
43 } *args = data;
44 int ret;
45
46 nvif_ioctl(object, "disp scanoutpos size %d\n", size);
47 if (nvif_unpack(args->v0, 0, 0, false)) {
48 nvif_ioctl(object, "disp scanoutpos vers %d\n",
49 args->v0.version);
50 args->v0.vblanke = (blanke & 0xffff0000) >> 16;
51 args->v0.hblanke = (blanke & 0x0000ffff);
52 args->v0.vblanks = (blanks & 0xffff0000) >> 16;
53 args->v0.hblanks = (blanks & 0x0000ffff);
54 args->v0.vtotal = ( total & 0xffff0000) >> 16;
55 args->v0.htotal = ( total & 0x0000ffff);
56 args->v0.time[0] = ktime_to_ns(ktime_get());
57 args->v0.vline = /* vline read locks hline */
58 nvkm_rd32(device, 0x616340 + (head * 0x800)) & 0xffff;
59 args->v0.time[1] = ktime_to_ns(ktime_get());
60 args->v0.hline =
61 nvkm_rd32(device, 0x616344 + (head * 0x800)) & 0xffff;
62 } else
63 return ret;
64
65 return 0;
66 }
67
68 void
gf119_disp_root_fini(struct nv50_disp_root * root)69 gf119_disp_root_fini(struct nv50_disp_root *root)
70 {
71 struct nvkm_device *device = root->disp->base.engine.subdev.device;
72 /* disable all interrupts */
73 nvkm_wr32(device, 0x6100b0, 0x00000000);
74 }
75
76 int
gf119_disp_root_init(struct nv50_disp_root * root)77 gf119_disp_root_init(struct nv50_disp_root *root)
78 {
79 struct nv50_disp *disp = root->disp;
80 struct nvkm_device *device = disp->base.engine.subdev.device;
81 u32 tmp;
82 int i;
83
84 /* The below segments of code copying values from one register to
85 * another appear to inform EVO of the display capabilities or
86 * something similar.
87 */
88
89 /* ... CRTC caps */
90 for (i = 0; i < disp->base.head.nr; i++) {
91 tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
92 nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp);
93 tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));
94 nvkm_wr32(device, 0x6101b8 + (i * 0x800), tmp);
95 tmp = nvkm_rd32(device, 0x61610c + (i * 0x800));
96 nvkm_wr32(device, 0x6101bc + (i * 0x800), tmp);
97 }
98
99 /* ... DAC caps */
100 for (i = 0; i < disp->func->dac.nr; i++) {
101 tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
102 nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
103 }
104
105 /* ... SOR caps */
106 for (i = 0; i < disp->func->sor.nr; i++) {
107 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
108 nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
109 }
110
111 /* steal display away from vbios, or something like that */
112 if (nvkm_rd32(device, 0x6100ac) & 0x00000100) {
113 nvkm_wr32(device, 0x6100ac, 0x00000100);
114 nvkm_mask(device, 0x6194e8, 0x00000001, 0x00000000);
115 if (nvkm_msec(device, 2000,
116 if (!(nvkm_rd32(device, 0x6194e8) & 0x00000002))
117 break;
118 ) < 0)
119 return -EBUSY;
120 }
121
122 /* point at display engine memory area (hash table, objects) */
123 nvkm_wr32(device, 0x610010, (root->instmem->addr >> 8) | 9);
124
125 /* enable supervisor interrupts, disable everything else */
126 nvkm_wr32(device, 0x610090, 0x00000000);
127 nvkm_wr32(device, 0x6100a0, 0x00000000);
128 nvkm_wr32(device, 0x6100b0, 0x00000307);
129
130 /* disable underflow reporting, preventing an intermittent issue
131 * on some gk104 boards where the production vbios left this
132 * setting enabled by default.
133 *
134 * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
135 */
136 for (i = 0; i < disp->base.head.nr; i++)
137 nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
138
139 return 0;
140 }
141
142 static const struct nv50_disp_root_func
143 gf119_disp_root = {
144 .init = gf119_disp_root_init,
145 .fini = gf119_disp_root_fini,
146 .dmac = {
147 &gf119_disp_core_oclass,
148 &gf119_disp_base_oclass,
149 &gf119_disp_ovly_oclass,
150 },
151 .pioc = {
152 &gf119_disp_oimm_oclass,
153 &gf119_disp_curs_oclass,
154 },
155 };
156
157 static int
gf119_disp_root_new(struct nvkm_disp * disp,const struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)158 gf119_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
159 void *data, u32 size, struct nvkm_object **pobject)
160 {
161 return nv50_disp_root_new_(&gf119_disp_root, disp, oclass,
162 data, size, pobject);
163 }
164
165 const struct nvkm_disp_oclass
166 gf119_disp_root_oclass = {
167 .base.oclass = GF110_DISP,
168 .base.minver = -1,
169 .base.maxver = -1,
170 .ctor = gf119_disp_root_new,
171 };
172