| /drivers/gpu/drm/armada/ |
| D | armada_overlay.c | 43 } vbl; member
93 armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); in armada_ovl_plane_work()
206 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0], in armada_ovl_plane_update()
208 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1], in armada_ovl_plane_update()
210 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2], in armada_ovl_plane_update()
212 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0], in armada_ovl_plane_update()
214 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1], in armada_ovl_plane_update()
216 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2], in armada_ovl_plane_update()
220 armada_reg_queue_set(dplane->vbl.regs, idx, val, in armada_ovl_plane_update()
223 armada_reg_queue_set(dplane->vbl.regs, idx, val, in armada_ovl_plane_update()
[all …]
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| /drivers/gpu/drm/radeon/ |
| D | radeon_display.c | 1868 u32 stat_crtc = 0, vbl = 0, position = 0; in radeon_get_crtc_scanoutpos() local
1882 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1889 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1896 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1903 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1910 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1917 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + in radeon_get_crtc_scanoutpos()
1925 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); in radeon_get_crtc_scanoutpos()
1930 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); in radeon_get_crtc_scanoutpos()
1940 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & in radeon_get_crtc_scanoutpos()
[all …]
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_display.c | 806 u32 vbl = 0, position = 0; in amdgpu_get_crtc_scanoutpos() local
818 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) in amdgpu_get_crtc_scanoutpos()
832 if (vbl > 0) { in amdgpu_get_crtc_scanoutpos()
835 vbl_start = vbl & 0x1fff; in amdgpu_get_crtc_scanoutpos()
836 vbl_end = (vbl >> 16) & 0x1fff; in amdgpu_get_crtc_scanoutpos()
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| D | amdgpu_mode.h | 287 u32 *vbl, u32 *position);
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| D | amdgpu.h | 2273 …age_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((a… argument
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| D | dce_v8_0.c | 251 u32 *vbl, u32 *position) in dce_v8_0_crtc_get_scanoutpos() argument
256 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
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| D | dce_v10_0.c | 302 u32 *vbl, u32 *position) in dce_v10_0_crtc_get_scanoutpos() argument
307 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
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| D | dce_v11_0.c | 292 u32 *vbl, u32 *position) in dce_v11_0_crtc_get_scanoutpos() argument
297 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv40.c | 80 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog() local
83 if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) { in nv40_ram_prog()
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| /drivers/video/fbdev/aty/ |
| D | atyfb_base.c | 1775 struct aty_interrupt *vbl; in aty_waitforvblank() local
1781 vbl = &par->vblank; in aty_waitforvblank()
1791 count = vbl->count; in aty_waitforvblank()
1792 ret = wait_event_interruptible_timeout(vbl->wait, in aty_waitforvblank()
1793 count != vbl->count, HZ/10); in aty_waitforvblank()
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| /drivers/video/fbdev/matrox/ |
| D | matroxfb_base.c | 312 int vbl; in matrox_pan_var() local
332 vbl = (var->activate & FB_ACTIVATE_VBL) && (matroxfb_enable_irq(minfo, 0) == 0); in matrox_pan_var()
341 if (vbl) { in matrox_pan_var()
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