| /drivers/clk/spear/ |
| D | clk-vco-pll.c | 97 for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { in clk_pll_round_rate_index()
100 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, in clk_pll_round_rate_index()
131 if (pll->vco->lock) in clk_pll_recalc_rate()
132 spin_lock_irqsave(pll->vco->lock, flags); in clk_pll_recalc_rate()
134 p = readl_relaxed(pll->vco->cfg_reg); in clk_pll_recalc_rate()
136 if (pll->vco->lock) in clk_pll_recalc_rate()
137 spin_unlock_irqrestore(pll->vco->lock, flags); in clk_pll_recalc_rate()
148 struct pll_rate_tbl *rtbl = pll->vco->rtbl; in clk_pll_set_rate()
154 if (pll->vco->lock) in clk_pll_set_rate()
155 spin_lock_irqsave(pll->vco->lock, flags); in clk_pll_set_rate()
[all …]
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| D | Makefile | 5 obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
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| D | clk.h | 104 struct clk_vco *vco; member
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| /drivers/cpufreq/ |
| D | integrator-cpufreq.c | 61 struct icst_vco vco; in integrator_verify_policy() local
65 vco = icst_hz_to_vco(&cclk_params, policy->max * 1000); in integrator_verify_policy()
66 policy->max = icst_hz(&cclk_params, vco) / 1000; in integrator_verify_policy()
68 vco = icst_hz_to_vco(&cclk_params, policy->min * 1000); in integrator_verify_policy()
69 policy->min = icst_hz(&cclk_params, vco) / 1000; in integrator_verify_policy()
82 struct icst_vco vco; in integrator_set_target() local
102 vco.s = (cm_osc >> 8) & 7; in integrator_set_target()
104 vco.s = 1; in integrator_set_target()
105 vco.v = cm_osc & 255; in integrator_set_target()
106 vco.r = 22; in integrator_set_target()
[all …]
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| /drivers/clk/versatile/ |
| D | clk-icst.c | 50 struct icst_vco vco; in vco_get() local
53 vco.v = val & 0x1ff; in vco_get()
54 vco.r = (val >> 9) & 0x7f; in vco_get()
55 vco.s = (val >> 16) & 03; in vco_get()
56 return vco; in vco_get()
67 struct icst_vco vco) in vco_set() argument
72 val |= vco.v | (vco.r << 9) | (vco.s << 16); in vco_set()
86 struct icst_vco vco; in icst_recalc_rate() local
90 vco = vco_get(icst->vcoreg); in icst_recalc_rate()
91 icst->rate = icst_hz(icst->params, vco); in icst_recalc_rate()
[all …]
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| /drivers/clk/berlin/ |
| D | berlin2-avpll.c | 126 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_is_enabled() local
129 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
130 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
138 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_enable() local
141 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
142 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_enable()
146 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
153 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_disable() local
156 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
157 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_disable()
[all …]
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| /drivers/clk/pistachio/ |
| D | clk-pll.c | 202 u64 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_frac_set_rate() local
213 vco = params->fref; in pll_gf40lp_frac_set_rate()
214 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
215 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
217 if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC) in pll_gf40lp_frac_set_rate()
218 pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco, in pll_gf40lp_frac_set_rate()
225 if (val > vco / 16) in pll_gf40lp_frac_set_rate()
227 name, val, vco / 16); in pll_gf40lp_frac_set_rate()
359 u32 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_laint_set_rate() local
369 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
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| /drivers/video/fbdev/matrox/ |
| D | g450_pll.c | 106 unsigned int *vco, unsigned int fout) in g450_firstpll() argument
114 *vco = vcomax; in g450_firstpll()
116 *vco = fout; in g450_firstpll()
131 *vco = tvco; in g450_firstpll()
133 return g450_nextpll(minfo, pi, vco, 0xFF0000 | p); in g450_firstpll()
440 unsigned int vco; in __g450_setclk() local
443 vco = g450_mnp2vco(minfo, mnp); in __g450_setclk()
448 if (vco < pixel_vco) { in __g450_setclk()
449 small = vco; in __g450_setclk()
453 big = vco; in __g450_setclk()
[all …]
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| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_display.c | 47 .vco = {.min = 1800000, .max = 3600000},
59 .vco = {.min = 1800000, .max = 3600000},
74 .vco = {.min = 1809000, .max = 3564000},
86 .vco = {.min = 1800000, .max = 3600000},
98 .vco = {.min = 1809000, .max = 3564000},
110 .vco = {.min = 1800000, .max = 3600000},
299 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
302 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
305 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
406 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
[all …]
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| D | gma_display.h | 34 int vco; member
49 struct gma_range_t dot, vco, n, m, m1, m2, p, p1; member
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| D | psb_intel_display.c | 38 .vco = {.min = 1400000, .max = 2800000},
50 .vco = {.min = 1400000, .max = 2800000},
81 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
82 clock->dot = clock->vco / clock->p; in psb_intel_clock()
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| D | oaktrail_hdmi.c | 102 struct intel_range vco, np, nr, nf; member
122 .vco = { .min = VCO_MIN, .max = VCO_MAX },
180 np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10); in oaktrail_hdmi_find_dpll()
181 np_max = oaktrail_hdmi_limit.vco.max / (target * 10); in oaktrail_hdmi_find_dpll()
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| D | gma_display.c | 718 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in gma_pll_is_valid()
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| D | oaktrail_crtc.c | 74 .vco = {.min = 1400000, .max = 2800000},
154 if (target_vco > limit->vco.max) in mrst_sdvo_find_best_pll()
157 if (target_vco < limit->vco.min) in mrst_sdvo_find_best_pll()
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| /drivers/clk/mediatek/ |
| D | clk-pll.c | 71 u64 vco; in __mtk_pll_recalc_rate() local
77 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
79 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) in __mtk_pll_recalc_rate()
82 vco >>= pcwfbits; in __mtk_pll_recalc_rate()
85 vco++; in __mtk_pll_recalc_rate()
87 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
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| /drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 247 const struct iproc_pll_vco_param *vco = &pll->vco_param[rate_index]; in pll_set_rate() local
250 unsigned long rate = vco->rate; in pll_set_rate()
259 if (vco->pdiv == 0) in pll_set_rate()
262 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
312 val |= vco->ndiv_int << ctrl->ndiv_int.shift; in pll_set_rate()
320 val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; in pll_set_rate()
328 val |= vco->pdiv << ctrl->pdiv.shift; in pll_set_rate()
591 const struct iproc_pll_vco_param *vco, in iproc_pll_clk_setup() argument
659 if (vco) { in iproc_pll_clk_setup()
661 pll->vco_param = vco; in iproc_pll_clk_setup()
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| D | clk-iproc.h | 189 const struct iproc_pll_vco_param *vco,
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| /drivers/media/i2c/soc_camera/ |
| D | mt9t112.c | 280 u32 vco, clk; in mt9t112_clock_info() local
309 vco = 2 * m * ext / (n+1); in mt9t112_clock_info()
310 enable = ((384000 > vco) || (768000 < vco)) ? "X" : ""; in mt9t112_clock_info()
311 dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable); in mt9t112_clock_info()
313 clk = vco / (p1+1) / (p2+1); in mt9t112_clock_info()
317 clk = vco / (p3+1); in mt9t112_clock_info()
321 clk = vco / (p6+1); in mt9t112_clock_info()
325 clk = vco / (p5+1); in mt9t112_clock_info()
329 clk = vco / (p4+1); in mt9t112_clock_info()
333 clk = vco / (p7+1); in mt9t112_clock_info()
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| /drivers/media/tuners/ |
| D | max2165.c | 238 u8 vco, vco_sub_band, adc; in max2165_debug_status() local
250 vco = autotune >> 6; in max2165_debug_status()
260 dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc); in max2165_debug_status()
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| /drivers/gpu/drm/i915/ |
| D | intel_display.c | 132 intel_range_t dot, vco, n, m, m1, m2, p, p1; member
238 .vco = { .min = 908000, .max = 1512000 },
251 .vco = { .min = 908000, .max = 1512000 },
264 .vco = { .min = 908000, .max = 1512000 },
277 .vco = { .min = 1400000, .max = 2800000 },
290 .vco = { .min = 1400000, .max = 2800000 },
304 .vco = { .min = 1750000, .max = 3500000},
319 .vco = { .min = 1750000, .max = 3500000},
332 .vco = { .min = 1750000, .max = 3500000 },
346 .vco = { .min = 1750000, .max = 3500000 },
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| D | intel_ddi.c | 1660 int vco = 0; in bxt_ddi_pll_select() local
1687 vco = best_clock.vco; in bxt_ddi_pll_select()
1699 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; in bxt_ddi_pll_select()
1702 if (vco >= 6200000 && vco <= 6700000) { in bxt_ddi_pll_select()
1707 } else if ((vco > 5400000 && vco < 6200000) || in bxt_ddi_pll_select()
1708 (vco >= 4800000 && vco < 5400000)) { in bxt_ddi_pll_select()
1713 } else if (vco == 5400000) { in bxt_ddi_pll_select()
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| /drivers/media/dvb-frontends/ |
| D | cx24120.c | 1246 u32 nxtal_khz, vco; in cx24120_set_vco() local
1251 vco = nxtal_khz * 10; in cx24120_set_vco()
1252 inv_vco = DIV_ROUND_CLOSEST_ULL(0x400000000ULL, vco); in cx24120_set_vco()
1255 xtal_khz, vco, inv_vco); in cx24120_set_vco()
1259 cmd.arg[0] = (vco >> 16) & 0xff; in cx24120_set_vco()
1260 cmd.arg[1] = (vco >> 8) & 0xff; in cx24120_set_vco()
1261 cmd.arg[2] = vco & 0xff; in cx24120_set_vco()
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| /drivers/gpu/drm/radeon/ |
| D | cypress_dpm.c | 444 u32 vco = clkf * ref_clk; in cypress_map_clkf_to_ibias() local
448 if (vco > 500000) in cypress_map_clkf_to_ibias()
450 if (vco > 400000) in cypress_map_clkf_to_ibias()
452 if (vco > 330000) in cypress_map_clkf_to_ibias()
454 if (vco > 250000) in cypress_map_clkf_to_ibias()
456 if (vco > 160000) in cypress_map_clkf_to_ibias()
458 if (vco > 120000) in cypress_map_clkf_to_ibias()
464 if (vco > 250000) in cypress_map_clkf_to_ibias()
466 if (vco > 200000) in cypress_map_clkf_to_ibias()
468 if (vco > 150000) in cypress_map_clkf_to_ibias()
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| D | radeon_display.c | 1229 uint32_t vco; in radeon_compute_pll_legacy() local
1238 vco = radeon_div(tmp, ref_div); in radeon_compute_pll_legacy()
1240 if (vco < pll_out_min) { in radeon_compute_pll_legacy()
1243 } else if (vco > pll_out_max) { in radeon_compute_pll_legacy()
1261 vco_diff = abs(vco - best_vco); in radeon_compute_pll_legacy()
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| /drivers/gpu/drm/mgag200/ |
| D | mgag200_mode.c | 600 unsigned int computed, vco; in mga_g200er_set_plls() local
621 vco = pllreffreq * (testn + 1) / in mga_g200er_set_plls()
623 if (vco < vcomin) in mga_g200er_set_plls()
625 if (vco > vcomax) in mga_g200er_set_plls()
627 computed = vco / (m_div_val[testm] * (testo + 1)); in mga_g200er_set_plls()
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