1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef _CLK_IPROC_H 15 #define _CLK_IPROC_H 16 17 #include <linux/kernel.h> 18 #include <linux/list.h> 19 #include <linux/spinlock.h> 20 #include <linux/slab.h> 21 #include <linux/device.h> 22 #include <linux/of.h> 23 #include <linux/clk-provider.h> 24 25 #define IPROC_CLK_NAME_LEN 25 26 #define IPROC_CLK_INVALID_OFFSET 0xffffffff 27 #define bit_mask(width) ((1 << (width)) - 1) 28 29 /* clocks that should not be disabled at runtime */ 30 #define IPROC_CLK_AON BIT(0) 31 32 /* PLL that requires gating through ASIU */ 33 #define IPROC_CLK_PLL_ASIU BIT(1) 34 35 /* PLL that has fractional part of the NDIV */ 36 #define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2) 37 38 /* 39 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back 40 * of the same register following the write to flush the write transaction into 41 * the intended register 42 */ 43 #define IPROC_CLK_NEEDS_READ_BACK BIT(3) 44 45 /* 46 * Some PLLs require the PLL SW override bit to be set before changes can be 47 * applied to the PLL 48 */ 49 #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4) 50 51 /* 52 * Some PLLs use a different way to control clock power, via the PWRDWN bit in 53 * the PLL control register 54 */ 55 #define IPROC_CLK_EMBED_PWRCTRL BIT(5) 56 57 /* 58 * Some PLLs have separate registers for Status and Control. Identify this to 59 * let the driver know if additional registers need to be used 60 */ 61 #define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6) 62 63 /* 64 * Parameters for VCO frequency configuration 65 * 66 * VCO frequency = 67 * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv) 68 */ 69 struct iproc_pll_vco_param { 70 unsigned long rate; 71 unsigned int ndiv_int; 72 unsigned int ndiv_frac; 73 unsigned int pdiv; 74 }; 75 76 struct iproc_clk_reg_op { 77 unsigned int offset; 78 unsigned int shift; 79 unsigned int width; 80 }; 81 82 /* 83 * Clock gating control at the top ASIU level 84 */ 85 struct iproc_asiu_gate { 86 unsigned int offset; 87 unsigned int en_shift; 88 }; 89 90 /* 91 * Control of powering on/off of a PLL 92 * 93 * Before powering off a PLL, input isolation (ISO) needs to be enabled 94 */ 95 struct iproc_pll_aon_pwr_ctrl { 96 unsigned int offset; 97 unsigned int pwr_width; 98 unsigned int pwr_shift; 99 unsigned int iso_shift; 100 }; 101 102 /* 103 * Control of the PLL reset 104 */ 105 struct iproc_pll_reset_ctrl { 106 unsigned int offset; 107 unsigned int reset_shift; 108 unsigned int p_reset_shift; 109 }; 110 111 /* 112 * Control of the Ki, Kp, and Ka parameters 113 */ 114 struct iproc_pll_dig_filter_ctrl { 115 unsigned int offset; 116 unsigned int ki_shift; 117 unsigned int ki_width; 118 unsigned int kp_shift; 119 unsigned int kp_width; 120 unsigned int ka_shift; 121 unsigned int ka_width; 122 }; 123 124 /* 125 * To enable SW control of the PLL 126 */ 127 struct iproc_pll_sw_ctrl { 128 unsigned int offset; 129 unsigned int shift; 130 }; 131 132 struct iproc_pll_vco_ctrl { 133 unsigned int u_offset; 134 unsigned int l_offset; 135 }; 136 137 /* 138 * Main PLL control parameters 139 */ 140 struct iproc_pll_ctrl { 141 unsigned long flags; 142 struct iproc_pll_aon_pwr_ctrl aon; 143 struct iproc_asiu_gate asiu; 144 struct iproc_pll_reset_ctrl reset; 145 struct iproc_pll_dig_filter_ctrl dig_filter; 146 struct iproc_pll_sw_ctrl sw_ctrl; 147 struct iproc_clk_reg_op ndiv_int; 148 struct iproc_clk_reg_op ndiv_frac; 149 struct iproc_clk_reg_op pdiv; 150 struct iproc_pll_vco_ctrl vco_ctrl; 151 struct iproc_clk_reg_op status; 152 }; 153 154 /* 155 * Controls enabling/disabling a PLL derived clock 156 */ 157 struct iproc_clk_enable_ctrl { 158 unsigned int offset; 159 unsigned int enable_shift; 160 unsigned int hold_shift; 161 unsigned int bypass_shift; 162 }; 163 164 /* 165 * Main clock control parameters for clocks derived from the PLLs 166 */ 167 struct iproc_clk_ctrl { 168 unsigned int channel; 169 unsigned long flags; 170 struct iproc_clk_enable_ctrl enable; 171 struct iproc_clk_reg_op mdiv; 172 }; 173 174 /* 175 * Divisor of the ASIU clocks 176 */ 177 struct iproc_asiu_div { 178 unsigned int offset; 179 unsigned int en_shift; 180 unsigned int high_shift; 181 unsigned int high_width; 182 unsigned int low_shift; 183 unsigned int low_width; 184 }; 185 186 void __init iproc_armpll_setup(struct device_node *node); 187 void __init iproc_pll_clk_setup(struct device_node *node, 188 const struct iproc_pll_ctrl *pll_ctrl, 189 const struct iproc_pll_vco_param *vco, 190 unsigned int num_vco_entries, 191 const struct iproc_clk_ctrl *clk_ctrl, 192 unsigned int num_clks); 193 void __init iproc_asiu_setup(struct device_node *node, 194 const struct iproc_asiu_div *div, 195 const struct iproc_asiu_gate *gate, 196 unsigned int num_clks); 197 198 #endif /* _CLK_IPROC_H */ 199