| /arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7269.c | 50 static struct clk pll_clk = { variable
67 .parent = &pll_clk,
82 .parent = &pll_clk,
89 &pll_clk,
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
145 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-sh7264.c | 54 static struct clk pll_clk = { variable
63 &pll_clk,
81 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
111 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7722.c | 94 static struct clk pll_clk = { variable
103 &pll_clk,
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
150 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
186 CLKDEV_CON_ID("pll_clk", &pll_clk),
238 pll_clk.parent = &dll_clk; in arch_clk_init()
240 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-sh7757.c | 40 static struct clk pll_clk = { variable
48 &pll_clk,
66 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
108 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-shx3.c | 39 static struct clk pll_clk = { variable
47 &pll_clk,
65 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
106 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-sh7366.c | 91 static struct clk pll_clk = { variable
100 &pll_clk,
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
137 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
200 CLKDEV_CON_ID("pll_clk", &pll_clk),
263 pll_clk.parent = &dll_clk; in arch_clk_init()
265 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-sh7343.c | 88 static struct clk pll_clk = { variable
97 &pll_clk,
118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
134 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
202 CLKDEV_CON_ID("pll_clk", &pll_clk),
270 pll_clk.parent = &dll_clk; in arch_clk_init()
272 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-sh7723.c | 95 static struct clk pll_clk = { variable
104 &pll_clk,
124 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
150 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
211 CLKDEV_CON_ID("pll_clk", &pll_clk),
286 pll_clk.parent = &dll_clk; in arch_clk_init()
288 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-sh7785.c | 43 static struct clk pll_clk = { variable
51 &pll_clk,
70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
122 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-sh7724.c | 97 static struct clk pll_clk = { variable
114 .parent = &pll_clk,
131 &pll_clk,
163 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
276 CLKDEV_CON_ID("pll_clk", &pll_clk),
360 pll_clk.parent = &fll_clk; in arch_clk_init()
362 pll_clk.parent = &extal_clk; in arch_clk_init()
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| D | clock-sh7786.c | 45 static struct clk pll_clk = { variable
53 &pll_clk,
71 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
131 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| D | clock-sh7734.c | 45 static struct clk pll_clk = { variable
53 &pll_clk,
73 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
184 CLKDEV_CON_ID("pll_clk", &pll_clk),
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| /arch/blackfin/mach-bf609/ |
| D | clock.c | 285 static struct clk pll_clk = { variable
357 .parent = &pll_clk,
380 CLK(pll_clk, NULL, "PLLCLK"),
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| /arch/arm/boot/dts/ |
| D | exynos4415.dtsi | 266 clock-names = "bus_clk", "pll_clk";
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| D | exynos3250.dtsi | 311 clock-names = "bus_clk", "pll_clk";
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| D | exynos5420.dtsi | 525 clock-names = "bus_clk", "pll_clk";
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