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Searched refs:readl (Results 1 – 25 of 192) sorted by relevance

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/arch/unicore32/kernel/
Dtime.c29 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_ost0_interrupt()
30 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_ost0_interrupt()
41 writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER); in puv3_osmr0_set_next_event()
42 next = readl(OST_OSCR) + delta; in puv3_osmr0_set_next_event()
44 oscr = readl(OST_OSCR); in puv3_osmr0_set_next_event()
51 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_osmr0_shutdown()
52 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_osmr0_shutdown()
67 return readl(OST_OSCR); in puv3_read_oscr()
109 osmr[0] = readl(OST_OSMR0); in puv3_timer_suspend()
110 osmr[1] = readl(OST_OSMR1); in puv3_timer_suspend()
[all …]
Dirq.c84 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); in puv3_low_gpio_mask()
89 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); in puv3_low_gpio_unmask()
95 writel(readl(PM_PWER) | (1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
97 writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
119 mask = readl(GPIO_GEDR); in puv3_gpio_handler()
134 mask = readl(GPIO_GEDR); in puv3_gpio_handler()
156 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); in puv3_high_gpio_mask()
157 writel(readl(GPIO_GFER) & ~mask, GPIO_GFER); in puv3_high_gpio_mask()
173 writel(readl(PM_PWER) | PM_PWER_GPIOHIGH, PM_PWER); in puv3_high_gpio_wake()
175 writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER); in puv3_high_gpio_wake()
[all …]
Dclock.c156 if (readl(PM_PLLVGACFG) == pll_vgacfg) in clk_set_rate()
163 while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC) in clk_set_rate()
168 writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR); in clk_set_rate()
170 writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK) in clk_set_rate()
173 writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET); in clk_set_rate()
174 while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV) in clk_set_rate()
178 writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR); in clk_set_rate()
182 u32 pll_rate, divstatus = readl(PM_DIVSTATUS); in clk_set_rate()
207 while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_SYSDFC) in clk_set_rate()
328 u32 pllrate, divstatus = readl(PM_DIVSTATUS); in clk_init()
[all …]
/arch/arm/mach-dove/
Dmpp.c63 readl(DOVE_MPP_CTRL4_VIRT_BASE)); in dove_mpp_dump_regs()
66 readl(DOVE_PMU_MPP_GENERAL_CTRL)); in dove_mpp_dump_regs()
68 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); in dove_mpp_dump_regs()
73 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_nfc()
84 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_cfg_au1()
85 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); in dove_mpp_cfg_au1()
86 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_au1()
87 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); in dove_mpp_cfg_au1()
124 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_conf_grp()
/arch/arm/mach-netx/include/mach/
Dpfifo.h32 return readl(NETX_PFIFO_BASE(no)); in pfifo_pop()
38 return readl(NETX_PFIFO_FILL_LEVEL(no)); in pfifo_fill_level()
43 return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0; in pfifo_full()
48 return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0; in pfifo_empty()
/arch/arm/plat-orion/
Dtime.c66 return ~readl(timer_base + TIMER0_VAL_OFF); in orion_read_sched_clock()
88 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
100 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
117 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_shutdown()
121 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_shutdown()
144 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_set_periodic()
148 u = readl(timer_base + TIMER_CTRL_OFF); in orion_clkevt_set_periodic()
216 u = readl(bridge_base + BRIDGE_MASK_OFF); in orion_time_init()
218 u = readl(timer_base + TIMER_CTRL_OFF); in orion_time_init()
Dpcie.c57 return readl(base + PCIE_DEV_ID_OFF) >> 16; in orion_pcie_dev_id()
62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; in orion_pcie_rev()
67 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); in orion_pcie_link_up()
72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); in orion_pcie_x4_mode()
77 u32 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_get_local_bus_nr()
86 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
103 reg = readl(base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
203 mask = readl(base + PCIE_MASK_OFF); in orion_pcie_setup()
217 *val = readl(base + PCIE_CONF_DATA_OFF); in orion_pcie_rd_conf()
236 *val = readl(base + PCIE_CONF_DATA_OFF); in orion_pcie_rd_conf_tlp()
[all …]
Dgpio.c100 u = readl(GPIO_IO_CONF(ochip)); in __set_direction()
112 u = readl(GPIO_OUT(ochip)); in __set_level()
125 u = readl(GPIO_BLINK_EN(ochip)); in __set_blinking()
189 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { in orion_gpio_get()
190 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); in orion_gpio_get()
192 val = readl(GPIO_OUT(ochip)); in orion_gpio_get()
367 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); in gpio_irq_set_type()
385 u = readl(GPIO_IN_POL(ochip)); in gpio_irq_set_type()
389 u = readl(GPIO_IN_POL(ochip)); in gpio_irq_set_type()
395 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); in gpio_irq_set_type()
[all …]
/arch/arm/mach-s3c64xx/
Dsetup-usb-phy.c29 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_init()
32 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; in s3c_usb_otgphy_init()
55 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); in s3c_usb_otgphy_init()
69 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | in s3c_usb_otgphy_exit()
72 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_exit()
/arch/mips/include/asm/mach-ar7/
Dar7.h124 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == in ar7_is_titan()
130 return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *) in ar7_chip_id()
136 unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + in titan_chip_id()
143 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : in ar7_chip_rev()
171 writel(readl(reset_reg) | (1 << bit), reset_reg); in ar7_device_enable()
179 writel(readl(reset_reg) & ~(1 << bit), reset_reg); in ar7_device_disable()
192 writel(readl(power_reg) | (1 << bit), power_reg); in ar7_device_on()
199 writel(readl(power_reg) & ~(1 << bit), power_reg); in ar7_device_off()
/arch/arm/mach-gemini/
Dtime.c68 return readl(TIMER_COUNT(TIMER3_BASE)); in gemini_read_sched_clock()
77 cr = readl(TIMER_COUNT(TIMER1_BASE)); in gemini_timer_set_next_event()
79 if (readl(TIMER_COUNT(TIMER1_BASE)) - cr > cycles) in gemini_timer_set_next_event()
94 cr = readl(TIMER_CR); in gemini_timer_shutdown()
103 cr = readl(TIMER_INTR_MASK); in gemini_timer_shutdown()
109 cr = readl(TIMER_CR); in gemini_timer_shutdown()
122 cr = readl(TIMER_CR); in gemini_timer_set_periodic()
132 cr = readl(TIMER_INTR_MASK); in gemini_timer_set_periodic()
138 cr = readl(TIMER_CR); in gemini_timer_set_periodic()
185 reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); in gemini_timer_init()
/arch/mips/ar7/
Dgpio.c40 return readl(gpio_in) & (1 << gpio); in ar7_gpio_get_value()
50 return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f)); in titan_gpio_get_value()
61 tmp = readl(gpio_out) & ~(1 << gpio); in ar7_gpio_set_value()
76 tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f)); in titan_gpio_set_value()
88 writel(readl(gpio_dir) | (1 << gpio), gpio_dir); in ar7_gpio_direction_input()
103 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), in titan_gpio_direction_input()
116 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir); in ar7_gpio_direction_output()
133 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << in titan_gpio_direction_output()
167 writel(readl(gpio_en) | (1 << gpio), gpio_en); in ar7_gpio_enable_ar7()
177 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), in ar7_gpio_enable_titan()
[all …]
Dclock.c160 didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18)); in tnetd7300_dsp_clock()
161 didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c)); in tnetd7300_dsp_clock()
177 u32 ctrl = readl(&clock->ctrl); in tnetd7300_get_clock()
178 u32 pll = readl(&clock->pll); in tnetd7300_get_clock()
244 while (readl(&clock->pll) & PLL_STATUS) in tnetd7300_set_clock()
286 while (readl(&clock->status) & 0x1) in tnetd7200_set_clock()
291 writel(readl(&clock->cmden) | 1, &clock->cmden); in tnetd7200_set_clock()
292 writel(readl(&clock->cmd) | 1, &clock->cmd); in tnetd7200_set_clock()
294 while (readl(&clock->status) & 0x1) in tnetd7200_set_clock()
299 writel(readl(&clock->cmden) | 1, &clock->cmden); in tnetd7200_set_clock()
[all …]
/arch/arm/mach-ux500/
Dpm.c52 u32 val = readl(PRCM_A9_MASK_REQ); in prcmu_gic_decouple()
59 readl(PRCM_A9_MASK_REQ); in prcmu_gic_decouple()
70 u32 val = readl(PRCM_A9_MASK_REQ); in prcmu_gic_recouple()
120 it = readl(PRCM_ARMITVAL31TO0 + i * 4); in prcmu_pending_irq()
121 im = readl(PRCM_ARMITMSK31TO0 + i * 4); in prcmu_pending_irq()
137 return readl(PRCM_ARM_WFI_STANDBY) & in prcmu_is_cpu_in_wfi()
Dcpu-db8500.c86 readl((u32 *)uid+0), in db8500_read_soc_id()
87 readl((u32 *)uid+1), readl((u32 *)uid+2), in db8500_read_soc_id()
88 readl((u32 *)uid+3), readl((u32 *)uid+4)); in db8500_read_soc_id()
/arch/arm/mach-netx/
Dgeneric.c77 stat = ((readl(NETX_DPMAS_INT_EN) & in netx_hif_demux_handler()
78 readl(NETX_DPMAS_INT_STAT)) >> 24) & 0x1f; in netx_hif_demux_handler()
95 val = readl(NETX_DPMAS_IF_CONF1); in netx_hif_irq_type()
129 val = readl(NETX_DPMAS_INT_EN); in netx_hif_ack_irq()
142 val = readl(NETX_DPMAS_INT_EN); in netx_hif_mask_irq()
154 val = readl(NETX_DPMAS_INT_EN); in netx_hif_unmask_irq()
/arch/arm/mach-clps711x/
Ddevices.c111 id[0] = readl(base + UNIQID); in clps711x_soc_init()
112 id[1] = readl(base + RANDID0); in clps711x_soc_init()
113 id[2] = readl(base + RANDID1); in clps711x_soc_init()
114 id[3] = readl(base + RANDID2); in clps711x_soc_init()
115 id[4] = readl(base + RANDID3); in clps711x_soc_init()
116 system_rev = SYSFLG1_VERID(readl(base + SYSFLG1)); in clps711x_soc_init()
/arch/arm/mach-cns3xxx/
Dcore.c104 clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET); in cns3xxx_power_off()
124 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_oneshot()
134 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_periodic()
148 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_next_event()
187 val = readl(stat); in cns3xxx_timer_interrupt()
226 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
232 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
241 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); in __cns3xxx_timer_init()
246 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
282 val = readl(base + L310_TAG_LATENCY_CTRL); in cns3xxx_l2x0_init()
[all …]
/arch/sparc/kernel/
Debus.c61 val = readl(p->regs + EBDMA_CSR); in __ebus_dma_reset()
76 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
135 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
141 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
162 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_unregister()
185 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_request()
230 return readl(p->regs + EBDMA_COUNT); in ebus_dma_residue()
236 return readl(p->regs + EBDMA_ADDR); in ebus_dma_addr()
246 orig_csr = csr = readl(p->regs + EBDMA_CSR); in ebus_dma_enable()
/arch/arm/mach-sunxi/
Dplatsmp.c90 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun6i_smp_boot_secondary()
94 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
103 reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); in sun6i_smp_boot_secondary()
111 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
172 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun8i_smp_boot_secondary()
176 reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); in sun8i_smp_boot_secondary()
/arch/arm/mach-mvebu/
Dpmsu.c216 reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); in mvebu_v7_pmsu_enable_l2_powerdown_onidle()
241 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
250 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
261 reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
350 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_exit()
355 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_exit()
453 reg = readl(mpsoc_base + MPCORE_RESET_CTL); in armada_38x_cpuidle_init()
460 reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY); in armada_38x_cpuidle_init()
547 reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); in mvebu_pmsu_dfs_request_local()
554 reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); in mvebu_pmsu_dfs_request_local()
[all …]
/arch/arm/mach-mv78xx0/
Dcommon.c54 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { in get_hclk()
72 readl(SAMPLE_AT_RESET_LOW)); in get_hclk()
87 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; in get_pclk_l2clk()
89 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; in get_pclk_l2clk()
112 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { in get_tclk()
121 readl(SAMPLE_AT_RESET_HIGH)); in get_tclk()
387 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); in is_l2_writethrough()
/arch/mips/mti-sead3/
Dsead3-time.c32 orig = readl(status_reg) & 0x2; /* get original sample */ in estimate_cpu_frequency()
34 while ((readl(status_reg) & 0x2) == orig) in estimate_cpu_frequency()
43 while ((readl(status_reg) & 0x2) == orig) in estimate_cpu_frequency()
/arch/arm/mach-ep93xx/
Dtimer-ep93xx.c57 ret = readl(EP93XX_TIMER4_VALUE_LOW); in ep93xx_read_sched_clock()
58 ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); in ep93xx_read_sched_clock()
66 ret = readl(EP93XX_TIMER4_VALUE_LOW); in ep93xx_clocksource_read()
67 ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); in ep93xx_clocksource_read()
/arch/unicore32/include/mach/
Ddma.h40 writel(readl(DMAC_CONFIG(ch)) & ~DMAC_CONFIG_EN, DMAC_CONFIG(ch)); in puv3_stop_dma()
45 writel(readl(DMAC_CONFIG(ch)) | DMAC_CONFIG_EN, DMAC_CONFIG(ch)); in puv3_resume_dma()

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