1============================================================================= 2Freescale Frame Manager Device Bindings 3 4CONTENTS 5 - FMan Node 6 - FMan Port Node 7 - FMan MURAM Node 8 - FMan dTSEC/XGEC/mEMAC Node 9 - FMan IEEE 1588 Node 10 - FMan MDIO Node 11 - Example 12 13============================================================================= 14FMan Node 15 16DESCRIPTION 17 18Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs, 19etc.) the FMan node will have child nodes for each of them. 20 21PROPERTIES 22 23- compatible 24 Usage: required 25 Value type: <stringlist> 26 Definition: Must include "fsl,fman" 27 FMan version can be determined via FM_IP_REV_1 register in the 28 FMan block. The offset is 0xc4 from the beginning of the 29 Frame Processing Manager memory map (0xc3000 from the 30 beginning of the FMan node). 31 32- cell-index 33 Usage: required 34 Value type: <u32> 35 Definition: Specifies the index of the FMan unit. 36 37 The cell-index value may be used by the SoC, to identify the 38 FMan unit in the SoC memory map. In the table bellow, 39 there's a description of the cell-index use in each SoC: 40 41 - P1023: 42 register[bit] FMan unit cell-index 43 ============================================================ 44 DEVDISR[1] 1 0 45 46 - P2041, P3041, P4080 P5020, P5040: 47 register[bit] FMan unit cell-index 48 ============================================================ 49 DCFG_DEVDISR2[6] 1 0 50 DCFG_DEVDISR2[14] 2 1 51 (Second FM available only in P4080 and P5040) 52 53 - B4860, T1040, T2080, T4240: 54 register[bit] FMan unit cell-index 55 ============================================================ 56 DCFG_CCSR_DEVDISR2[24] 1 0 57 DCFG_CCSR_DEVDISR2[25] 2 1 58 (Second FM available only in T4240) 59 60 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in 61 the specific SoC "Device Configuration/Pin Control" Memory 62 Map. 63 64- reg 65 Usage: required 66 Value type: <prop-encoded-array> 67 Definition: A standard property. Specifies the offset of the 68 following configuration registers: 69 - BMI configuration registers. 70 - QMI configuration registers. 71 - DMA configuration registers. 72 - FPM configuration registers. 73 - FMan controller configuration registers. 74 75- ranges 76 Usage: required 77 Value type: <prop-encoded-array> 78 Definition: A standard property. 79 80- clocks 81 Usage: required 82 Value type: <prop-encoded-array> 83 Definition: phandle for the fman input clock. 84 85- clock-names 86 usage: required 87 Value type: <stringlist> 88 Definition: "fmanclk" for the fman input clock. 89 90- interrupts 91 Usage: required 92 Value type: <prop-encoded-array> 93 Definition: A pair of IRQs are specified in this property. 94 The first element is associated with the event interrupts and 95 the second element is associated with the error interrupts. 96 97- fsl,qman-channel-range 98 Usage: required 99 Value type: <prop-encoded-array> 100 Definition: Specifies the range of the available dedicated 101 channels in the FMan. The first cell specifies the beginning 102 of the range and the second cell specifies the number of 103 channels. 104 Further information available at: 105 "Work Queue (WQ) Channel Assignments in the QMan" section 106 in DPAA Reference Manual. 107 108- fsl,qman 109- fsl,bman 110 Usage: required 111 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt 112 113- fsl,erratum-a050385 114 Usage: optional 115 Value type: boolean 116 Definition: A boolean property. Indicates the presence of the 117 erratum A050385 which indicates that DMA transactions that are 118 split can result in a FMan lock. 119 120============================================================================= 121FMan MURAM Node 122 123DESCRIPTION 124 125FMan Internal memory - shared between all the FMan modules. 126It contains data structures that are common and written to or read by 127the modules. 128FMan internal memory is split into the following parts: 129 Packet buffering (Tx/Rx FIFOs) 130 Frames internal context 131 132PROPERTIES 133 134- compatible 135 Usage: required 136 Value type: <stringlist> 137 Definition: Must include "fsl,fman-muram" 138 139- ranges 140 Usage: required 141 Value type: <prop-encoded-array> 142 Definition: A standard property. 143 Specifies the multi-user memory offset and the size within 144 the FMan. 145 146EXAMPLE 147 148muram@0 { 149 compatible = "fsl,fman-muram"; 150 ranges = <0 0x000000 0x28000>; 151}; 152 153============================================================================= 154FMan Port Node 155 156DESCRIPTION 157 158The Frame Manager (FMan) supports several types of hardware ports: 159 Ethernet receiver (RX) 160 Ethernet transmitter (TX) 161 Offline/Host command (O/H) 162 163PROPERTIES 164 165- compatible 166 Usage: required 167 Value type: <stringlist> 168 Definition: A standard property. 169 Must include one of the following: 170 - "fsl,fman-v2-port-oh" for FManV2 OH ports 171 - "fsl,fman-v2-port-rx" for FManV2 RX ports 172 - "fsl,fman-v2-port-tx" for FManV2 TX ports 173 - "fsl,fman-v3-port-oh" for FManV3 OH ports 174 - "fsl,fman-v3-port-rx" for FManV3 RX ports 175 - "fsl,fman-v3-port-tx" for FManV3 TX ports 176 177- cell-index 178 Usage: required 179 Value type: <u32> 180 Definition: Specifies the hardware port id. 181 Each hardware port on the FMan has its own hardware PortID. 182 Super set of all hardware Port IDs available at FMan Reference 183 Manual under "FMan Hardware Ports in Freescale Devices" table. 184 185 Each hardware port is assigned a 4KB, port-specific page in 186 the FMan hardware port memory region (which is part of the 187 FMan memory map). The first 4 KB in the FMan hardware ports 188 memory region is used for what are called common registers. 189 The subsequent 63 4KB pages are allocated to the hardware 190 ports. 191 The page of a specific port is determined by the cell-index. 192 193- reg 194 Usage: required 195 Value type: <prop-encoded-array> 196 Definition: There is one reg region describing the port 197 configuration registers. 198 199- fsl,fman-10g-port 200 Usage: optional 201 Value type: boolean 202 Definition: The default port rate is 1G. 203 If this property exists, the port is s 10G port. 204 205- fsl,fman-best-effort-port 206 Usage: optional 207 Value type: boolean 208 Definition: Can be defined only if 10G-support is set. 209 This property marks a best-effort 10G port (10G port that 210 may not be capable of line rate). 211 212EXAMPLE 213 214port@a8000 { 215 cell-index = <0x28>; 216 compatible = "fsl,fman-v2-port-tx"; 217 reg = <0xa8000 0x1000>; 218}; 219 220port@88000 { 221 cell-index = <0x8>; 222 compatible = "fsl,fman-v2-port-rx"; 223 reg = <0x88000 0x1000>; 224}; 225 226port@81000 { 227 cell-index = <0x1>; 228 compatible = "fsl,fman-v2-port-oh"; 229 reg = <0x81000 0x1000>; 230}; 231 232============================================================================= 233FMan dTSEC/XGEC/mEMAC Node 234 235DESCRIPTION 236 237mEMAC/dTSEC/XGEC are the Ethernet network interfaces 238 239PROPERTIES 240 241- compatible 242 Usage: required 243 Value type: <stringlist> 244 Definition: A standard property. 245 Must include one of the following: 246 - "fsl,fman-dtsec" for dTSEC MAC 247 - "fsl,fman-xgec" for XGEC MAC 248 - "fsl,fman-memac for mEMAC MAC 249 250- cell-index 251 Usage: required 252 Value type: <u32> 253 Definition: Specifies the MAC id. 254 255 The cell-index value may be used by the FMan or the SoC, to 256 identify the MAC unit in the FMan (or SoC) memory map. 257 In the tables bellow there's a description of the cell-index 258 use, there are two tables, one describes the use of cell-index 259 by the FMan, the second describes the use by the SoC: 260 261 1. FMan Registers 262 263 FManV2: 264 register[bit] MAC cell-index 265 ============================================================ 266 FM_EPI[16] XGEC 8 267 FM_EPI[16+n] dTSECn n-1 268 FM_NPI[11+n] dTSECn n-1 269 n = 1,..,5 270 271 FManV3: 272 register[bit] MAC cell-index 273 ============================================================ 274 FM_EPI[16+n] mEMACn n-1 275 FM_EPI[25] mEMAC10 9 276 277 FM_NPI[11+n] mEMACn n-1 278 FM_NPI[10] mEMAC10 9 279 FM_NPI[11] mEMAC9 8 280 n = 1,..8 281 282 FM_EPI and FM_NPI are located in the FMan memory map. 283 284 2. SoC registers: 285 286 - P2041, P3041, P4080 P5020, P5040: 287 register[bit] FMan MAC cell 288 Unit index 289 ============================================================ 290 DCFG_DEVDISR2[7] 1 XGEC 8 291 DCFG_DEVDISR2[7+n] 1 dTSECn n-1 292 DCFG_DEVDISR2[15] 2 XGEC 8 293 DCFG_DEVDISR2[15+n] 2 dTSECn n-1 294 n = 1,..5 295 296 - T1040, T2080, T4240, B4860: 297 register[bit] FMan MAC cell 298 Unit index 299 ============================================================ 300 DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 301 DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 302 n = 1,..6,9,10 303 304 EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in 305 the specific SoC "Device Configuration/Pin Control" Memory 306 Map. 307 308- reg 309 Usage: required 310 Value type: <prop-encoded-array> 311 Definition: A standard property. 312 313- fsl,fman-ports 314 Usage: required 315 Value type: <prop-encoded-array> 316 Definition: An array of two phandles - the first references is 317 the FMan RX port and the second is the TX port used by this 318 MAC. 319 320- ptp-timer 321 Usage required 322 Value type: <phandle> 323 Definition: A phandle for 1EEE1588 timer. 324 325EXAMPLE 326 327fman1_tx28: port@a8000 { 328 cell-index = <0x28>; 329 compatible = "fsl,fman-v2-port-tx"; 330 reg = <0xa8000 0x1000>; 331}; 332 333fman1_rx8: port@88000 { 334 cell-index = <0x8>; 335 compatible = "fsl,fman-v2-port-rx"; 336 reg = <0x88000 0x1000>; 337}; 338 339ptp-timer: ptp_timer@fe000 { 340 compatible = "fsl,fman-ptp-timer"; 341 reg = <0xfe000 0x1000>; 342}; 343 344ethernet@e0000 { 345 compatible = "fsl,fman-dtsec"; 346 cell-index = <0>; 347 reg = <0xe0000 0x1000>; 348 fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; 349 ptp-timer = <&ptp-timer>; 350}; 351 352============================================================================ 353FMan IEEE 1588 Node 354 355DESCRIPTION 356 357The FMan interface to support IEEE 1588 358 359 360PROPERTIES 361 362- compatible 363 Usage: required 364 Value type: <stringlist> 365 Definition: A standard property. 366 Must include "fsl,fman-ptp-timer". 367 368- reg 369 Usage: required 370 Value type: <prop-encoded-array> 371 Definition: A standard property. 372 373EXAMPLE 374 375ptp-timer@fe000 { 376 compatible = "fsl,fman-ptp-timer"; 377 reg = <0xfe000 0x1000>; 378}; 379 380============================================================================= 381FMan MDIO Node 382 383DESCRIPTION 384 385The MDIO is a bus to which the PHY devices are connected. 386 387PROPERTIES 388 389- compatible 390 Usage: required 391 Value type: <stringlist> 392 Definition: A standard property. 393 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2. 394 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2. 395 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from 396 FMan v3. 397 398- reg 399 Usage: required 400 Value type: <prop-encoded-array> 401 Definition: A standard property. 402 403- bus-frequency 404 Usage: optional 405 Value type: <u32> 406 Definition: Specifies the external MDIO bus clock speed to 407 be used, if different from the standard 2.5 MHz. 408 This may be due to the standard speed being unsupported (e.g. 409 due to a hardware problem), or to advertise that all relevant 410 components in the system support a faster speed. 411 412- interrupts 413 Usage: required for external MDIO 414 Value type: <prop-encoded-array> 415 Definition: Event interrupt of external MDIO controller. 416 417- fsl,fman-internal-mdio 418 Usage: required for internal MDIO 419 Value type: boolean 420 Definition: Fman has internal MDIO for internal PCS(Physical 421 Coding Sublayer) PHYs and external MDIO for external PHYs. 422 The settings and programming routines for internal/external 423 MDIO are different. Must be included for internal MDIO. 424 425EXAMPLE 426 427Example for FMan v2 external MDIO: 428 429mdio@f1000 { 430 compatible = "fsl,fman-xmdio"; 431 reg = <0xf1000 0x1000>; 432 interrupts = <101 2 0 0>; 433}; 434 435Example for FMan v3 internal MDIO: 436 437mdio@f1000 { 438 compatible = "fsl,fman-memac-mdio"; 439 reg = <0xf1000 0x1000>; 440 fsl,fman-internal-mdio; 441}; 442 443============================================================================= 444Example 445 446fman@400000 { 447 #address-cells = <1>; 448 #size-cells = <1>; 449 cell-index = <1>; 450 compatible = "fsl,fman" 451 ranges = <0 0x400000 0x100000>; 452 reg = <0x400000 0x100000>; 453 clocks = <&fman_clk>; 454 clock-names = "fmanclk"; 455 interrupts = < 456 96 2 0 0 457 16 2 1 1>; 458 fsl,qman-channel-range = <0x40 0xc>; 459 460 muram@0 { 461 compatible = "fsl,fman-muram"; 462 reg = <0x0 0x28000>; 463 }; 464 465 port@81000 { 466 cell-index = <1>; 467 compatible = "fsl,fman-v2-port-oh"; 468 reg = <0x81000 0x1000>; 469 }; 470 471 port@82000 { 472 cell-index = <2>; 473 compatible = "fsl,fman-v2-port-oh"; 474 reg = <0x82000 0x1000>; 475 }; 476 477 port@83000 { 478 cell-index = <3>; 479 compatible = "fsl,fman-v2-port-oh"; 480 reg = <0x83000 0x1000>; 481 }; 482 483 port@84000 { 484 cell-index = <4>; 485 compatible = "fsl,fman-v2-port-oh"; 486 reg = <0x84000 0x1000>; 487 }; 488 489 port@85000 { 490 cell-index = <5>; 491 compatible = "fsl,fman-v2-port-oh"; 492 reg = <0x85000 0x1000>; 493 }; 494 495 port@86000 { 496 cell-index = <6>; 497 compatible = "fsl,fman-v2-port-oh"; 498 reg = <0x86000 0x1000>; 499 }; 500 501 fman1_rx_0x8: port@88000 { 502 cell-index = <0x8>; 503 compatible = "fsl,fman-v2-port-rx"; 504 reg = <0x88000 0x1000>; 505 }; 506 507 fman1_rx_0x9: port@89000 { 508 cell-index = <0x9>; 509 compatible = "fsl,fman-v2-port-rx"; 510 reg = <0x89000 0x1000>; 511 }; 512 513 fman1_rx_0xa: port@8a000 { 514 cell-index = <0xa>; 515 compatible = "fsl,fman-v2-port-rx"; 516 reg = <0x8a000 0x1000>; 517 }; 518 519 fman1_rx_0xb: port@8b000 { 520 cell-index = <0xb>; 521 compatible = "fsl,fman-v2-port-rx"; 522 reg = <0x8b000 0x1000>; 523 }; 524 525 fman1_rx_0xc: port@8c000 { 526 cell-index = <0xc>; 527 compatible = "fsl,fman-v2-port-rx"; 528 reg = <0x8c000 0x1000>; 529 }; 530 531 fman1_rx_0x10: port@90000 { 532 cell-index = <0x10>; 533 compatible = "fsl,fman-v2-port-rx"; 534 reg = <0x90000 0x1000>; 535 }; 536 537 fman1_tx_0x28: port@a8000 { 538 cell-index = <0x28>; 539 compatible = "fsl,fman-v2-port-tx"; 540 reg = <0xa8000 0x1000>; 541 }; 542 543 fman1_tx_0x29: port@a9000 { 544 cell-index = <0x29>; 545 compatible = "fsl,fman-v2-port-tx"; 546 reg = <0xa9000 0x1000>; 547 }; 548 549 fman1_tx_0x2a: port@aa000 { 550 cell-index = <0x2a>; 551 compatible = "fsl,fman-v2-port-tx"; 552 reg = <0xaa000 0x1000>; 553 }; 554 555 fman1_tx_0x2b: port@ab000 { 556 cell-index = <0x2b>; 557 compatible = "fsl,fman-v2-port-tx"; 558 reg = <0xab000 0x1000>; 559 }; 560 561 fman1_tx_0x2c: port@ac0000 { 562 cell-index = <0x2c>; 563 compatible = "fsl,fman-v2-port-tx"; 564 reg = <0xac000 0x1000>; 565 }; 566 567 fman1_tx_0x30: port@b0000 { 568 cell-index = <0x30>; 569 compatible = "fsl,fman-v2-port-tx"; 570 reg = <0xb0000 0x1000>; 571 }; 572 573 ethernet@e0000 { 574 compatible = "fsl,fman-dtsec"; 575 cell-index = <0>; 576 reg = <0xe0000 0x1000>; 577 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>; 578 }; 579 580 ethernet@e2000 { 581 compatible = "fsl,fman-dtsec"; 582 cell-index = <1>; 583 reg = <0xe2000 0x1000>; 584 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>; 585 }; 586 587 ethernet@e4000 { 588 compatible = "fsl,fman-dtsec"; 589 cell-index = <2>; 590 reg = <0xe4000 0x1000>; 591 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>; 592 }; 593 594 ethernet@e6000 { 595 compatible = "fsl,fman-dtsec"; 596 cell-index = <3>; 597 reg = <0xe6000 0x1000>; 598 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>; 599 }; 600 601 ethernet@e8000 { 602 compatible = "fsl,fman-dtsec"; 603 cell-index = <4>; 604 reg = <0xf0000 0x1000>; 605 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>; 606 607 ethernet@f0000 { 608 cell-index = <8>; 609 compatible = "fsl,fman-xgec"; 610 reg = <0xf0000 0x1000>; 611 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; 612 }; 613 614 ptp-timer@fe000 { 615 compatible = "fsl,fman-ptp-timer"; 616 reg = <0xfe000 0x1000>; 617 }; 618 619 mdio@f1000 { 620 compatible = "fsl,fman-xmdio"; 621 reg = <0xf1000 0x1000>; 622 interrupts = <101 2 0 0>; 623 }; 624}; 625