1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* AM437x GP EVM */ 10 11/dts-v1/; 12 13#include "am4372.dtsi" 14#include <dt-bindings/pinctrl/am43xx.h> 15#include <dt-bindings/pwm/pwm.h> 16#include <dt-bindings/gpio/gpio.h> 17 18/ { 19 model = "TI AM437x GP EVM"; 20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; 21 22 aliases { 23 display0 = &lcd0; 24 }; 25 26 evm_v3_3d: fixedregulator-v3_3d { 27 compatible = "regulator-fixed"; 28 regulator-name = "evm_v3_3d"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 enable-active-high; 32 }; 33 34 vtt_fixed: fixedregulator-vtt { 35 compatible = "regulator-fixed"; 36 regulator-name = "vtt_fixed"; 37 regulator-min-microvolt = <1500000>; 38 regulator-max-microvolt = <1500000>; 39 regulator-always-on; 40 regulator-boot-on; 41 enable-active-high; 42 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; 43 }; 44 45 vmmcwl_fixed: fixedregulator-mmcwl { 46 compatible = "regulator-fixed"; 47 regulator-name = "vmmcwl_fixed"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; 51 enable-active-high; 52 }; 53 54 backlight { 55 compatible = "pwm-backlight"; 56 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 57 brightness-levels = <0 51 53 56 62 75 101 152 255>; 58 default-brightness-level = <8>; 59 }; 60 61 matrix_keypad: matrix_keypad@0 { 62 compatible = "gpio-matrix-keypad"; 63 debounce-delay-ms = <5>; 64 col-scan-delay-us = <2>; 65 66 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */ 67 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ 68 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ 69 70 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ 71 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ 72 73 linux,keymap = <0x00000201 /* P1 */ 74 0x00010202 /* P2 */ 75 0x01000067 /* UP */ 76 0x0101006a /* RIGHT */ 77 0x02000069 /* LEFT */ 78 0x0201006c>; /* DOWN */ 79 }; 80 81 lcd0: display { 82 compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; 83 label = "lcd"; 84 85 panel-timing { 86 clock-frequency = <33000000>; 87 hactive = <800>; 88 vactive = <480>; 89 hfront-porch = <210>; 90 hback-porch = <16>; 91 hsync-len = <30>; 92 vback-porch = <10>; 93 vfront-porch = <22>; 94 vsync-len = <13>; 95 hsync-active = <0>; 96 vsync-active = <0>; 97 de-active = <1>; 98 pixelclk-active = <1>; 99 }; 100 101 port { 102 lcd_in: endpoint { 103 remote-endpoint = <&dpi_out>; 104 }; 105 }; 106 }; 107 108 /* fixed 12MHz oscillator */ 109 refclk: oscillator { 110 #clock-cells = <0>; 111 compatible = "fixed-clock"; 112 clock-frequency = <12000000>; 113 }; 114 115 /* fixed 32k external oscillator clock */ 116 clk_32k_rtc: clk_32k_rtc { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 clock-frequency = <32768>; 120 }; 121 122 sound0: sound@0 { 123 compatible = "simple-audio-card"; 124 simple-audio-card,name = "AM437x-GP-EVM"; 125 simple-audio-card,widgets = 126 "Headphone", "Headphone Jack", 127 "Line", "Line In"; 128 simple-audio-card,routing = 129 "Headphone Jack", "HPLOUT", 130 "Headphone Jack", "HPROUT", 131 "LINE1L", "Line In", 132 "LINE1R", "Line In"; 133 simple-audio-card,format = "dsp_b"; 134 simple-audio-card,bitclock-master = <&sound0_master>; 135 simple-audio-card,frame-master = <&sound0_master>; 136 simple-audio-card,bitclock-inversion; 137 138 simple-audio-card,cpu { 139 sound-dai = <&mcasp1>; 140 system-clock-frequency = <12000000>; 141 }; 142 143 sound0_master: simple-audio-card,codec { 144 sound-dai = <&tlv320aic3106>; 145 system-clock-frequency = <12000000>; 146 }; 147 }; 148}; 149 150&am43xx_pinmux { 151 pinctrl-names = "default", "sleep"; 152 pinctrl-0 = <&wlan_pins_default>; 153 pinctrl-1 = <&wlan_pins_sleep>; 154 155 i2c0_pins: i2c0_pins { 156 pinctrl-single,pins = < 157 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 158 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 159 >; 160 }; 161 162 i2c1_pins: i2c1_pins { 163 pinctrl-single,pins = < 164 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 165 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ 166 >; 167 }; 168 169 mmc1_pins: pinmux_mmc1_pins { 170 pinctrl-single,pins = < 171 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 172 >; 173 }; 174 175 ecap0_pins: backlight_pins { 176 pinctrl-single,pins = < 177 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 178 >; 179 }; 180 181 pixcir_ts_pins: pixcir_ts_pins { 182 pinctrl-single,pins = < 183 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ 184 >; 185 }; 186 187 cpsw_default: cpsw_default { 188 pinctrl-single,pins = < 189 /* Slave 1 */ 190 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ 191 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ 192 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ 193 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ 194 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ 195 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ 196 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ 197 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ 198 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ 199 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ 200 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ 201 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ 202 >; 203 }; 204 205 cpsw_sleep: cpsw_sleep { 206 pinctrl-single,pins = < 207 /* Slave 1 reset value */ 208 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 209 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 210 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 211 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 212 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 213 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 214 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 215 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 216 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 217 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 218 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 219 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 220 >; 221 }; 222 223 davinci_mdio_default: davinci_mdio_default { 224 pinctrl-single,pins = < 225 /* MDIO */ 226 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 227 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 228 >; 229 }; 230 231 davinci_mdio_sleep: davinci_mdio_sleep { 232 pinctrl-single,pins = < 233 /* MDIO reset value */ 234 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 235 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 236 >; 237 }; 238 239 nand_flash_x8: nand_flash_x8 { 240 pinctrl-single,pins = < 241 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 242 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 243 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 244 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 245 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 246 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 247 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 248 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 249 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 250 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 251 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 252 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 253 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 254 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 255 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 256 >; 257 }; 258 259 dss_pins: dss_pins { 260 pinctrl-single,pins = < 261 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 262 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) 263 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) 264 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1) 265 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) 266 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) 267 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) 268 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 269 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 270 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 271 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 272 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0) 273 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 274 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 275 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 276 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0) 277 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 278 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 279 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 280 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0) 281 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 282 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 283 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 284 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 285 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 286 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 287 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 288 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 289 290 >; 291 }; 292 293 display_mux_pins: display_mux_pins { 294 pinctrl-single,pins = < 295 /* GPIO 5_8 to select LCD / HDMI */ 296 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) 297 >; 298 }; 299 300 dcan0_default: dcan0_default_pins { 301 pinctrl-single,pins = < 302 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ 303 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ 304 >; 305 }; 306 307 dcan0_sleep: dcan0_sleep_pins { 308 pinctrl-single,pins = < 309 0x178 (PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ 310 0x17c (PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ 311 >; 312 }; 313 314 dcan1_default: dcan1_default_pins { 315 pinctrl-single,pins = < 316 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ 317 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ 318 >; 319 }; 320 321 dcan1_sleep: dcan1_sleep_pins { 322 pinctrl-single,pins = < 323 0x180 (PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ 324 0x184 (PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ 325 >; 326 }; 327 328 vpfe0_pins_default: vpfe0_pins_default { 329 pinctrl-single,pins = < 330 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ 331 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ 332 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ 333 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ 334 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ 335 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ 336 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ 337 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ 338 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ 339 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ 340 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ 341 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ 342 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ 343 >; 344 }; 345 346 vpfe0_pins_sleep: vpfe0_pins_sleep { 347 pinctrl-single,pins = < 348 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ 349 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ 350 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ 351 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ 352 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ 353 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ 354 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ 355 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ 356 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ 357 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ 358 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ 359 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ 360 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ 361 >; 362 }; 363 364 vpfe1_pins_default: vpfe1_pins_default { 365 pinctrl-single,pins = < 366 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ 367 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ 368 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ 369 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ 370 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ 371 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ 372 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ 373 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ 374 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ 375 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ 376 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ 377 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ 378 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ 379 >; 380 }; 381 382 vpfe1_pins_sleep: vpfe1_pins_sleep { 383 pinctrl-single,pins = < 384 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ 385 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ 386 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ 387 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ 388 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ 389 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ 390 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ 391 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ 392 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ 393 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ 394 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ 395 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ 396 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ 397 >; 398 }; 399 400 mmc3_pins_default: pinmux_mmc3_pins_default { 401 pinctrl-single,pins = < 402 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ 403 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ 404 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ 405 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ 406 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ 407 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ 408 >; 409 }; 410 411 mmc3_pins_sleep: pinmux_mmc3_pins_sleep { 412 pinctrl-single,pins = < 413 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ 414 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ 415 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ 416 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ 417 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ 418 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ 419 >; 420 }; 421 422 wlan_pins_default: pinmux_wlan_pins_default { 423 pinctrl-single,pins = < 424 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ 425 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ 426 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ 427 >; 428 }; 429 430 wlan_pins_sleep: pinmux_wlan_pins_sleep { 431 pinctrl-single,pins = < 432 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ 433 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ 434 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ 435 >; 436 }; 437 438 uart3_pins: uart3_pins { 439 pinctrl-single,pins = < 440 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ 441 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ 442 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ 443 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ 444 >; 445 }; 446 447 mcasp1_pins: mcasp1_pins { 448 pinctrl-single,pins = < 449 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 450 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 451 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 452 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 453 >; 454 }; 455 456 mcasp1_sleep_pins: mcasp1_sleep_pins { 457 pinctrl-single,pins = < 458 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) 459 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) 460 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) 461 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) 462 >; 463 }; 464 465 gpio0_pins: gpio0_pins { 466 pinctrl-single,pins = < 467 0x26c (PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ 468 >; 469 }; 470 471 emmc_pins_default: emmc_pins_default { 472 pinctrl-single,pins = < 473 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 474 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 475 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 476 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 477 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 478 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 479 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 480 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 481 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 482 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 483 >; 484 }; 485 486 emmc_pins_sleep: emmc_pins_sleep { 487 pinctrl-single,pins = < 488 0x00 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ 489 0x04 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ 490 0x08 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ 491 0x0c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ 492 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ 493 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ 494 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ 495 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ 496 0x80 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ 497 0x84 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ 498 >; 499 }; 500}; 501 502&i2c0 { 503 status = "okay"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&i2c0_pins>; 506 clock-frequency = <100000>; 507 508 tps65218: tps65218@24 { 509 reg = <0x24>; 510 compatible = "ti,tps65218"; 511 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 515 dcdc1: regulator-dcdc1 { 516 compatible = "ti,tps65218-dcdc1"; 517 regulator-name = "vdd_core"; 518 regulator-min-microvolt = <912000>; 519 regulator-max-microvolt = <1144000>; 520 regulator-boot-on; 521 regulator-always-on; 522 }; 523 524 dcdc2: regulator-dcdc2 { 525 compatible = "ti,tps65218-dcdc2"; 526 regulator-name = "vdd_mpu"; 527 regulator-min-microvolt = <912000>; 528 regulator-max-microvolt = <1378000>; 529 regulator-boot-on; 530 regulator-always-on; 531 }; 532 533 dcdc3: regulator-dcdc3 { 534 compatible = "ti,tps65218-dcdc3"; 535 regulator-name = "vdcdc3"; 536 regulator-min-microvolt = <1500000>; 537 regulator-max-microvolt = <1500000>; 538 regulator-boot-on; 539 regulator-always-on; 540 }; 541 dcdc5: regulator-dcdc5 { 542 compatible = "ti,tps65218-dcdc5"; 543 regulator-name = "v1_0bat"; 544 regulator-min-microvolt = <1000000>; 545 regulator-max-microvolt = <1000000>; 546 regulator-boot-on; 547 regulator-always-on; 548 }; 549 550 dcdc6: regulator-dcdc6 { 551 compatible = "ti,tps65218-dcdc6"; 552 regulator-name = "v1_8bat"; 553 regulator-min-microvolt = <1800000>; 554 regulator-max-microvolt = <1800000>; 555 regulator-boot-on; 556 regulator-always-on; 557 }; 558 559 ldo1: regulator-ldo1 { 560 compatible = "ti,tps65218-ldo1"; 561 regulator-min-microvolt = <1800000>; 562 regulator-max-microvolt = <1800000>; 563 regulator-boot-on; 564 regulator-always-on; 565 }; 566 }; 567 568 ov2659@30 { 569 compatible = "ovti,ov2659"; 570 reg = <0x30>; 571 572 clocks = <&refclk 0>; 573 clock-names = "xvclk"; 574 575 port { 576 ov2659_0: endpoint { 577 remote-endpoint = <&vpfe1_ep>; 578 link-frequencies = /bits/ 64 <70000000>; 579 }; 580 }; 581 }; 582}; 583 584&i2c1 { 585 status = "okay"; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&i2c1_pins>; 588 pixcir_ts@5c { 589 compatible = "pixcir,pixcir_tangoc"; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&pixcir_ts_pins>; 592 reg = <0x5c>; 593 interrupt-parent = <&gpio3>; 594 interrupts = <22 0>; 595 596 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 597 598 /* 599 * 0x264 represents the offset of padconf register of 600 * gpio3_22 from am43xx_pinmux base. 601 */ 602 interrupts-extended = <&gpio3 22 IRQ_TYPE_NONE>, 603 <&am43xx_pinmux 0x264>; 604 interrupt-names = "tsc", "wakeup"; 605 606 touchscreen-size-x = <1024>; 607 touchscreen-size-y = <600>; 608 wakeup-source; 609 }; 610 611 ov2659@30 { 612 compatible = "ovti,ov2659"; 613 reg = <0x30>; 614 615 clocks = <&refclk 0>; 616 clock-names = "xvclk"; 617 618 port { 619 ov2659_1: endpoint { 620 remote-endpoint = <&vpfe0_ep>; 621 link-frequencies = /bits/ 64 <70000000>; 622 }; 623 }; 624 }; 625 626 tlv320aic3106: tlv320aic3106@1b { 627 #sound-dai-cells = <0>; 628 compatible = "ti,tlv320aic3106"; 629 reg = <0x1b>; 630 status = "okay"; 631 632 /* Regulators */ 633 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */ 634 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ 635 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ 636 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ 637 }; 638}; 639 640&epwmss0 { 641 status = "okay"; 642}; 643 644&tscadc { 645 status = "okay"; 646 647 adc { 648 ti,adc-channels = <0 1 2 3 4 5 6 7>; 649 }; 650}; 651 652&ecap0 { 653 status = "okay"; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&ecap0_pins>; 656}; 657 658&gpio0 { 659 pinctrl-names = "default"; 660 pinctrl-0 = <&gpio0_pins>; 661 status = "okay"; 662 663 p23 { 664 gpio-hog; 665 gpios = <23 GPIO_ACTIVE_HIGH>; 666 /* SelEMMCorNAND selects between eMMC and NAND: 667 * Low: NAND 668 * High: eMMC 669 * When changing this line make sure the newly 670 * selected device node is enabled and the previously 671 * selected device node is disabled. 672 */ 673 output-low; 674 line-name = "SelEMMCorNAND"; 675 }; 676}; 677 678&gpio1 { 679 status = "okay"; 680}; 681 682&gpio3 { 683 status = "okay"; 684}; 685 686&gpio4 { 687 status = "okay"; 688}; 689 690&gpio5 { 691 pinctrl-names = "default"; 692 pinctrl-0 = <&display_mux_pins>; 693 status = "okay"; 694 ti,no-reset-on-init; 695 696 p8 { 697 /* 698 * SelLCDorHDMI selects between display and audio paths: 699 * Low: HDMI display with audio via HDMI 700 * High: LCD display with analog audio via aic3111 codec 701 */ 702 gpio-hog; 703 gpios = <8 GPIO_ACTIVE_HIGH>; 704 output-high; 705 line-name = "SelLCDorHDMI"; 706 }; 707}; 708 709&mmc1 { 710 status = "okay"; 711 vmmc-supply = <&evm_v3_3d>; 712 bus-width = <4>; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&mmc1_pins>; 715 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 716}; 717 718/* eMMC sits on mmc2 */ 719&mmc2 { 720 /* 721 * When enabling eMMC, disable GPMC/NAND and set 722 * SelEMMCorNAND to output-high 723 */ 724 status = "disabled"; 725 vmmc-supply = <&evm_v3_3d>; 726 bus-width = <8>; 727 pinctrl-names = "default", "sleep"; 728 pinctrl-0 = <&emmc_pins_default>; 729 pinctrl-1 = <&emmc_pins_sleep>; 730 ti,non-removable; 731}; 732 733&mmc3 { 734 status = "okay"; 735 /* these are on the crossbar and are outlined in the 736 xbar-event-map element */ 737 dmas = <&edma 30 738 &edma 31>; 739 dma-names = "tx", "rx"; 740 vmmc-supply = <&vmmcwl_fixed>; 741 bus-width = <4>; 742 pinctrl-names = "default", "sleep"; 743 pinctrl-0 = <&mmc3_pins_default>; 744 pinctrl-1 = <&mmc3_pins_sleep>; 745 cap-power-off-card; 746 keep-power-in-suspend; 747 ti,non-removable; 748 749 #address-cells = <1>; 750 #size-cells = <0>; 751 wlcore: wlcore@0 { 752 compatible = "ti,wl1835"; 753 reg = <2>; 754 interrupt-parent = <&gpio1>; 755 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 756 }; 757}; 758 759&edma { 760 ti,edma-xbar-event-map = /bits/ 16 <1 30 761 2 31>; 762}; 763 764&uart3 { 765 status = "okay"; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&uart3_pins>; 768}; 769 770&usb2_phy1 { 771 status = "okay"; 772}; 773 774&usb1 { 775 dr_mode = "peripheral"; 776 status = "okay"; 777}; 778 779&usb2_phy2 { 780 status = "okay"; 781}; 782 783&usb2 { 784 dr_mode = "host"; 785 status = "okay"; 786}; 787 788&mac { 789 slaves = <1>; 790 pinctrl-names = "default", "sleep"; 791 pinctrl-0 = <&cpsw_default>; 792 pinctrl-1 = <&cpsw_sleep>; 793 status = "okay"; 794}; 795 796&davinci_mdio { 797 pinctrl-names = "default", "sleep"; 798 pinctrl-0 = <&davinci_mdio_default>; 799 pinctrl-1 = <&davinci_mdio_sleep>; 800 status = "okay"; 801}; 802 803&cpsw_emac0 { 804 phy_id = <&davinci_mdio>, <0>; 805 phy-mode = "rgmii"; 806}; 807 808&elm { 809 status = "okay"; 810}; 811 812&gpmc { 813 /* 814 * When enabling GPMC, disable eMMC and set 815 * SelEMMCorNAND to output-low 816 */ 817 status = "okay"; 818 pinctrl-names = "default"; 819 pinctrl-0 = <&nand_flash_x8>; 820 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 821 nand@0,0 { 822 reg = <0 0 4>; /* device IO registers */ 823 ti,nand-ecc-opt = "bch16"; 824 ti,elm-id = <&elm>; 825 nand-bus-width = <8>; 826 gpmc,device-width = <1>; 827 gpmc,sync-clk-ps = <0>; 828 gpmc,cs-on-ns = <0>; 829 gpmc,cs-rd-off-ns = <40>; 830 gpmc,cs-wr-off-ns = <40>; 831 gpmc,adv-on-ns = <0>; 832 gpmc,adv-rd-off-ns = <25>; 833 gpmc,adv-wr-off-ns = <25>; 834 gpmc,we-on-ns = <0>; 835 gpmc,we-off-ns = <20>; 836 gpmc,oe-on-ns = <3>; 837 gpmc,oe-off-ns = <30>; 838 gpmc,access-ns = <30>; 839 gpmc,rd-cycle-ns = <40>; 840 gpmc,wr-cycle-ns = <40>; 841 gpmc,wait-pin = <0>; 842 gpmc,bus-turnaround-ns = <0>; 843 gpmc,cycle2cycle-delay-ns = <0>; 844 gpmc,clk-activation-ns = <0>; 845 gpmc,wait-monitoring-ns = <0>; 846 gpmc,wr-access-ns = <40>; 847 gpmc,wr-data-mux-bus-ns = <0>; 848 /* MTD partition table */ 849 /* All SPL-* partitions are sized to minimal length 850 * which can be independently programmable. For 851 * NAND flash this is equal to size of erase-block */ 852 #address-cells = <1>; 853 #size-cells = <1>; 854 partition@0 { 855 label = "NAND.SPL"; 856 reg = <0x00000000 0x00040000>; 857 }; 858 partition@1 { 859 label = "NAND.SPL.backup1"; 860 reg = <0x00040000 0x00040000>; 861 }; 862 partition@2 { 863 label = "NAND.SPL.backup2"; 864 reg = <0x00080000 0x00040000>; 865 }; 866 partition@3 { 867 label = "NAND.SPL.backup3"; 868 reg = <0x000c0000 0x00040000>; 869 }; 870 partition@4 { 871 label = "NAND.u-boot-spl-os"; 872 reg = <0x00100000 0x00080000>; 873 }; 874 partition@5 { 875 label = "NAND.u-boot"; 876 reg = <0x00180000 0x00100000>; 877 }; 878 partition@6 { 879 label = "NAND.u-boot-env"; 880 reg = <0x00280000 0x00040000>; 881 }; 882 partition@7 { 883 label = "NAND.u-boot-env.backup1"; 884 reg = <0x002c0000 0x00040000>; 885 }; 886 partition@8 { 887 label = "NAND.kernel"; 888 reg = <0x00300000 0x00700000>; 889 }; 890 partition@9 { 891 label = "NAND.file-system"; 892 reg = <0x00a00000 0x1f600000>; 893 }; 894 }; 895}; 896 897&dss { 898 status = "ok"; 899 900 pinctrl-names = "default"; 901 pinctrl-0 = <&dss_pins>; 902 903 port { 904 dpi_out: endpoint@0 { 905 remote-endpoint = <&lcd_in>; 906 data-lines = <24>; 907 }; 908 }; 909}; 910 911&dcan0 { 912 pinctrl-names = "default", "sleep"; 913 pinctrl-0 = <&dcan0_default>; 914 pinctrl-1 = <&dcan0_sleep>; 915 status = "okay"; 916}; 917 918&dcan1 { 919 pinctrl-names = "default", "sleep"; 920 pinctrl-0 = <&dcan1_default>; 921 pinctrl-1 = <&dcan1_sleep>; 922 status = "okay"; 923}; 924 925&vpfe0 { 926 status = "okay"; 927 pinctrl-names = "default", "sleep"; 928 pinctrl-0 = <&vpfe0_pins_default>; 929 pinctrl-1 = <&vpfe0_pins_sleep>; 930 931 port { 932 vpfe0_ep: endpoint { 933 remote-endpoint = <&ov2659_1>; 934 ti,am437x-vpfe-interface = <0>; 935 bus-width = <8>; 936 hsync-active = <0>; 937 vsync-active = <0>; 938 }; 939 }; 940}; 941 942&vpfe1 { 943 status = "okay"; 944 pinctrl-names = "default", "sleep"; 945 pinctrl-0 = <&vpfe1_pins_default>; 946 pinctrl-1 = <&vpfe1_pins_sleep>; 947 948 port { 949 vpfe1_ep: endpoint { 950 remote-endpoint = <&ov2659_0>; 951 ti,am437x-vpfe-interface = <0>; 952 bus-width = <8>; 953 hsync-active = <0>; 954 vsync-active = <0>; 955 }; 956 }; 957}; 958 959&mcasp1 { 960 #sound-dai-cells = <0>; 961 pinctrl-names = "default", "sleep"; 962 pinctrl-0 = <&mcasp1_pins>; 963 pinctrl-1 = <&mcasp1_sleep_pins>; 964 965 status = "okay"; 966 967 op-mode = <0>; /* MCASP_IIS_MODE */ 968 tdm-slots = <2>; 969 /* 4 serializers */ 970 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 971 0 0 1 2 972 >; 973 tx-num-evt = <32>; 974 rx-num-evt = <32>; 975}; 976 977&rtc { 978 clocks = <&clk_32k_rtc>, <&clk_32768_ck>; 979 clock-names = "ext-clk", "int-clk"; 980 status = "okay"; 981}; 982