1/* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12#include <dt-bindings/gpio/gpio.h> 13#include "skeleton.dtsi" 14#include "imx28-pinfunc.h" 15 16/ { 17 interrupt-parent = <&icoll>; 18 19 aliases { 20 ethernet0 = &mac0; 21 ethernet1 = &mac1; 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 saif0 = &saif0; 28 saif1 = &saif1; 29 serial0 = &auart0; 30 serial1 = &auart1; 31 serial2 = &auart2; 32 serial3 = &auart3; 33 serial4 = &auart4; 34 spi0 = &ssp1; 35 spi1 = &ssp2; 36 usbphy0 = &usbphy0; 37 usbphy1 = &usbphy1; 38 }; 39 40 cpus { 41 #address-cells = <0>; 42 #size-cells = <0>; 43 44 cpu { 45 compatible = "arm,arm926ej-s"; 46 device_type = "cpu"; 47 }; 48 }; 49 50 apb@80000000 { 51 compatible = "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 reg = <0x80000000 0x80000>; 55 ranges; 56 57 apbh@80000000 { 58 compatible = "simple-bus"; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 reg = <0x80000000 0x3c900>; 62 ranges; 63 64 icoll: interrupt-controller@80000000 { 65 compatible = "fsl,imx28-icoll", "fsl,icoll"; 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 reg = <0x80000000 0x2000>; 69 }; 70 71 hsadc: hsadc@80002000 { 72 reg = <0x80002000 0x2000>; 73 interrupts = <13>; 74 dmas = <&dma_apbh 12>; 75 dma-names = "rx"; 76 status = "disabled"; 77 }; 78 79 dma_apbh: dma-apbh@80004000 { 80 compatible = "fsl,imx28-dma-apbh"; 81 reg = <0x80004000 0x2000>; 82 interrupts = <82 83 84 85 83 88 88 88 88 84 88 88 88 88 85 87 86 0 0>; 86 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", 87 "gpmi0", "gmpi1", "gpmi2", "gmpi3", 88 "gpmi4", "gmpi5", "gpmi6", "gmpi7", 89 "hsadc", "lcdif", "empty", "empty"; 90 #dma-cells = <1>; 91 dma-channels = <16>; 92 clocks = <&clks 25>; 93 }; 94 95 perfmon: perfmon@80006000 { 96 reg = <0x80006000 0x800>; 97 interrupts = <27>; 98 status = "disabled"; 99 }; 100 101 gpmi: gpmi-nand@8000c000 { 102 compatible = "fsl,imx28-gpmi-nand"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; 106 reg-names = "gpmi-nand", "bch"; 107 interrupts = <41>; 108 interrupt-names = "bch"; 109 clocks = <&clks 50>; 110 clock-names = "gpmi_io"; 111 dmas = <&dma_apbh 4>; 112 dma-names = "rx-tx"; 113 status = "disabled"; 114 }; 115 116 ssp0: ssp@80010000 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 reg = <0x80010000 0x2000>; 120 interrupts = <96>; 121 clocks = <&clks 46>; 122 dmas = <&dma_apbh 0>; 123 dma-names = "rx-tx"; 124 status = "disabled"; 125 }; 126 127 ssp1: ssp@80012000 { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 reg = <0x80012000 0x2000>; 131 interrupts = <97>; 132 clocks = <&clks 47>; 133 dmas = <&dma_apbh 1>; 134 dma-names = "rx-tx"; 135 status = "disabled"; 136 }; 137 138 ssp2: ssp@80014000 { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 reg = <0x80014000 0x2000>; 142 interrupts = <98>; 143 clocks = <&clks 48>; 144 dmas = <&dma_apbh 2>; 145 dma-names = "rx-tx"; 146 status = "disabled"; 147 }; 148 149 ssp3: ssp@80016000 { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 reg = <0x80016000 0x2000>; 153 interrupts = <99>; 154 clocks = <&clks 49>; 155 dmas = <&dma_apbh 3>; 156 dma-names = "rx-tx"; 157 status = "disabled"; 158 }; 159 160 pinctrl: pinctrl@80018000 { 161 #address-cells = <1>; 162 #size-cells = <0>; 163 compatible = "fsl,imx28-pinctrl", "simple-bus"; 164 reg = <0x80018000 0x2000>; 165 166 gpio0: gpio@0 { 167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 168 interrupts = <127>; 169 gpio-controller; 170 #gpio-cells = <2>; 171 interrupt-controller; 172 #interrupt-cells = <2>; 173 }; 174 175 gpio1: gpio@1 { 176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 177 interrupts = <126>; 178 gpio-controller; 179 #gpio-cells = <2>; 180 interrupt-controller; 181 #interrupt-cells = <2>; 182 }; 183 184 gpio2: gpio@2 { 185 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 186 interrupts = <125>; 187 gpio-controller; 188 #gpio-cells = <2>; 189 interrupt-controller; 190 #interrupt-cells = <2>; 191 }; 192 193 gpio3: gpio@3 { 194 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 195 interrupts = <124>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 }; 201 202 gpio4: gpio@4 { 203 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; 204 interrupts = <123>; 205 gpio-controller; 206 #gpio-cells = <2>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 }; 210 211 duart_pins_a: duart@0 { 212 reg = <0>; 213 fsl,pinmux-ids = < 214 MX28_PAD_PWM0__DUART_RX 215 MX28_PAD_PWM1__DUART_TX 216 >; 217 fsl,drive-strength = <MXS_DRIVE_4mA>; 218 fsl,voltage = <MXS_VOLTAGE_HIGH>; 219 fsl,pull-up = <MXS_PULL_DISABLE>; 220 }; 221 222 duart_pins_b: duart@1 { 223 reg = <1>; 224 fsl,pinmux-ids = < 225 MX28_PAD_AUART0_CTS__DUART_RX 226 MX28_PAD_AUART0_RTS__DUART_TX 227 >; 228 fsl,drive-strength = <MXS_DRIVE_4mA>; 229 fsl,voltage = <MXS_VOLTAGE_HIGH>; 230 fsl,pull-up = <MXS_PULL_DISABLE>; 231 }; 232 233 duart_4pins_a: duart-4pins@0 { 234 reg = <0>; 235 fsl,pinmux-ids = < 236 MX28_PAD_AUART0_CTS__DUART_RX 237 MX28_PAD_AUART0_RTS__DUART_TX 238 MX28_PAD_AUART0_RX__DUART_CTS 239 MX28_PAD_AUART0_TX__DUART_RTS 240 >; 241 fsl,drive-strength = <MXS_DRIVE_4mA>; 242 fsl,voltage = <MXS_VOLTAGE_HIGH>; 243 fsl,pull-up = <MXS_PULL_DISABLE>; 244 }; 245 246 gpmi_pins_a: gpmi-nand@0 { 247 reg = <0>; 248 fsl,pinmux-ids = < 249 MX28_PAD_GPMI_D00__GPMI_D0 250 MX28_PAD_GPMI_D01__GPMI_D1 251 MX28_PAD_GPMI_D02__GPMI_D2 252 MX28_PAD_GPMI_D03__GPMI_D3 253 MX28_PAD_GPMI_D04__GPMI_D4 254 MX28_PAD_GPMI_D05__GPMI_D5 255 MX28_PAD_GPMI_D06__GPMI_D6 256 MX28_PAD_GPMI_D07__GPMI_D7 257 MX28_PAD_GPMI_CE0N__GPMI_CE0N 258 MX28_PAD_GPMI_RDY0__GPMI_READY0 259 MX28_PAD_GPMI_RDN__GPMI_RDN 260 MX28_PAD_GPMI_WRN__GPMI_WRN 261 MX28_PAD_GPMI_ALE__GPMI_ALE 262 MX28_PAD_GPMI_CLE__GPMI_CLE 263 MX28_PAD_GPMI_RESETN__GPMI_RESETN 264 >; 265 fsl,drive-strength = <MXS_DRIVE_4mA>; 266 fsl,voltage = <MXS_VOLTAGE_HIGH>; 267 fsl,pull-up = <MXS_PULL_DISABLE>; 268 }; 269 270 gpmi_status_cfg: gpmi-status-cfg { 271 fsl,pinmux-ids = < 272 MX28_PAD_GPMI_RDN__GPMI_RDN 273 MX28_PAD_GPMI_WRN__GPMI_WRN 274 MX28_PAD_GPMI_RESETN__GPMI_RESETN 275 >; 276 fsl,drive-strength = <MXS_DRIVE_12mA>; 277 }; 278 279 auart0_pins_a: auart0@0 { 280 reg = <0>; 281 fsl,pinmux-ids = < 282 MX28_PAD_AUART0_RX__AUART0_RX 283 MX28_PAD_AUART0_TX__AUART0_TX 284 MX28_PAD_AUART0_CTS__AUART0_CTS 285 MX28_PAD_AUART0_RTS__AUART0_RTS 286 >; 287 fsl,drive-strength = <MXS_DRIVE_4mA>; 288 fsl,voltage = <MXS_VOLTAGE_HIGH>; 289 fsl,pull-up = <MXS_PULL_DISABLE>; 290 }; 291 292 auart0_2pins_a: auart0-2pins@0 { 293 reg = <0>; 294 fsl,pinmux-ids = < 295 MX28_PAD_AUART0_RX__AUART0_RX 296 MX28_PAD_AUART0_TX__AUART0_TX 297 >; 298 fsl,drive-strength = <MXS_DRIVE_4mA>; 299 fsl,voltage = <MXS_VOLTAGE_HIGH>; 300 fsl,pull-up = <MXS_PULL_DISABLE>; 301 }; 302 303 auart1_pins_a: auart1@0 { 304 reg = <0>; 305 fsl,pinmux-ids = < 306 MX28_PAD_AUART1_RX__AUART1_RX 307 MX28_PAD_AUART1_TX__AUART1_TX 308 MX28_PAD_AUART1_CTS__AUART1_CTS 309 MX28_PAD_AUART1_RTS__AUART1_RTS 310 >; 311 fsl,drive-strength = <MXS_DRIVE_4mA>; 312 fsl,voltage = <MXS_VOLTAGE_HIGH>; 313 fsl,pull-up = <MXS_PULL_DISABLE>; 314 }; 315 316 auart1_2pins_a: auart1-2pins@0 { 317 reg = <0>; 318 fsl,pinmux-ids = < 319 MX28_PAD_AUART1_RX__AUART1_RX 320 MX28_PAD_AUART1_TX__AUART1_TX 321 >; 322 fsl,drive-strength = <MXS_DRIVE_4mA>; 323 fsl,voltage = <MXS_VOLTAGE_HIGH>; 324 fsl,pull-up = <MXS_PULL_DISABLE>; 325 }; 326 327 auart2_2pins_a: auart2-2pins@0 { 328 reg = <0>; 329 fsl,pinmux-ids = < 330 MX28_PAD_SSP2_SCK__AUART2_RX 331 MX28_PAD_SSP2_MOSI__AUART2_TX 332 >; 333 fsl,drive-strength = <MXS_DRIVE_4mA>; 334 fsl,voltage = <MXS_VOLTAGE_HIGH>; 335 fsl,pull-up = <MXS_PULL_DISABLE>; 336 }; 337 338 auart2_2pins_b: auart2-2pins@1 { 339 reg = <1>; 340 fsl,pinmux-ids = < 341 MX28_PAD_AUART2_RX__AUART2_RX 342 MX28_PAD_AUART2_TX__AUART2_TX 343 >; 344 fsl,drive-strength = <MXS_DRIVE_4mA>; 345 fsl,voltage = <MXS_VOLTAGE_HIGH>; 346 fsl,pull-up = <MXS_PULL_DISABLE>; 347 }; 348 349 auart2_pins_a: auart2-pins@0 { 350 reg = <0>; 351 fsl,pinmux-ids = < 352 MX28_PAD_AUART2_RX__AUART2_RX 353 MX28_PAD_AUART2_TX__AUART2_TX 354 MX28_PAD_AUART2_CTS__AUART2_CTS 355 MX28_PAD_AUART2_RTS__AUART2_RTS 356 >; 357 fsl,drive-strength = <MXS_DRIVE_4mA>; 358 fsl,voltage = <MXS_VOLTAGE_HIGH>; 359 fsl,pull-up = <MXS_PULL_DISABLE>; 360 }; 361 362 auart3_pins_a: auart3@0 { 363 reg = <0>; 364 fsl,pinmux-ids = < 365 MX28_PAD_AUART3_RX__AUART3_RX 366 MX28_PAD_AUART3_TX__AUART3_TX 367 MX28_PAD_AUART3_CTS__AUART3_CTS 368 MX28_PAD_AUART3_RTS__AUART3_RTS 369 >; 370 fsl,drive-strength = <MXS_DRIVE_4mA>; 371 fsl,voltage = <MXS_VOLTAGE_HIGH>; 372 fsl,pull-up = <MXS_PULL_DISABLE>; 373 }; 374 375 auart3_2pins_a: auart3-2pins@0 { 376 reg = <0>; 377 fsl,pinmux-ids = < 378 MX28_PAD_SSP2_MISO__AUART3_RX 379 MX28_PAD_SSP2_SS0__AUART3_TX 380 >; 381 fsl,drive-strength = <MXS_DRIVE_4mA>; 382 fsl,voltage = <MXS_VOLTAGE_HIGH>; 383 fsl,pull-up = <MXS_PULL_DISABLE>; 384 }; 385 386 auart3_2pins_b: auart3-2pins@1 { 387 reg = <1>; 388 fsl,pinmux-ids = < 389 MX28_PAD_AUART3_RX__AUART3_RX 390 MX28_PAD_AUART3_TX__AUART3_TX 391 >; 392 fsl,drive-strength = <MXS_DRIVE_4mA>; 393 fsl,voltage = <MXS_VOLTAGE_HIGH>; 394 fsl,pull-up = <MXS_PULL_DISABLE>; 395 }; 396 397 auart4_2pins_a: auart4@0 { 398 reg = <0>; 399 fsl,pinmux-ids = < 400 MX28_PAD_SSP3_SCK__AUART4_TX 401 MX28_PAD_SSP3_MOSI__AUART4_RX 402 >; 403 fsl,drive-strength = <MXS_DRIVE_4mA>; 404 fsl,voltage = <MXS_VOLTAGE_HIGH>; 405 fsl,pull-up = <MXS_PULL_DISABLE>; 406 }; 407 408 mac0_pins_a: mac0@0 { 409 reg = <0>; 410 fsl,pinmux-ids = < 411 MX28_PAD_ENET0_MDC__ENET0_MDC 412 MX28_PAD_ENET0_MDIO__ENET0_MDIO 413 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 414 MX28_PAD_ENET0_RXD0__ENET0_RXD0 415 MX28_PAD_ENET0_RXD1__ENET0_RXD1 416 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 417 MX28_PAD_ENET0_TXD0__ENET0_TXD0 418 MX28_PAD_ENET0_TXD1__ENET0_TXD1 419 MX28_PAD_ENET_CLK__CLKCTRL_ENET 420 >; 421 fsl,drive-strength = <MXS_DRIVE_8mA>; 422 fsl,voltage = <MXS_VOLTAGE_HIGH>; 423 fsl,pull-up = <MXS_PULL_ENABLE>; 424 }; 425 426 mac1_pins_a: mac1@0 { 427 reg = <0>; 428 fsl,pinmux-ids = < 429 MX28_PAD_ENET0_CRS__ENET1_RX_EN 430 MX28_PAD_ENET0_RXD2__ENET1_RXD0 431 MX28_PAD_ENET0_RXD3__ENET1_RXD1 432 MX28_PAD_ENET0_COL__ENET1_TX_EN 433 MX28_PAD_ENET0_TXD2__ENET1_TXD0 434 MX28_PAD_ENET0_TXD3__ENET1_TXD1 435 >; 436 fsl,drive-strength = <MXS_DRIVE_8mA>; 437 fsl,voltage = <MXS_VOLTAGE_HIGH>; 438 fsl,pull-up = <MXS_PULL_ENABLE>; 439 }; 440 441 mmc0_8bit_pins_a: mmc0-8bit@0 { 442 reg = <0>; 443 fsl,pinmux-ids = < 444 MX28_PAD_SSP0_DATA0__SSP0_D0 445 MX28_PAD_SSP0_DATA1__SSP0_D1 446 MX28_PAD_SSP0_DATA2__SSP0_D2 447 MX28_PAD_SSP0_DATA3__SSP0_D3 448 MX28_PAD_SSP0_DATA4__SSP0_D4 449 MX28_PAD_SSP0_DATA5__SSP0_D5 450 MX28_PAD_SSP0_DATA6__SSP0_D6 451 MX28_PAD_SSP0_DATA7__SSP0_D7 452 MX28_PAD_SSP0_CMD__SSP0_CMD 453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 454 MX28_PAD_SSP0_SCK__SSP0_SCK 455 >; 456 fsl,drive-strength = <MXS_DRIVE_8mA>; 457 fsl,voltage = <MXS_VOLTAGE_HIGH>; 458 fsl,pull-up = <MXS_PULL_ENABLE>; 459 }; 460 461 mmc0_4bit_pins_a: mmc0-4bit@0 { 462 reg = <0>; 463 fsl,pinmux-ids = < 464 MX28_PAD_SSP0_DATA0__SSP0_D0 465 MX28_PAD_SSP0_DATA1__SSP0_D1 466 MX28_PAD_SSP0_DATA2__SSP0_D2 467 MX28_PAD_SSP0_DATA3__SSP0_D3 468 MX28_PAD_SSP0_CMD__SSP0_CMD 469 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 470 MX28_PAD_SSP0_SCK__SSP0_SCK 471 >; 472 fsl,drive-strength = <MXS_DRIVE_8mA>; 473 fsl,voltage = <MXS_VOLTAGE_HIGH>; 474 fsl,pull-up = <MXS_PULL_ENABLE>; 475 }; 476 477 mmc0_cd_cfg: mmc0-cd-cfg { 478 fsl,pinmux-ids = < 479 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 480 >; 481 fsl,pull-up = <MXS_PULL_DISABLE>; 482 }; 483 484 mmc0_sck_cfg: mmc0-sck-cfg { 485 fsl,pinmux-ids = < 486 MX28_PAD_SSP0_SCK__SSP0_SCK 487 >; 488 fsl,drive-strength = <MXS_DRIVE_12mA>; 489 fsl,pull-up = <MXS_PULL_DISABLE>; 490 }; 491 492 mmc1_4bit_pins_a: mmc1-4bit@0 { 493 reg = <0>; 494 fsl,pinmux-ids = < 495 MX28_PAD_GPMI_D00__SSP1_D0 496 MX28_PAD_GPMI_D01__SSP1_D1 497 MX28_PAD_GPMI_D02__SSP1_D2 498 MX28_PAD_GPMI_D03__SSP1_D3 499 MX28_PAD_GPMI_RDY1__SSP1_CMD 500 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 501 MX28_PAD_GPMI_WRN__SSP1_SCK 502 >; 503 fsl,drive-strength = <MXS_DRIVE_8mA>; 504 fsl,voltage = <MXS_VOLTAGE_HIGH>; 505 fsl,pull-up = <MXS_PULL_ENABLE>; 506 }; 507 508 mmc1_cd_cfg: mmc1-cd-cfg { 509 fsl,pinmux-ids = < 510 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 511 >; 512 fsl,pull-up = <MXS_PULL_DISABLE>; 513 }; 514 515 mmc1_sck_cfg: mmc1-sck-cfg { 516 fsl,pinmux-ids = < 517 MX28_PAD_GPMI_WRN__SSP1_SCK 518 >; 519 fsl,drive-strength = <MXS_DRIVE_12mA>; 520 fsl,pull-up = <MXS_PULL_DISABLE>; 521 }; 522 523 524 mmc2_4bit_pins_a: mmc2-4bit@0 { 525 reg = <0>; 526 fsl,pinmux-ids = < 527 MX28_PAD_SSP0_DATA4__SSP2_D0 528 MX28_PAD_SSP1_SCK__SSP2_D1 529 MX28_PAD_SSP1_CMD__SSP2_D2 530 MX28_PAD_SSP0_DATA5__SSP2_D3 531 MX28_PAD_SSP0_DATA6__SSP2_CMD 532 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 533 MX28_PAD_SSP0_DATA7__SSP2_SCK 534 >; 535 fsl,drive-strength = <MXS_DRIVE_8mA>; 536 fsl,voltage = <MXS_VOLTAGE_HIGH>; 537 fsl,pull-up = <MXS_PULL_ENABLE>; 538 }; 539 540 mmc2_cd_cfg: mmc2-cd-cfg { 541 fsl,pinmux-ids = < 542 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 543 >; 544 fsl,pull-up = <MXS_PULL_DISABLE>; 545 }; 546 547 mmc2_sck_cfg: mmc2-sck-cfg { 548 fsl,pinmux-ids = < 549 MX28_PAD_SSP0_DATA7__SSP2_SCK 550 >; 551 fsl,drive-strength = <MXS_DRIVE_12mA>; 552 fsl,pull-up = <MXS_PULL_DISABLE>; 553 }; 554 555 i2c0_pins_a: i2c0@0 { 556 reg = <0>; 557 fsl,pinmux-ids = < 558 MX28_PAD_I2C0_SCL__I2C0_SCL 559 MX28_PAD_I2C0_SDA__I2C0_SDA 560 >; 561 fsl,drive-strength = <MXS_DRIVE_8mA>; 562 fsl,voltage = <MXS_VOLTAGE_HIGH>; 563 fsl,pull-up = <MXS_PULL_ENABLE>; 564 }; 565 566 i2c0_pins_b: i2c0@1 { 567 reg = <1>; 568 fsl,pinmux-ids = < 569 MX28_PAD_AUART0_RX__I2C0_SCL 570 MX28_PAD_AUART0_TX__I2C0_SDA 571 >; 572 fsl,drive-strength = <MXS_DRIVE_8mA>; 573 fsl,voltage = <MXS_VOLTAGE_HIGH>; 574 fsl,pull-up = <MXS_PULL_ENABLE>; 575 }; 576 577 i2c1_pins_a: i2c1@0 { 578 reg = <0>; 579 fsl,pinmux-ids = < 580 MX28_PAD_PWM0__I2C1_SCL 581 MX28_PAD_PWM1__I2C1_SDA 582 >; 583 fsl,drive-strength = <MXS_DRIVE_8mA>; 584 fsl,voltage = <MXS_VOLTAGE_HIGH>; 585 fsl,pull-up = <MXS_PULL_ENABLE>; 586 }; 587 588 i2c1_pins_b: i2c1@1 { 589 reg = <1>; 590 fsl,pinmux-ids = < 591 MX28_PAD_AUART2_CTS__I2C1_SCL 592 MX28_PAD_AUART2_RTS__I2C1_SDA 593 >; 594 fsl,drive-strength = <MXS_DRIVE_8mA>; 595 fsl,voltage = <MXS_VOLTAGE_HIGH>; 596 fsl,pull-up = <MXS_PULL_ENABLE>; 597 }; 598 599 saif0_pins_a: saif0@0 { 600 reg = <0>; 601 fsl,pinmux-ids = < 602 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 603 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 604 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 605 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 606 >; 607 fsl,drive-strength = <MXS_DRIVE_12mA>; 608 fsl,voltage = <MXS_VOLTAGE_HIGH>; 609 fsl,pull-up = <MXS_PULL_ENABLE>; 610 }; 611 612 saif0_pins_b: saif0@1 { 613 reg = <1>; 614 fsl,pinmux-ids = < 615 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 616 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 617 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 618 >; 619 fsl,drive-strength = <MXS_DRIVE_12mA>; 620 fsl,voltage = <MXS_VOLTAGE_HIGH>; 621 fsl,pull-up = <MXS_PULL_ENABLE>; 622 }; 623 624 saif1_pins_a: saif1@0 { 625 reg = <0>; 626 fsl,pinmux-ids = < 627 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 628 >; 629 fsl,drive-strength = <MXS_DRIVE_12mA>; 630 fsl,voltage = <MXS_VOLTAGE_HIGH>; 631 fsl,pull-up = <MXS_PULL_ENABLE>; 632 }; 633 634 pwm0_pins_a: pwm0@0 { 635 reg = <0>; 636 fsl,pinmux-ids = < 637 MX28_PAD_PWM0__PWM_0 638 >; 639 fsl,drive-strength = <MXS_DRIVE_4mA>; 640 fsl,voltage = <MXS_VOLTAGE_HIGH>; 641 fsl,pull-up = <MXS_PULL_DISABLE>; 642 }; 643 644 pwm2_pins_a: pwm2@0 { 645 reg = <0>; 646 fsl,pinmux-ids = < 647 MX28_PAD_PWM2__PWM_2 648 >; 649 fsl,drive-strength = <MXS_DRIVE_4mA>; 650 fsl,voltage = <MXS_VOLTAGE_HIGH>; 651 fsl,pull-up = <MXS_PULL_DISABLE>; 652 }; 653 654 pwm3_pins_a: pwm3@0 { 655 reg = <0>; 656 fsl,pinmux-ids = < 657 MX28_PAD_PWM3__PWM_3 658 >; 659 fsl,drive-strength = <MXS_DRIVE_4mA>; 660 fsl,voltage = <MXS_VOLTAGE_HIGH>; 661 fsl,pull-up = <MXS_PULL_DISABLE>; 662 }; 663 664 pwm3_pins_b: pwm3@1 { 665 reg = <1>; 666 fsl,pinmux-ids = < 667 MX28_PAD_SAIF0_MCLK__PWM_3 668 >; 669 fsl,drive-strength = <MXS_DRIVE_4mA>; 670 fsl,voltage = <MXS_VOLTAGE_HIGH>; 671 fsl,pull-up = <MXS_PULL_DISABLE>; 672 }; 673 674 pwm4_pins_a: pwm4@0 { 675 reg = <0>; 676 fsl,pinmux-ids = < 677 MX28_PAD_PWM4__PWM_4 678 >; 679 fsl,drive-strength = <MXS_DRIVE_4mA>; 680 fsl,voltage = <MXS_VOLTAGE_HIGH>; 681 fsl,pull-up = <MXS_PULL_DISABLE>; 682 }; 683 684 lcdif_24bit_pins_a: lcdif-24bit@0 { 685 reg = <0>; 686 fsl,pinmux-ids = < 687 MX28_PAD_LCD_D00__LCD_D0 688 MX28_PAD_LCD_D01__LCD_D1 689 MX28_PAD_LCD_D02__LCD_D2 690 MX28_PAD_LCD_D03__LCD_D3 691 MX28_PAD_LCD_D04__LCD_D4 692 MX28_PAD_LCD_D05__LCD_D5 693 MX28_PAD_LCD_D06__LCD_D6 694 MX28_PAD_LCD_D07__LCD_D7 695 MX28_PAD_LCD_D08__LCD_D8 696 MX28_PAD_LCD_D09__LCD_D9 697 MX28_PAD_LCD_D10__LCD_D10 698 MX28_PAD_LCD_D11__LCD_D11 699 MX28_PAD_LCD_D12__LCD_D12 700 MX28_PAD_LCD_D13__LCD_D13 701 MX28_PAD_LCD_D14__LCD_D14 702 MX28_PAD_LCD_D15__LCD_D15 703 MX28_PAD_LCD_D16__LCD_D16 704 MX28_PAD_LCD_D17__LCD_D17 705 MX28_PAD_LCD_D18__LCD_D18 706 MX28_PAD_LCD_D19__LCD_D19 707 MX28_PAD_LCD_D20__LCD_D20 708 MX28_PAD_LCD_D21__LCD_D21 709 MX28_PAD_LCD_D22__LCD_D22 710 MX28_PAD_LCD_D23__LCD_D23 711 >; 712 fsl,drive-strength = <MXS_DRIVE_4mA>; 713 fsl,voltage = <MXS_VOLTAGE_HIGH>; 714 fsl,pull-up = <MXS_PULL_DISABLE>; 715 }; 716 717 lcdif_18bit_pins_a: lcdif-18bit@0 { 718 reg = <0>; 719 fsl,pinmux-ids = < 720 MX28_PAD_LCD_D00__LCD_D0 721 MX28_PAD_LCD_D01__LCD_D1 722 MX28_PAD_LCD_D02__LCD_D2 723 MX28_PAD_LCD_D03__LCD_D3 724 MX28_PAD_LCD_D04__LCD_D4 725 MX28_PAD_LCD_D05__LCD_D5 726 MX28_PAD_LCD_D06__LCD_D6 727 MX28_PAD_LCD_D07__LCD_D7 728 MX28_PAD_LCD_D08__LCD_D8 729 MX28_PAD_LCD_D09__LCD_D9 730 MX28_PAD_LCD_D10__LCD_D10 731 MX28_PAD_LCD_D11__LCD_D11 732 MX28_PAD_LCD_D12__LCD_D12 733 MX28_PAD_LCD_D13__LCD_D13 734 MX28_PAD_LCD_D14__LCD_D14 735 MX28_PAD_LCD_D15__LCD_D15 736 MX28_PAD_LCD_D16__LCD_D16 737 MX28_PAD_LCD_D17__LCD_D17 738 >; 739 fsl,drive-strength = <MXS_DRIVE_4mA>; 740 fsl,voltage = <MXS_VOLTAGE_HIGH>; 741 fsl,pull-up = <MXS_PULL_DISABLE>; 742 }; 743 744 lcdif_16bit_pins_a: lcdif-16bit@0 { 745 reg = <0>; 746 fsl,pinmux-ids = < 747 MX28_PAD_LCD_D00__LCD_D0 748 MX28_PAD_LCD_D01__LCD_D1 749 MX28_PAD_LCD_D02__LCD_D2 750 MX28_PAD_LCD_D03__LCD_D3 751 MX28_PAD_LCD_D04__LCD_D4 752 MX28_PAD_LCD_D05__LCD_D5 753 MX28_PAD_LCD_D06__LCD_D6 754 MX28_PAD_LCD_D07__LCD_D7 755 MX28_PAD_LCD_D08__LCD_D8 756 MX28_PAD_LCD_D09__LCD_D9 757 MX28_PAD_LCD_D10__LCD_D10 758 MX28_PAD_LCD_D11__LCD_D11 759 MX28_PAD_LCD_D12__LCD_D12 760 MX28_PAD_LCD_D13__LCD_D13 761 MX28_PAD_LCD_D14__LCD_D14 762 MX28_PAD_LCD_D15__LCD_D15 763 >; 764 fsl,drive-strength = <MXS_DRIVE_4mA>; 765 fsl,voltage = <MXS_VOLTAGE_HIGH>; 766 fsl,pull-up = <MXS_PULL_DISABLE>; 767 }; 768 769 lcdif_sync_pins_a: lcdif-sync@0 { 770 reg = <0>; 771 fsl,pinmux-ids = < 772 MX28_PAD_LCD_RS__LCD_DOTCLK 773 MX28_PAD_LCD_CS__LCD_ENABLE 774 MX28_PAD_LCD_RD_E__LCD_VSYNC 775 MX28_PAD_LCD_WR_RWN__LCD_HSYNC 776 >; 777 fsl,drive-strength = <MXS_DRIVE_4mA>; 778 fsl,voltage = <MXS_VOLTAGE_HIGH>; 779 fsl,pull-up = <MXS_PULL_DISABLE>; 780 }; 781 782 can0_pins_a: can0@0 { 783 reg = <0>; 784 fsl,pinmux-ids = < 785 MX28_PAD_GPMI_RDY2__CAN0_TX 786 MX28_PAD_GPMI_RDY3__CAN0_RX 787 >; 788 fsl,drive-strength = <MXS_DRIVE_4mA>; 789 fsl,voltage = <MXS_VOLTAGE_HIGH>; 790 fsl,pull-up = <MXS_PULL_DISABLE>; 791 }; 792 793 can1_pins_a: can1@0 { 794 reg = <0>; 795 fsl,pinmux-ids = < 796 MX28_PAD_GPMI_CE2N__CAN1_TX 797 MX28_PAD_GPMI_CE3N__CAN1_RX 798 >; 799 fsl,drive-strength = <MXS_DRIVE_4mA>; 800 fsl,voltage = <MXS_VOLTAGE_HIGH>; 801 fsl,pull-up = <MXS_PULL_DISABLE>; 802 }; 803 804 spi2_pins_a: spi2@0 { 805 reg = <0>; 806 fsl,pinmux-ids = < 807 MX28_PAD_SSP2_SCK__SSP2_SCK 808 MX28_PAD_SSP2_MOSI__SSP2_CMD 809 MX28_PAD_SSP2_MISO__SSP2_D0 810 MX28_PAD_SSP2_SS0__SSP2_D3 811 >; 812 fsl,drive-strength = <MXS_DRIVE_8mA>; 813 fsl,voltage = <MXS_VOLTAGE_HIGH>; 814 fsl,pull-up = <MXS_PULL_ENABLE>; 815 }; 816 817 spi3_pins_a: spi3@0 { 818 reg = <0>; 819 fsl,pinmux-ids = < 820 MX28_PAD_AUART2_RX__SSP3_D4 821 MX28_PAD_AUART2_TX__SSP3_D5 822 MX28_PAD_SSP3_SCK__SSP3_SCK 823 MX28_PAD_SSP3_MOSI__SSP3_CMD 824 MX28_PAD_SSP3_MISO__SSP3_D0 825 MX28_PAD_SSP3_SS0__SSP3_D3 826 >; 827 fsl,drive-strength = <MXS_DRIVE_8mA>; 828 fsl,voltage = <MXS_VOLTAGE_HIGH>; 829 fsl,pull-up = <MXS_PULL_DISABLE>; 830 }; 831 832 spi3_pins_b: spi3@1 { 833 reg = <1>; 834 fsl,pinmux-ids = < 835 MX28_PAD_SSP3_SCK__SSP3_SCK 836 MX28_PAD_SSP3_MOSI__SSP3_CMD 837 MX28_PAD_SSP3_MISO__SSP3_D0 838 MX28_PAD_SSP3_SS0__SSP3_D3 839 >; 840 fsl,drive-strength = <MXS_DRIVE_8mA>; 841 fsl,voltage = <MXS_VOLTAGE_HIGH>; 842 fsl,pull-up = <MXS_PULL_ENABLE>; 843 }; 844 845 usb0_pins_a: usb0@0 { 846 reg = <0>; 847 fsl,pinmux-ids = < 848 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 849 >; 850 fsl,drive-strength = <MXS_DRIVE_12mA>; 851 fsl,voltage = <MXS_VOLTAGE_HIGH>; 852 fsl,pull-up = <MXS_PULL_DISABLE>; 853 }; 854 855 usb0_pins_b: usb0@1 { 856 reg = <1>; 857 fsl,pinmux-ids = < 858 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 859 >; 860 fsl,drive-strength = <MXS_DRIVE_12mA>; 861 fsl,voltage = <MXS_VOLTAGE_HIGH>; 862 fsl,pull-up = <MXS_PULL_DISABLE>; 863 }; 864 865 usb1_pins_a: usb1@0 { 866 reg = <0>; 867 fsl,pinmux-ids = < 868 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 869 >; 870 fsl,drive-strength = <MXS_DRIVE_12mA>; 871 fsl,voltage = <MXS_VOLTAGE_HIGH>; 872 fsl,pull-up = <MXS_PULL_DISABLE>; 873 }; 874 875 usb0_id_pins_a: usb0id@0 { 876 reg = <0>; 877 fsl,pinmux-ids = < 878 MX28_PAD_AUART1_RTS__USB0_ID 879 >; 880 fsl,drive-strength = <MXS_DRIVE_12mA>; 881 fsl,voltage = <MXS_VOLTAGE_HIGH>; 882 fsl,pull-up = <MXS_PULL_ENABLE>; 883 }; 884 885 usb0_id_pins_b: usb0id1@0 { 886 reg = <0>; 887 fsl,pinmux-ids = < 888 MX28_PAD_PWM2__USB0_ID 889 >; 890 fsl,drive-strength = <MXS_DRIVE_12mA>; 891 fsl,voltage = <MXS_VOLTAGE_HIGH>; 892 fsl,pull-up = <MXS_PULL_ENABLE>; 893 }; 894 895 }; 896 897 digctl: digctl@8001c000 { 898 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; 899 reg = <0x8001c000 0x2000>; 900 interrupts = <89>; 901 status = "disabled"; 902 }; 903 904 etm: etm@80022000 { 905 reg = <0x80022000 0x2000>; 906 status = "disabled"; 907 }; 908 909 dma_apbx: dma-apbx@80024000 { 910 compatible = "fsl,imx28-dma-apbx"; 911 reg = <0x80024000 0x2000>; 912 interrupts = <78 79 66 0 913 80 81 68 69 914 70 71 72 73 915 74 75 76 77>; 916 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", 917 "saif0", "saif1", "i2c0", "i2c1", 918 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", 919 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; 920 #dma-cells = <1>; 921 dma-channels = <16>; 922 clocks = <&clks 26>; 923 }; 924 925 dcp: dcp@80028000 { 926 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; 927 reg = <0x80028000 0x2000>; 928 interrupts = <52 53 54>; 929 status = "okay"; 930 }; 931 932 pxp: pxp@8002a000 { 933 reg = <0x8002a000 0x2000>; 934 interrupts = <39>; 935 status = "disabled"; 936 }; 937 938 ocotp: ocotp@8002c000 { 939 compatible = "fsl,imx28-ocotp", "fsl,ocotp"; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 reg = <0x8002c000 0x2000>; 943 clocks = <&clks 25>; 944 }; 945 946 axi-ahb@8002e000 { 947 reg = <0x8002e000 0x2000>; 948 status = "disabled"; 949 }; 950 951 lcdif: lcdif@80030000 { 952 compatible = "fsl,imx28-lcdif"; 953 reg = <0x80030000 0x2000>; 954 interrupts = <38>; 955 clocks = <&clks 55>; 956 dmas = <&dma_apbh 13>; 957 dma-names = "rx"; 958 status = "disabled"; 959 }; 960 961 can0: can@80032000 { 962 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; 963 reg = <0x80032000 0x2000>; 964 interrupts = <8>; 965 clocks = <&clks 58>, <&clks 58>; 966 clock-names = "ipg", "per"; 967 status = "disabled"; 968 }; 969 970 can1: can@80034000 { 971 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; 972 reg = <0x80034000 0x2000>; 973 interrupts = <9>; 974 clocks = <&clks 59>, <&clks 59>; 975 clock-names = "ipg", "per"; 976 status = "disabled"; 977 }; 978 979 simdbg: simdbg@8003c000 { 980 reg = <0x8003c000 0x200>; 981 status = "disabled"; 982 }; 983 984 simgpmisel: simgpmisel@8003c200 { 985 reg = <0x8003c200 0x100>; 986 status = "disabled"; 987 }; 988 989 simsspsel: simsspsel@8003c300 { 990 reg = <0x8003c300 0x100>; 991 status = "disabled"; 992 }; 993 994 simmemsel: simmemsel@8003c400 { 995 reg = <0x8003c400 0x100>; 996 status = "disabled"; 997 }; 998 999 gpiomon: gpiomon@8003c500 { 1000 reg = <0x8003c500 0x100>; 1001 status = "disabled"; 1002 }; 1003 1004 simenet: simenet@8003c700 { 1005 reg = <0x8003c700 0x100>; 1006 status = "disabled"; 1007 }; 1008 1009 armjtag: armjtag@8003c800 { 1010 reg = <0x8003c800 0x100>; 1011 status = "disabled"; 1012 }; 1013 }; 1014 1015 apbx@80040000 { 1016 compatible = "simple-bus"; 1017 #address-cells = <1>; 1018 #size-cells = <1>; 1019 reg = <0x80040000 0x40000>; 1020 ranges; 1021 1022 clks: clkctrl@80040000 { 1023 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; 1024 reg = <0x80040000 0x2000>; 1025 #clock-cells = <1>; 1026 }; 1027 1028 saif0: saif@80042000 { 1029 compatible = "fsl,imx28-saif"; 1030 reg = <0x80042000 0x2000>; 1031 interrupts = <59>; 1032 #clock-cells = <0>; 1033 clocks = <&clks 53>; 1034 dmas = <&dma_apbx 4>; 1035 dma-names = "rx-tx"; 1036 status = "disabled"; 1037 }; 1038 1039 power: power@80044000 { 1040 reg = <0x80044000 0x2000>; 1041 status = "disabled"; 1042 }; 1043 1044 saif1: saif@80046000 { 1045 compatible = "fsl,imx28-saif"; 1046 reg = <0x80046000 0x2000>; 1047 interrupts = <58>; 1048 clocks = <&clks 54>; 1049 dmas = <&dma_apbx 5>; 1050 dma-names = "rx-tx"; 1051 status = "disabled"; 1052 }; 1053 1054 lradc: lradc@80050000 { 1055 compatible = "fsl,imx28-lradc"; 1056 reg = <0x80050000 0x2000>; 1057 interrupts = <10 14 15 16 17 18 19 1058 20 21 22 23 24 25>; 1059 status = "disabled"; 1060 clocks = <&clks 41>; 1061 #io-channel-cells = <1>; 1062 }; 1063 1064 spdif: spdif@80054000 { 1065 reg = <0x80054000 0x2000>; 1066 interrupts = <45>; 1067 dmas = <&dma_apbx 2>; 1068 dma-names = "tx"; 1069 status = "disabled"; 1070 }; 1071 1072 mxs_rtc: rtc@80056000 { 1073 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; 1074 reg = <0x80056000 0x2000>; 1075 interrupts = <29>; 1076 }; 1077 1078 i2c0: i2c@80058000 { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 compatible = "fsl,imx28-i2c"; 1082 reg = <0x80058000 0x2000>; 1083 interrupts = <111>; 1084 clock-frequency = <100000>; 1085 dmas = <&dma_apbx 6>; 1086 dma-names = "rx-tx"; 1087 status = "disabled"; 1088 }; 1089 1090 i2c1: i2c@8005a000 { 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 compatible = "fsl,imx28-i2c"; 1094 reg = <0x8005a000 0x2000>; 1095 interrupts = <110>; 1096 clock-frequency = <100000>; 1097 dmas = <&dma_apbx 7>; 1098 dma-names = "rx-tx"; 1099 status = "disabled"; 1100 }; 1101 1102 pwm: pwm@80064000 { 1103 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; 1104 reg = <0x80064000 0x2000>; 1105 clocks = <&clks 44>; 1106 #pwm-cells = <2>; 1107 fsl,pwm-number = <8>; 1108 status = "disabled"; 1109 }; 1110 1111 timer: timrot@80068000 { 1112 compatible = "fsl,imx28-timrot", "fsl,timrot"; 1113 reg = <0x80068000 0x2000>; 1114 interrupts = <48 49 50 51>; 1115 clocks = <&clks 26>; 1116 }; 1117 1118 auart0: serial@8006a000 { 1119 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 1120 reg = <0x8006a000 0x2000>; 1121 interrupts = <112>; 1122 dmas = <&dma_apbx 8>, <&dma_apbx 9>; 1123 dma-names = "rx", "tx"; 1124 clocks = <&clks 45>; 1125 status = "disabled"; 1126 }; 1127 1128 auart1: serial@8006c000 { 1129 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 1130 reg = <0x8006c000 0x2000>; 1131 interrupts = <113>; 1132 dmas = <&dma_apbx 10>, <&dma_apbx 11>; 1133 dma-names = "rx", "tx"; 1134 clocks = <&clks 45>; 1135 status = "disabled"; 1136 }; 1137 1138 auart2: serial@8006e000 { 1139 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 1140 reg = <0x8006e000 0x2000>; 1141 interrupts = <114>; 1142 dmas = <&dma_apbx 12>, <&dma_apbx 13>; 1143 dma-names = "rx", "tx"; 1144 clocks = <&clks 45>; 1145 status = "disabled"; 1146 }; 1147 1148 auart3: serial@80070000 { 1149 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 1150 reg = <0x80070000 0x2000>; 1151 interrupts = <115>; 1152 dmas = <&dma_apbx 14>, <&dma_apbx 15>; 1153 dma-names = "rx", "tx"; 1154 clocks = <&clks 45>; 1155 status = "disabled"; 1156 }; 1157 1158 auart4: serial@80072000 { 1159 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 1160 reg = <0x80072000 0x2000>; 1161 interrupts = <116>; 1162 dmas = <&dma_apbx 0>, <&dma_apbx 1>; 1163 dma-names = "rx", "tx"; 1164 clocks = <&clks 45>; 1165 status = "disabled"; 1166 }; 1167 1168 duart: serial@80074000 { 1169 compatible = "arm,pl011", "arm,primecell"; 1170 reg = <0x80074000 0x1000>; 1171 interrupts = <47>; 1172 clocks = <&clks 45>, <&clks 26>; 1173 clock-names = "uart", "apb_pclk"; 1174 status = "disabled"; 1175 }; 1176 1177 usbphy0: usbphy@8007c000 { 1178 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; 1179 reg = <0x8007c000 0x2000>; 1180 clocks = <&clks 62>; 1181 status = "disabled"; 1182 }; 1183 1184 usbphy1: usbphy@8007e000 { 1185 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; 1186 reg = <0x8007e000 0x2000>; 1187 clocks = <&clks 63>; 1188 status = "disabled"; 1189 }; 1190 }; 1191 }; 1192 1193 ahb@80080000 { 1194 compatible = "simple-bus"; 1195 #address-cells = <1>; 1196 #size-cells = <1>; 1197 reg = <0x80080000 0x80000>; 1198 ranges; 1199 1200 usb0: usb@80080000 { 1201 compatible = "fsl,imx28-usb", "fsl,imx27-usb"; 1202 reg = <0x80080000 0x10000>; 1203 interrupts = <93>; 1204 clocks = <&clks 60>; 1205 fsl,usbphy = <&usbphy0>; 1206 status = "disabled"; 1207 }; 1208 1209 usb1: usb@80090000 { 1210 compatible = "fsl,imx28-usb", "fsl,imx27-usb"; 1211 reg = <0x80090000 0x10000>; 1212 interrupts = <92>; 1213 clocks = <&clks 61>; 1214 fsl,usbphy = <&usbphy1>; 1215 dr_mode = "host"; 1216 status = "disabled"; 1217 }; 1218 1219 dflpt: dflpt@800c0000 { 1220 reg = <0x800c0000 0x10000>; 1221 status = "disabled"; 1222 }; 1223 1224 mac0: ethernet@800f0000 { 1225 compatible = "fsl,imx28-fec"; 1226 reg = <0x800f0000 0x4000>; 1227 interrupts = <101>; 1228 clocks = <&clks 57>, <&clks 57>, <&clks 64>; 1229 clock-names = "ipg", "ahb", "enet_out"; 1230 status = "disabled"; 1231 }; 1232 1233 mac1: ethernet@800f4000 { 1234 compatible = "fsl,imx28-fec"; 1235 reg = <0x800f4000 0x4000>; 1236 interrupts = <102>; 1237 clocks = <&clks 57>, <&clks 57>; 1238 clock-names = "ipg", "ahb"; 1239 status = "disabled"; 1240 }; 1241 1242 etn_switch: switch@800f8000 { 1243 reg = <0x800f8000 0x8000>; 1244 status = "disabled"; 1245 }; 1246 }; 1247 1248 iio_hwmon { 1249 compatible = "iio-hwmon"; 1250 io-channels = <&lradc 8>; 1251 }; 1252}; 1253