1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include "imx53.dtsi" 14 15/ { 16 chosen { 17 stdout-path = &uart1; 18 }; 19 20 memory { 21 reg = <0x70000000 0x20000000>, 22 <0xb0000000 0x20000000>; 23 }; 24 25 display0: display@di0 { 26 compatible = "fsl,imx-parallel-display"; 27 interface-pix-fmt = "rgb565"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_ipu_disp0>; 30 status = "disabled"; 31 display-timings { 32 claawvga { 33 native-mode; 34 clock-frequency = <27000000>; 35 hactive = <800>; 36 vactive = <480>; 37 hback-porch = <40>; 38 hfront-porch = <60>; 39 vback-porch = <10>; 40 vfront-porch = <10>; 41 hsync-len = <20>; 42 vsync-len = <10>; 43 hsync-active = <0>; 44 vsync-active = <0>; 45 de-active = <1>; 46 pixelclk-active = <0>; 47 }; 48 }; 49 50 port { 51 display0_in: endpoint { 52 remote-endpoint = <&ipu_di0_disp0>; 53 }; 54 }; 55 }; 56 57 gpio-keys { 58 compatible = "gpio-keys"; 59 60 power { 61 label = "Power Button"; 62 gpios = <&gpio1 8 0>; 63 linux,code = <116>; /* KEY_POWER */ 64 }; 65 66 volume-up { 67 label = "Volume Up"; 68 gpios = <&gpio2 14 0>; 69 linux,code = <115>; /* KEY_VOLUMEUP */ 70 gpio-key,wakeup; 71 }; 72 73 volume-down { 74 label = "Volume Down"; 75 gpios = <&gpio2 15 0>; 76 linux,code = <114>; /* KEY_VOLUMEDOWN */ 77 gpio-key,wakeup; 78 }; 79 }; 80 81 leds { 82 compatible = "gpio-leds"; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&led_pin_gpio7_7>; 85 86 user { 87 label = "Heartbeat"; 88 gpios = <&gpio7 7 0>; 89 linux,default-trigger = "heartbeat"; 90 }; 91 }; 92 93 regulators { 94 compatible = "simple-bus"; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 reg_3p2v: regulator@0 { 99 compatible = "regulator-fixed"; 100 reg = <0>; 101 regulator-name = "3P2V"; 102 regulator-min-microvolt = <3200000>; 103 regulator-max-microvolt = <3200000>; 104 regulator-always-on; 105 }; 106 107 reg_usb_vbus: regulator@1 { 108 compatible = "regulator-fixed"; 109 reg = <1>; 110 regulator-name = "usb_vbus"; 111 regulator-min-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>; 113 gpio = <&gpio7 8 0>; 114 enable-active-high; 115 }; 116 }; 117 118 sound { 119 compatible = "fsl,imx53-qsb-sgtl5000", 120 "fsl,imx-audio-sgtl5000"; 121 model = "imx53-qsb-sgtl5000"; 122 ssi-controller = <&ssi2>; 123 audio-codec = <&sgtl5000>; 124 audio-routing = 125 "MIC_IN", "Mic Jack", 126 "Mic Jack", "Mic Bias", 127 "Headphone Jack", "HP_OUT"; 128 mux-int-port = <2>; 129 mux-ext-port = <5>; 130 }; 131}; 132 133&cpu0 { 134 /* CPU rated to 1GHz, not 1.2GHz as per the default settings */ 135 operating-points = < 136 /* kHz uV */ 137 166666 850000 138 400000 900000 139 800000 1050000 140 1000000 1200000 141 >; 142}; 143 144&esdhc1 { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_esdhc1>; 147 status = "okay"; 148}; 149 150&ipu_di0_disp0 { 151 remote-endpoint = <&display0_in>; 152}; 153 154&ssi2 { 155 status = "okay"; 156}; 157 158&esdhc3 { 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_esdhc3>; 161 cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; 162 wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; 163 bus-width = <8>; 164 status = "okay"; 165}; 166 167&iomuxc { 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_hog>; 170 171 imx53-qsb { 172 pinctrl_hog: hoggrp { 173 fsl,pins = < 174 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 175 MX53_PAD_GPIO_8__GPIO1_8 0x80000000 176 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 177 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 178 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000 179 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 180 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 181 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 182 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 183 >; 184 }; 185 186 led_pin_gpio7_7: led_gpio7_7@0 { 187 fsl,pins = < 188 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 189 >; 190 }; 191 192 pinctrl_audmux: audmuxgrp { 193 fsl,pins = < 194 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 195 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 196 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 197 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 198 >; 199 }; 200 201 pinctrl_esdhc1: esdhc1grp { 202 fsl,pins = < 203 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 204 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 205 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 206 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 207 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 208 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 209 >; 210 }; 211 212 pinctrl_esdhc3: esdhc3grp { 213 fsl,pins = < 214 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 215 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 216 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 217 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 218 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 219 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 220 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 221 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 222 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 223 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 224 >; 225 }; 226 227 pinctrl_fec: fecgrp { 228 fsl,pins = < 229 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 230 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 231 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 232 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 233 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 234 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 235 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 236 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 237 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 238 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 239 >; 240 }; 241 242 /* open drain */ 243 pinctrl_i2c1: i2c1grp { 244 fsl,pins = < 245 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec 246 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec 247 >; 248 }; 249 250 pinctrl_i2c2: i2c2grp { 251 fsl,pins = < 252 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 253 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 254 >; 255 }; 256 257 pinctrl_ipu_disp0: ipudisp0grp { 258 fsl,pins = < 259 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 260 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 261 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 262 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 263 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 264 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 265 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 266 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 267 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 268 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 269 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 270 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 271 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 272 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 273 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 274 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 275 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 276 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 277 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 278 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 279 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 280 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 281 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 282 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 283 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 284 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 285 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 286 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 287 >; 288 }; 289 290 pinctrl_vga_sync: vgasync-grp { 291 fsl,pins = < 292 /* VGA_HSYNC, VSYNC with max drive strength */ 293 MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6 294 MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6 295 >; 296 }; 297 298 pinctrl_uart1: uart1grp { 299 fsl,pins = < 300 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 301 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 302 >; 303 }; 304 }; 305}; 306 307&tve { 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_vga_sync>; 310 ddc-i2c-bus = <&i2c2>; 311 fsl,tve-mode = "vga"; 312 fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */ 313 fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */ 314 status = "okay"; 315}; 316 317&uart1 { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_uart1>; 320 status = "okay"; 321}; 322 323&i2c2 { 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_i2c2>; 326 status = "okay"; 327 328 sgtl5000: codec@0a { 329 compatible = "fsl,sgtl5000"; 330 reg = <0x0a>; 331 VDDA-supply = <®_3p2v>; 332 VDDIO-supply = <®_3p2v>; 333 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; 334 }; 335}; 336 337&i2c1 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_i2c1>; 340 status = "okay"; 341 342 accelerometer: mma8450@1c { 343 compatible = "fsl,mma8450"; 344 reg = <0x1c>; 345 }; 346}; 347 348&audmux { 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_audmux>; 351 status = "okay"; 352}; 353 354&fec { 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pinctrl_fec>; 357 phy-mode = "rmii"; 358 phy-reset-gpios = <&gpio7 6 0>; 359 status = "okay"; 360}; 361 362&sata { 363 status = "okay"; 364}; 365 366&vpu { 367 status = "okay"; 368}; 369 370&usbh1 { 371 vbus-supply = <®_usb_vbus>; 372 phy_type = "utmi"; 373 status = "okay"; 374}; 375 376&usbotg { 377 dr_mode = "peripheral"; 378 status = "okay"; 379}; 380