1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include <dt-bindings/clock/imx6qdl-clock.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15 16#include "skeleton.dtsi" 17 18/ { 19 aliases { 20 ethernet0 = &fec; 21 can0 = &can1; 22 can1 = &can2; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 gpio5 = &gpio6; 29 gpio6 = &gpio7; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 mmc2 = &usdhc3; 36 mmc3 = &usdhc4; 37 serial0 = &uart1; 38 serial1 = &uart2; 39 serial2 = &uart3; 40 serial3 = &uart4; 41 serial4 = &uart5; 42 spi0 = &ecspi1; 43 spi1 = &ecspi2; 44 spi2 = &ecspi3; 45 spi3 = &ecspi4; 46 usbphy0 = &usbphy1; 47 usbphy1 = &usbphy2; 48 }; 49 50 intc: interrupt-controller@00a01000 { 51 compatible = "arm,cortex-a9-gic"; 52 #interrupt-cells = <3>; 53 interrupt-controller; 54 reg = <0x00a01000 0x1000>, 55 <0x00a00100 0x100>; 56 interrupt-parent = <&intc>; 57 }; 58 59 clocks { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 ckil { 64 compatible = "fsl,imx-ckil", "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <32768>; 67 }; 68 69 ckih1 { 70 compatible = "fsl,imx-ckih1", "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <0>; 73 }; 74 75 osc { 76 compatible = "fsl,imx-osc", "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <24000000>; 79 }; 80 }; 81 82 soc { 83 #address-cells = <1>; 84 #size-cells = <1>; 85 compatible = "simple-bus"; 86 interrupt-parent = <&gpc>; 87 ranges; 88 89 dma_apbh: dma-apbh@00110000 { 90 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 91 reg = <0x00110000 0x2000>; 92 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 93 <0 13 IRQ_TYPE_LEVEL_HIGH>, 94 <0 13 IRQ_TYPE_LEVEL_HIGH>, 95 <0 13 IRQ_TYPE_LEVEL_HIGH>; 96 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 97 #dma-cells = <1>; 98 dma-channels = <4>; 99 clocks = <&clks IMX6QDL_CLK_APBH_DMA>; 100 }; 101 102 gpmi: gpmi-nand@00112000 { 103 compatible = "fsl,imx6q-gpmi-nand"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 107 reg-names = "gpmi-nand", "bch"; 108 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-names = "bch"; 110 clocks = <&clks IMX6QDL_CLK_GPMI_IO>, 111 <&clks IMX6QDL_CLK_GPMI_APB>, 112 <&clks IMX6QDL_CLK_GPMI_BCH>, 113 <&clks IMX6QDL_CLK_GPMI_BCH_APB>, 114 <&clks IMX6QDL_CLK_PER1_BCH>; 115 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 116 "gpmi_bch_apb", "per1_bch"; 117 dmas = <&dma_apbh 0>; 118 dma-names = "rx-tx"; 119 status = "disabled"; 120 }; 121 122 hdmi: hdmi@0120000 { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 reg = <0x00120000 0x9000>; 126 interrupts = <0 115 0x04>; 127 gpr = <&gpr>; 128 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, 129 <&clks IMX6QDL_CLK_HDMI_ISFR>; 130 clock-names = "iahb", "isfr"; 131 status = "disabled"; 132 133 port@0 { 134 reg = <0>; 135 136 hdmi_mux_0: endpoint { 137 remote-endpoint = <&ipu1_di0_hdmi>; 138 }; 139 }; 140 141 port@1 { 142 reg = <1>; 143 144 hdmi_mux_1: endpoint { 145 remote-endpoint = <&ipu1_di1_hdmi>; 146 }; 147 }; 148 }; 149 150 timer@00a00600 { 151 compatible = "arm,cortex-a9-twd-timer"; 152 reg = <0x00a00600 0x20>; 153 interrupts = <1 13 0xf01>; 154 interrupt-parent = <&intc>; 155 clocks = <&clks IMX6QDL_CLK_TWD>; 156 }; 157 158 L2: l2-cache@00a02000 { 159 compatible = "arm,pl310-cache"; 160 reg = <0x00a02000 0x1000>; 161 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 162 cache-unified; 163 cache-level = <2>; 164 arm,tag-latency = <4 2 3>; 165 arm,data-latency = <4 2 3>; 166 }; 167 168 pcie: pcie@0x01000000 { 169 compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; 170 reg = <0x01ffc000 0x04000>, 171 <0x01f00000 0x80000>; 172 reg-names = "dbi", "config"; 173 #address-cells = <3>; 174 #size-cells = <2>; 175 device_type = "pci"; 176 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ 177 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 178 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 179 num-lanes = <1>; 180 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "msi"; 182 #interrupt-cells = <1>; 183 interrupt-map-mask = <0 0 0 0x7>; 184 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 185 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 186 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 187 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 189 <&clks IMX6QDL_CLK_LVDS1_GATE>, 190 <&clks IMX6QDL_CLK_PCIE_REF_125M>; 191 clock-names = "pcie", "pcie_bus", "pcie_phy"; 192 status = "disabled"; 193 }; 194 195 pmu { 196 compatible = "arm,cortex-a9-pmu"; 197 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 198 }; 199 200 aips-bus@02000000 { /* AIPS1 */ 201 compatible = "fsl,aips-bus", "simple-bus"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 reg = <0x02000000 0x100000>; 205 ranges; 206 207 spba-bus@02000000 { 208 compatible = "fsl,spba-bus", "simple-bus"; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 reg = <0x02000000 0x40000>; 212 ranges; 213 214 spdif: spdif@02004000 { 215 compatible = "fsl,imx35-spdif"; 216 reg = <0x02004000 0x4000>; 217 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 218 dmas = <&sdma 14 18 0>, 219 <&sdma 15 18 0>; 220 dma-names = "rx", "tx"; 221 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, 222 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, 223 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, 224 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, 225 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; 226 clock-names = "core", "rxtx0", 227 "rxtx1", "rxtx2", 228 "rxtx3", "rxtx4", 229 "rxtx5", "rxtx6", 230 "rxtx7", "dma"; 231 status = "disabled"; 232 }; 233 234 ecspi1: ecspi@02008000 { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 238 reg = <0x02008000 0x4000>; 239 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&clks IMX6QDL_CLK_ECSPI1>, 241 <&clks IMX6QDL_CLK_ECSPI1>; 242 clock-names = "ipg", "per"; 243 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 244 dma-names = "rx", "tx"; 245 status = "disabled"; 246 }; 247 248 ecspi2: ecspi@0200c000 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 252 reg = <0x0200c000 0x4000>; 253 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&clks IMX6QDL_CLK_ECSPI2>, 255 <&clks IMX6QDL_CLK_ECSPI2>; 256 clock-names = "ipg", "per"; 257 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 258 dma-names = "rx", "tx"; 259 status = "disabled"; 260 }; 261 262 ecspi3: ecspi@02010000 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 266 reg = <0x02010000 0x4000>; 267 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&clks IMX6QDL_CLK_ECSPI3>, 269 <&clks IMX6QDL_CLK_ECSPI3>; 270 clock-names = "ipg", "per"; 271 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 272 dma-names = "rx", "tx"; 273 status = "disabled"; 274 }; 275 276 ecspi4: ecspi@02014000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 280 reg = <0x02014000 0x4000>; 281 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&clks IMX6QDL_CLK_ECSPI4>, 283 <&clks IMX6QDL_CLK_ECSPI4>; 284 clock-names = "ipg", "per"; 285 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 286 dma-names = "rx", "tx"; 287 status = "disabled"; 288 }; 289 290 uart1: serial@02020000 { 291 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 292 reg = <0x02020000 0x4000>; 293 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 295 <&clks IMX6QDL_CLK_UART_SERIAL>; 296 clock-names = "ipg", "per"; 297 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 298 dma-names = "rx", "tx"; 299 status = "disabled"; 300 }; 301 302 esai: esai@02024000 { 303 #sound-dai-cells = <0>; 304 compatible = "fsl,imx35-esai"; 305 reg = <0x02024000 0x4000>; 306 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, 308 <&clks IMX6QDL_CLK_ESAI_MEM>, 309 <&clks IMX6QDL_CLK_ESAI_EXTAL>, 310 <&clks IMX6QDL_CLK_ESAI_IPG>, 311 <&clks IMX6QDL_CLK_SPBA>; 312 clock-names = "core", "mem", "extal", "fsys", "dma"; 313 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; 314 dma-names = "rx", "tx"; 315 status = "disabled"; 316 }; 317 318 ssi1: ssi@02028000 { 319 #sound-dai-cells = <0>; 320 compatible = "fsl,imx6q-ssi", 321 "fsl,imx51-ssi"; 322 reg = <0x02028000 0x4000>; 323 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, 325 <&clks IMX6QDL_CLK_SSI1>; 326 clock-names = "ipg", "baud"; 327 dmas = <&sdma 37 1 0>, 328 <&sdma 38 1 0>; 329 dma-names = "rx", "tx"; 330 fsl,fifo-depth = <15>; 331 status = "disabled"; 332 }; 333 334 ssi2: ssi@0202c000 { 335 #sound-dai-cells = <0>; 336 compatible = "fsl,imx6q-ssi", 337 "fsl,imx51-ssi"; 338 reg = <0x0202c000 0x4000>; 339 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, 341 <&clks IMX6QDL_CLK_SSI2>; 342 clock-names = "ipg", "baud"; 343 dmas = <&sdma 41 1 0>, 344 <&sdma 42 1 0>; 345 dma-names = "rx", "tx"; 346 fsl,fifo-depth = <15>; 347 status = "disabled"; 348 }; 349 350 ssi3: ssi@02030000 { 351 #sound-dai-cells = <0>; 352 compatible = "fsl,imx6q-ssi", 353 "fsl,imx51-ssi"; 354 reg = <0x02030000 0x4000>; 355 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, 357 <&clks IMX6QDL_CLK_SSI3>; 358 clock-names = "ipg", "baud"; 359 dmas = <&sdma 45 1 0>, 360 <&sdma 46 1 0>; 361 dma-names = "rx", "tx"; 362 fsl,fifo-depth = <15>; 363 status = "disabled"; 364 }; 365 366 asrc: asrc@02034000 { 367 compatible = "fsl,imx53-asrc"; 368 reg = <0x02034000 0x4000>; 369 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, 371 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, 372 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 373 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 374 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 375 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, 376 <&clks IMX6QDL_CLK_SPBA>; 377 clock-names = "mem", "ipg", "asrck_0", 378 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 379 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 380 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 381 "asrck_d", "asrck_e", "asrck_f", "dma"; 382 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 383 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 384 dma-names = "rxa", "rxb", "rxc", 385 "txa", "txb", "txc"; 386 fsl,asrc-rate = <48000>; 387 fsl,asrc-width = <16>; 388 status = "okay"; 389 }; 390 391 spba@0203c000 { 392 reg = <0x0203c000 0x4000>; 393 }; 394 }; 395 396 vpu: vpu@02040000 { 397 compatible = "cnm,coda960"; 398 reg = <0x02040000 0x3c000>; 399 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, 400 <0 3 IRQ_TYPE_LEVEL_HIGH>; 401 interrupt-names = "bit", "jpeg"; 402 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 403 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; 404 clock-names = "per", "ahb"; 405 power-domains = <&gpc 1>; 406 resets = <&src 1>; 407 iram = <&ocram>; 408 }; 409 410 aipstz@0207c000 { /* AIPSTZ1 */ 411 reg = <0x0207c000 0x4000>; 412 }; 413 414 pwm1: pwm@02080000 { 415 #pwm-cells = <2>; 416 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 417 reg = <0x02080000 0x4000>; 418 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&clks IMX6QDL_CLK_IPG>, 420 <&clks IMX6QDL_CLK_PWM1>; 421 clock-names = "ipg", "per"; 422 status = "disabled"; 423 }; 424 425 pwm2: pwm@02084000 { 426 #pwm-cells = <2>; 427 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 428 reg = <0x02084000 0x4000>; 429 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clks IMX6QDL_CLK_IPG>, 431 <&clks IMX6QDL_CLK_PWM2>; 432 clock-names = "ipg", "per"; 433 status = "disabled"; 434 }; 435 436 pwm3: pwm@02088000 { 437 #pwm-cells = <2>; 438 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 439 reg = <0x02088000 0x4000>; 440 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clks IMX6QDL_CLK_IPG>, 442 <&clks IMX6QDL_CLK_PWM3>; 443 clock-names = "ipg", "per"; 444 status = "disabled"; 445 }; 446 447 pwm4: pwm@0208c000 { 448 #pwm-cells = <2>; 449 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 450 reg = <0x0208c000 0x4000>; 451 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&clks IMX6QDL_CLK_IPG>, 453 <&clks IMX6QDL_CLK_PWM4>; 454 clock-names = "ipg", "per"; 455 status = "disabled"; 456 }; 457 458 can1: flexcan@02090000 { 459 compatible = "fsl,imx6q-flexcan"; 460 reg = <0x02090000 0x4000>; 461 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, 463 <&clks IMX6QDL_CLK_CAN1_SERIAL>; 464 clock-names = "ipg", "per"; 465 status = "disabled"; 466 }; 467 468 can2: flexcan@02094000 { 469 compatible = "fsl,imx6q-flexcan"; 470 reg = <0x02094000 0x4000>; 471 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, 473 <&clks IMX6QDL_CLK_CAN2_SERIAL>; 474 clock-names = "ipg", "per"; 475 status = "disabled"; 476 }; 477 478 gpt: gpt@02098000 { 479 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 480 reg = <0x02098000 0x4000>; 481 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 483 <&clks IMX6QDL_CLK_GPT_IPG_PER>, 484 <&clks IMX6QDL_CLK_GPT_3M>; 485 clock-names = "ipg", "per", "osc_per"; 486 }; 487 488 gpio1: gpio@0209c000 { 489 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 490 reg = <0x0209c000 0x4000>; 491 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 492 <0 67 IRQ_TYPE_LEVEL_HIGH>; 493 gpio-controller; 494 #gpio-cells = <2>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 }; 498 499 gpio2: gpio@020a0000 { 500 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 501 reg = <0x020a0000 0x4000>; 502 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 503 <0 69 IRQ_TYPE_LEVEL_HIGH>; 504 gpio-controller; 505 #gpio-cells = <2>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 }; 509 510 gpio3: gpio@020a4000 { 511 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 512 reg = <0x020a4000 0x4000>; 513 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 514 <0 71 IRQ_TYPE_LEVEL_HIGH>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 }; 520 521 gpio4: gpio@020a8000 { 522 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 523 reg = <0x020a8000 0x4000>; 524 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 525 <0 73 IRQ_TYPE_LEVEL_HIGH>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 }; 531 532 gpio5: gpio@020ac000 { 533 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 534 reg = <0x020ac000 0x4000>; 535 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 536 <0 75 IRQ_TYPE_LEVEL_HIGH>; 537 gpio-controller; 538 #gpio-cells = <2>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 }; 542 543 gpio6: gpio@020b0000 { 544 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 545 reg = <0x020b0000 0x4000>; 546 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, 547 <0 77 IRQ_TYPE_LEVEL_HIGH>; 548 gpio-controller; 549 #gpio-cells = <2>; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 }; 553 554 gpio7: gpio@020b4000 { 555 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 556 reg = <0x020b4000 0x4000>; 557 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, 558 <0 79 IRQ_TYPE_LEVEL_HIGH>; 559 gpio-controller; 560 #gpio-cells = <2>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 }; 564 565 kpp: kpp@020b8000 { 566 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; 567 reg = <0x020b8000 0x4000>; 568 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&clks IMX6QDL_CLK_IPG>; 570 status = "disabled"; 571 }; 572 573 wdog1: wdog@020bc000 { 574 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 575 reg = <0x020bc000 0x4000>; 576 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&clks IMX6QDL_CLK_DUMMY>; 578 }; 579 580 wdog2: wdog@020c0000 { 581 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 582 reg = <0x020c0000 0x4000>; 583 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&clks IMX6QDL_CLK_DUMMY>; 585 status = "disabled"; 586 }; 587 588 clks: ccm@020c4000 { 589 compatible = "fsl,imx6q-ccm"; 590 reg = <0x020c4000 0x4000>; 591 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 592 <0 88 IRQ_TYPE_LEVEL_HIGH>; 593 #clock-cells = <1>; 594 }; 595 596 anatop: anatop@020c8000 { 597 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; 598 reg = <0x020c8000 0x1000>; 599 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 600 <0 54 IRQ_TYPE_LEVEL_HIGH>, 601 <0 127 IRQ_TYPE_LEVEL_HIGH>; 602 603 regulator-1p1@110 { 604 compatible = "fsl,anatop-regulator"; 605 regulator-name = "vdd1p1"; 606 regulator-min-microvolt = <800000>; 607 regulator-max-microvolt = <1375000>; 608 regulator-always-on; 609 anatop-reg-offset = <0x110>; 610 anatop-vol-bit-shift = <8>; 611 anatop-vol-bit-width = <5>; 612 anatop-min-bit-val = <4>; 613 anatop-min-voltage = <800000>; 614 anatop-max-voltage = <1375000>; 615 }; 616 617 regulator-3p0@120 { 618 compatible = "fsl,anatop-regulator"; 619 regulator-name = "vdd3p0"; 620 regulator-min-microvolt = <2800000>; 621 regulator-max-microvolt = <3150000>; 622 regulator-always-on; 623 anatop-reg-offset = <0x120>; 624 anatop-vol-bit-shift = <8>; 625 anatop-vol-bit-width = <5>; 626 anatop-min-bit-val = <0>; 627 anatop-min-voltage = <2625000>; 628 anatop-max-voltage = <3400000>; 629 }; 630 631 regulator-2p5@130 { 632 compatible = "fsl,anatop-regulator"; 633 regulator-name = "vdd2p5"; 634 regulator-min-microvolt = <2000000>; 635 regulator-max-microvolt = <2750000>; 636 regulator-always-on; 637 anatop-reg-offset = <0x130>; 638 anatop-vol-bit-shift = <8>; 639 anatop-vol-bit-width = <5>; 640 anatop-min-bit-val = <0>; 641 anatop-min-voltage = <2000000>; 642 anatop-max-voltage = <2750000>; 643 }; 644 645 reg_arm: regulator-vddcore@140 { 646 compatible = "fsl,anatop-regulator"; 647 regulator-name = "vddarm"; 648 regulator-min-microvolt = <725000>; 649 regulator-max-microvolt = <1450000>; 650 regulator-always-on; 651 anatop-reg-offset = <0x140>; 652 anatop-vol-bit-shift = <0>; 653 anatop-vol-bit-width = <5>; 654 anatop-delay-reg-offset = <0x170>; 655 anatop-delay-bit-shift = <24>; 656 anatop-delay-bit-width = <2>; 657 anatop-min-bit-val = <1>; 658 anatop-min-voltage = <725000>; 659 anatop-max-voltage = <1450000>; 660 }; 661 662 reg_pu: regulator-vddpu@140 { 663 compatible = "fsl,anatop-regulator"; 664 regulator-name = "vddpu"; 665 regulator-min-microvolt = <725000>; 666 regulator-max-microvolt = <1450000>; 667 regulator-enable-ramp-delay = <150>; 668 anatop-reg-offset = <0x140>; 669 anatop-vol-bit-shift = <9>; 670 anatop-vol-bit-width = <5>; 671 anatop-delay-reg-offset = <0x170>; 672 anatop-delay-bit-shift = <26>; 673 anatop-delay-bit-width = <2>; 674 anatop-min-bit-val = <1>; 675 anatop-min-voltage = <725000>; 676 anatop-max-voltage = <1450000>; 677 }; 678 679 reg_soc: regulator-vddsoc@140 { 680 compatible = "fsl,anatop-regulator"; 681 regulator-name = "vddsoc"; 682 regulator-min-microvolt = <725000>; 683 regulator-max-microvolt = <1450000>; 684 regulator-always-on; 685 anatop-reg-offset = <0x140>; 686 anatop-vol-bit-shift = <18>; 687 anatop-vol-bit-width = <5>; 688 anatop-delay-reg-offset = <0x170>; 689 anatop-delay-bit-shift = <28>; 690 anatop-delay-bit-width = <2>; 691 anatop-min-bit-val = <1>; 692 anatop-min-voltage = <725000>; 693 anatop-max-voltage = <1450000>; 694 }; 695 }; 696 697 tempmon: tempmon { 698 compatible = "fsl,imx6q-tempmon"; 699 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 700 fsl,tempmon = <&anatop>; 701 fsl,tempmon-data = <&ocotp>; 702 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 703 }; 704 705 usbphy1: usbphy@020c9000 { 706 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 707 reg = <0x020c9000 0x1000>; 708 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&clks IMX6QDL_CLK_USBPHY1>; 710 fsl,anatop = <&anatop>; 711 }; 712 713 usbphy2: usbphy@020ca000 { 714 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 715 reg = <0x020ca000 0x1000>; 716 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&clks IMX6QDL_CLK_USBPHY2>; 718 fsl,anatop = <&anatop>; 719 }; 720 721 snvs: snvs@020cc000 { 722 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 723 reg = <0x020cc000 0x4000>; 724 725 snvs_rtc: snvs-rtc-lp { 726 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 727 regmap = <&snvs>; 728 offset = <0x34>; 729 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 730 <0 20 IRQ_TYPE_LEVEL_HIGH>; 731 }; 732 733 snvs_poweroff: snvs-poweroff { 734 compatible = "syscon-poweroff"; 735 regmap = <&snvs>; 736 offset = <0x38>; 737 mask = <0x60>; 738 status = "disabled"; 739 }; 740 }; 741 742 epit1: epit@020d0000 { /* EPIT1 */ 743 reg = <0x020d0000 0x4000>; 744 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 745 }; 746 747 epit2: epit@020d4000 { /* EPIT2 */ 748 reg = <0x020d4000 0x4000>; 749 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 750 }; 751 752 src: src@020d8000 { 753 compatible = "fsl,imx6q-src", "fsl,imx51-src"; 754 reg = <0x020d8000 0x4000>; 755 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 756 <0 96 IRQ_TYPE_LEVEL_HIGH>; 757 #reset-cells = <1>; 758 }; 759 760 gpc: gpc@020dc000 { 761 compatible = "fsl,imx6q-gpc"; 762 reg = <0x020dc000 0x4000>; 763 interrupt-controller; 764 #interrupt-cells = <3>; 765 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, 766 <0 90 IRQ_TYPE_LEVEL_HIGH>; 767 interrupt-parent = <&intc>; 768 pu-supply = <®_pu>; 769 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 770 <&clks IMX6QDL_CLK_GPU3D_SHADER>, 771 <&clks IMX6QDL_CLK_GPU2D_CORE>, 772 <&clks IMX6QDL_CLK_GPU2D_AXI>, 773 <&clks IMX6QDL_CLK_OPENVG_AXI>, 774 <&clks IMX6QDL_CLK_VPU_AXI>; 775 #power-domain-cells = <1>; 776 }; 777 778 gpr: iomuxc-gpr@020e0000 { 779 compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; 780 reg = <0x020e0000 0x38>; 781 }; 782 783 iomuxc: iomuxc@020e0000 { 784 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 785 reg = <0x020e0000 0x4000>; 786 }; 787 788 ldb: ldb@020e0008 { 789 #address-cells = <1>; 790 #size-cells = <0>; 791 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; 792 gpr = <&gpr>; 793 status = "disabled"; 794 795 lvds-channel@0 { 796 #address-cells = <1>; 797 #size-cells = <0>; 798 reg = <0>; 799 status = "disabled"; 800 801 port@0 { 802 reg = <0>; 803 804 lvds0_mux_0: endpoint { 805 remote-endpoint = <&ipu1_di0_lvds0>; 806 }; 807 }; 808 809 port@1 { 810 reg = <1>; 811 812 lvds0_mux_1: endpoint { 813 remote-endpoint = <&ipu1_di1_lvds0>; 814 }; 815 }; 816 }; 817 818 lvds-channel@1 { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 reg = <1>; 822 status = "disabled"; 823 824 port@0 { 825 reg = <0>; 826 827 lvds1_mux_0: endpoint { 828 remote-endpoint = <&ipu1_di0_lvds1>; 829 }; 830 }; 831 832 port@1 { 833 reg = <1>; 834 835 lvds1_mux_1: endpoint { 836 remote-endpoint = <&ipu1_di1_lvds1>; 837 }; 838 }; 839 }; 840 }; 841 842 dcic1: dcic@020e4000 { 843 reg = <0x020e4000 0x4000>; 844 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; 845 }; 846 847 dcic2: dcic@020e8000 { 848 reg = <0x020e8000 0x4000>; 849 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; 850 }; 851 852 sdma: sdma@020ec000 { 853 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 854 reg = <0x020ec000 0x4000>; 855 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clks IMX6QDL_CLK_IPG>, 857 <&clks IMX6QDL_CLK_SDMA>; 858 clock-names = "ipg", "ahb"; 859 #dma-cells = <3>; 860 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 861 }; 862 }; 863 864 aips-bus@02100000 { /* AIPS2 */ 865 compatible = "fsl,aips-bus", "simple-bus"; 866 #address-cells = <1>; 867 #size-cells = <1>; 868 reg = <0x02100000 0x100000>; 869 ranges; 870 871 crypto: caam@2100000 { 872 compatible = "fsl,sec-v4.0"; 873 fsl,sec-era = <4>; 874 #address-cells = <1>; 875 #size-cells = <1>; 876 reg = <0x2100000 0x10000>; 877 ranges = <0 0x2100000 0x10000>; 878 interrupt-parent = <&intc>; 879 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, 880 <&clks IMX6QDL_CLK_CAAM_ACLK>, 881 <&clks IMX6QDL_CLK_CAAM_IPG>, 882 <&clks IMX6QDL_CLK_EIM_SLOW>; 883 clock-names = "mem", "aclk", "ipg", "emi_slow"; 884 885 sec_jr0: jr0@1000 { 886 compatible = "fsl,sec-v4.0-job-ring"; 887 reg = <0x1000 0x1000>; 888 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 889 }; 890 891 sec_jr1: jr1@2000 { 892 compatible = "fsl,sec-v4.0-job-ring"; 893 reg = <0x2000 0x1000>; 894 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 895 }; 896 }; 897 898 aipstz@0217c000 { /* AIPSTZ2 */ 899 reg = <0x0217c000 0x4000>; 900 }; 901 902 usbotg: usb@02184000 { 903 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 904 reg = <0x02184000 0x200>; 905 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clks IMX6QDL_CLK_USBOH3>; 907 fsl,usbphy = <&usbphy1>; 908 fsl,usbmisc = <&usbmisc 0>; 909 status = "disabled"; 910 }; 911 912 usbh1: usb@02184200 { 913 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 914 reg = <0x02184200 0x200>; 915 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&clks IMX6QDL_CLK_USBOH3>; 917 fsl,usbphy = <&usbphy2>; 918 fsl,usbmisc = <&usbmisc 1>; 919 dr_mode = "host"; 920 status = "disabled"; 921 }; 922 923 usbh2: usb@02184400 { 924 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 925 reg = <0x02184400 0x200>; 926 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&clks IMX6QDL_CLK_USBOH3>; 928 fsl,usbmisc = <&usbmisc 2>; 929 dr_mode = "host"; 930 status = "disabled"; 931 }; 932 933 usbh3: usb@02184600 { 934 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 935 reg = <0x02184600 0x200>; 936 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&clks IMX6QDL_CLK_USBOH3>; 938 fsl,usbmisc = <&usbmisc 3>; 939 dr_mode = "host"; 940 status = "disabled"; 941 }; 942 943 usbmisc: usbmisc@02184800 { 944 #index-cells = <1>; 945 compatible = "fsl,imx6q-usbmisc"; 946 reg = <0x02184800 0x200>; 947 clocks = <&clks IMX6QDL_CLK_USBOH3>; 948 }; 949 950 fec: ethernet@02188000 { 951 compatible = "fsl,imx6q-fec"; 952 reg = <0x02188000 0x4000>; 953 interrupts-extended = 954 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, 955 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clks IMX6QDL_CLK_ENET>, 957 <&clks IMX6QDL_CLK_ENET>, 958 <&clks IMX6QDL_CLK_ENET_REF>; 959 clock-names = "ipg", "ahb", "ptp"; 960 status = "disabled"; 961 }; 962 963 mlb@0218c000 { 964 reg = <0x0218c000 0x4000>; 965 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, 966 <0 117 IRQ_TYPE_LEVEL_HIGH>, 967 <0 126 IRQ_TYPE_LEVEL_HIGH>; 968 }; 969 970 usdhc1: usdhc@02190000 { 971 compatible = "fsl,imx6q-usdhc"; 972 reg = <0x02190000 0x4000>; 973 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&clks IMX6QDL_CLK_USDHC1>, 975 <&clks IMX6QDL_CLK_USDHC1>, 976 <&clks IMX6QDL_CLK_USDHC1>; 977 clock-names = "ipg", "ahb", "per"; 978 bus-width = <4>; 979 status = "disabled"; 980 }; 981 982 usdhc2: usdhc@02194000 { 983 compatible = "fsl,imx6q-usdhc"; 984 reg = <0x02194000 0x4000>; 985 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&clks IMX6QDL_CLK_USDHC2>, 987 <&clks IMX6QDL_CLK_USDHC2>, 988 <&clks IMX6QDL_CLK_USDHC2>; 989 clock-names = "ipg", "ahb", "per"; 990 bus-width = <4>; 991 status = "disabled"; 992 }; 993 994 usdhc3: usdhc@02198000 { 995 compatible = "fsl,imx6q-usdhc"; 996 reg = <0x02198000 0x4000>; 997 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&clks IMX6QDL_CLK_USDHC3>, 999 <&clks IMX6QDL_CLK_USDHC3>, 1000 <&clks IMX6QDL_CLK_USDHC3>; 1001 clock-names = "ipg", "ahb", "per"; 1002 bus-width = <4>; 1003 status = "disabled"; 1004 }; 1005 1006 usdhc4: usdhc@0219c000 { 1007 compatible = "fsl,imx6q-usdhc"; 1008 reg = <0x0219c000 0x4000>; 1009 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&clks IMX6QDL_CLK_USDHC4>, 1011 <&clks IMX6QDL_CLK_USDHC4>, 1012 <&clks IMX6QDL_CLK_USDHC4>; 1013 clock-names = "ipg", "ahb", "per"; 1014 bus-width = <4>; 1015 status = "disabled"; 1016 }; 1017 1018 i2c1: i2c@021a0000 { 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1022 reg = <0x021a0000 0x4000>; 1023 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&clks IMX6QDL_CLK_I2C1>; 1025 status = "disabled"; 1026 }; 1027 1028 i2c2: i2c@021a4000 { 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1032 reg = <0x021a4000 0x4000>; 1033 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&clks IMX6QDL_CLK_I2C2>; 1035 status = "disabled"; 1036 }; 1037 1038 i2c3: i2c@021a8000 { 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1042 reg = <0x021a8000 0x4000>; 1043 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&clks IMX6QDL_CLK_I2C3>; 1045 status = "disabled"; 1046 }; 1047 1048 romcp@021ac000 { 1049 reg = <0x021ac000 0x4000>; 1050 }; 1051 1052 mmdc0: mmdc@021b0000 { /* MMDC0 */ 1053 compatible = "fsl,imx6q-mmdc"; 1054 reg = <0x021b0000 0x4000>; 1055 }; 1056 1057 mmdc1: mmdc@021b4000 { /* MMDC1 */ 1058 reg = <0x021b4000 0x4000>; 1059 }; 1060 1061 weim: weim@021b8000 { 1062 compatible = "fsl,imx6q-weim"; 1063 reg = <0x021b8000 0x4000>; 1064 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; 1066 }; 1067 1068 ocotp: ocotp@021bc000 { 1069 compatible = "fsl,imx6q-ocotp", "syscon"; 1070 reg = <0x021bc000 0x4000>; 1071 }; 1072 1073 tzasc@021d0000 { /* TZASC1 */ 1074 reg = <0x021d0000 0x4000>; 1075 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 1076 }; 1077 1078 tzasc@021d4000 { /* TZASC2 */ 1079 reg = <0x021d4000 0x4000>; 1080 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 1081 }; 1082 1083 audmux: audmux@021d8000 { 1084 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 1085 reg = <0x021d8000 0x4000>; 1086 status = "disabled"; 1087 }; 1088 1089 mipi_csi: mipi@021dc000 { 1090 reg = <0x021dc000 0x4000>; 1091 }; 1092 1093 mipi_dsi: mipi@021e0000 { 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 reg = <0x021e0000 0x4000>; 1097 status = "disabled"; 1098 1099 ports { 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 1103 port@0 { 1104 reg = <0>; 1105 1106 mipi_mux_0: endpoint { 1107 remote-endpoint = <&ipu1_di0_mipi>; 1108 }; 1109 }; 1110 1111 port@1 { 1112 reg = <1>; 1113 1114 mipi_mux_1: endpoint { 1115 remote-endpoint = <&ipu1_di1_mipi>; 1116 }; 1117 }; 1118 }; 1119 }; 1120 1121 vdoa@021e4000 { 1122 reg = <0x021e4000 0x4000>; 1123 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 1124 }; 1125 1126 uart2: serial@021e8000 { 1127 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1128 reg = <0x021e8000 0x4000>; 1129 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1131 <&clks IMX6QDL_CLK_UART_SERIAL>; 1132 clock-names = "ipg", "per"; 1133 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1134 dma-names = "rx", "tx"; 1135 status = "disabled"; 1136 }; 1137 1138 uart3: serial@021ec000 { 1139 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1140 reg = <0x021ec000 0x4000>; 1141 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1143 <&clks IMX6QDL_CLK_UART_SERIAL>; 1144 clock-names = "ipg", "per"; 1145 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1146 dma-names = "rx", "tx"; 1147 status = "disabled"; 1148 }; 1149 1150 uart4: serial@021f0000 { 1151 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1152 reg = <0x021f0000 0x4000>; 1153 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1155 <&clks IMX6QDL_CLK_UART_SERIAL>; 1156 clock-names = "ipg", "per"; 1157 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1158 dma-names = "rx", "tx"; 1159 status = "disabled"; 1160 }; 1161 1162 uart5: serial@021f4000 { 1163 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1164 reg = <0x021f4000 0x4000>; 1165 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1167 <&clks IMX6QDL_CLK_UART_SERIAL>; 1168 clock-names = "ipg", "per"; 1169 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1170 dma-names = "rx", "tx"; 1171 status = "disabled"; 1172 }; 1173 }; 1174 1175 ipu1: ipu@02400000 { 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 compatible = "fsl,imx6q-ipu"; 1179 reg = <0x02400000 0x400000>; 1180 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, 1181 <0 5 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&clks IMX6QDL_CLK_IPU1>, 1183 <&clks IMX6QDL_CLK_IPU1_DI0>, 1184 <&clks IMX6QDL_CLK_IPU1_DI1>; 1185 clock-names = "bus", "di0", "di1"; 1186 resets = <&src 2>; 1187 1188 ipu1_csi0: port@0 { 1189 reg = <0>; 1190 }; 1191 1192 ipu1_csi1: port@1 { 1193 reg = <1>; 1194 }; 1195 1196 ipu1_di0: port@2 { 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 reg = <2>; 1200 1201 ipu1_di0_disp0: endpoint@0 { 1202 }; 1203 1204 ipu1_di0_hdmi: endpoint@1 { 1205 remote-endpoint = <&hdmi_mux_0>; 1206 }; 1207 1208 ipu1_di0_mipi: endpoint@2 { 1209 remote-endpoint = <&mipi_mux_0>; 1210 }; 1211 1212 ipu1_di0_lvds0: endpoint@3 { 1213 remote-endpoint = <&lvds0_mux_0>; 1214 }; 1215 1216 ipu1_di0_lvds1: endpoint@4 { 1217 remote-endpoint = <&lvds1_mux_0>; 1218 }; 1219 }; 1220 1221 ipu1_di1: port@3 { 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 reg = <3>; 1225 1226 ipu1_di0_disp1: endpoint@0 { 1227 }; 1228 1229 ipu1_di1_hdmi: endpoint@1 { 1230 remote-endpoint = <&hdmi_mux_1>; 1231 }; 1232 1233 ipu1_di1_mipi: endpoint@2 { 1234 remote-endpoint = <&mipi_mux_1>; 1235 }; 1236 1237 ipu1_di1_lvds0: endpoint@3 { 1238 remote-endpoint = <&lvds0_mux_1>; 1239 }; 1240 1241 ipu1_di1_lvds1: endpoint@4 { 1242 remote-endpoint = <&lvds1_mux_1>; 1243 }; 1244 }; 1245 }; 1246 }; 1247}; 1248