1/ { 2 mbus { 3 pciec: pcie-controller { 4 compatible = "marvell,kirkwood-pcie"; 5 status = "disabled"; 6 device_type = "pci"; 7 8 #address-cells = <3>; 9 #size-cells = <2>; 10 11 bus-range = <0x00 0xff>; 12 13 ranges = 14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 15 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 16 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 17 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 18 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 19 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 20 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; 21 22 pcie0: pcie@1,0 { 23 device_type = "pci"; 24 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 25 reg = <0x0800 0 0 0 0>; 26 #address-cells = <3>; 27 #size-cells = <2>; 28 #interrupt-cells = <1>; 29 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 30 0x81000000 0 0 0x81000000 0x1 0 1 0>; 31 interrupt-map-mask = <0 0 0 0>; 32 interrupt-map = <0 0 0 0 &intc 9>; 33 marvell,pcie-port = <0>; 34 marvell,pcie-lane = <0>; 35 clocks = <&gate_clk 2>; 36 status = "disabled"; 37 }; 38 39 pcie1: pcie@2,0 { 40 device_type = "pci"; 41 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; 42 reg = <0x1000 0 0 0 0>; 43 #address-cells = <3>; 44 #size-cells = <2>; 45 #interrupt-cells = <1>; 46 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 47 0x81000000 0 0 0x81000000 0x2 0 1 0>; 48 interrupt-map-mask = <0 0 0 0>; 49 interrupt-map = <0 0 0 0 &intc 10>; 50 marvell,pcie-port = <1>; 51 marvell,pcie-lane = <0>; 52 clocks = <&gate_clk 18>; 53 status = "disabled"; 54 }; 55 }; 56 }; 57 ocp@f1000000 { 58 59 pinctrl: pin-controller@10000 { 60 compatible = "marvell,88f6282-pinctrl"; 61 62 pmx_sata0: pmx-sata0 { 63 marvell,pins = "mpp5", "mpp21", "mpp23"; 64 marvell,function = "sata0"; 65 }; 66 pmx_sata1: pmx-sata1 { 67 marvell,pins = "mpp4", "mpp20", "mpp22"; 68 marvell,function = "sata1"; 69 }; 70 71 /* 72 * Default I2C1 pinctrl setting on mpp36/mpp37, 73 * overwrite marvell,pins on board level if required. 74 */ 75 pmx_twsi1: pmx-twsi1 { 76 marvell,pins = "mpp36", "mpp37"; 77 marvell,function = "twsi1"; 78 }; 79 80 pmx_sdio: pmx-sdio { 81 marvell,pins = "mpp12", "mpp13", "mpp14", 82 "mpp15", "mpp16", "mpp17"; 83 marvell,function = "sdio"; 84 }; 85 }; 86 87 thermal: thermal@10078 { 88 compatible = "marvell,kirkwood-thermal"; 89 reg = <0x10078 0x4>; 90 status = "okay"; 91 }; 92 93 rtc: rtc@10300 { 94 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; 95 reg = <0x10300 0x20>; 96 interrupts = <53>; 97 clocks = <&gate_clk 7>; 98 }; 99 100 i2c1: i2c@11100 { 101 compatible = "marvell,mv64xxx-i2c"; 102 reg = <0x11100 0x20>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 interrupts = <32>; 106 clock-frequency = <100000>; 107 clocks = <&gate_clk 7>; 108 pinctrl-0 = <&pmx_twsi1>; 109 pinctrl-names = "default"; 110 status = "disabled"; 111 }; 112 113 sata: sata@80000 { 114 compatible = "marvell,orion-sata"; 115 reg = <0x80000 0x5000>; 116 interrupts = <21>; 117 clocks = <&gate_clk 14>, <&gate_clk 15>; 118 clock-names = "0", "1"; 119 phys = <&sata_phy0>, <&sata_phy1>; 120 phy-names = "port0", "port1"; 121 status = "disabled"; 122 }; 123 124 sdio: mvsdio@90000 { 125 compatible = "marvell,orion-sdio"; 126 reg = <0x90000 0x200>; 127 interrupts = <28>; 128 clocks = <&gate_clk 4>; 129 pinctrl-0 = <&pmx_sdio>; 130 pinctrl-names = "default"; 131 bus-width = <4>; 132 cap-sdio-irq; 133 cap-sd-highspeed; 134 cap-mmc-highspeed; 135 status = "disabled"; 136 }; 137 }; 138}; 139