1/* 2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * Based on "omap4.dtsi" 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/pinctrl/omap.h> 13 14#include "skeleton.dtsi" 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 compatible = "ti,omap5"; 21 interrupt-parent = <&wakeupgen>; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 i2c3 = &i2c4; 28 i2c4 = &i2c5; 29 mmc0 = &mmc1; 30 mmc1 = &mmc2; 31 mmc2 = &mmc3; 32 mmc3 = &mmc4; 33 mmc4 = &mmc5; 34 serial0 = &uart1; 35 serial1 = &uart2; 36 serial2 = &uart3; 37 serial3 = &uart4; 38 serial4 = &uart5; 39 serial5 = &uart6; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a15"; 49 reg = <0x0>; 50 51 operating-points = < 52 /* kHz uV */ 53 1000000 1060000 54 1500000 1250000 55 >; 56 57 clocks = <&dpll_mpu_ck>; 58 clock-names = "cpu"; 59 60 clock-latency = <300000>; /* From omap-cpufreq driver */ 61 62 /* cooling options */ 63 cooling-min-level = <0>; 64 cooling-max-level = <2>; 65 #cooling-cells = <2>; /* min followed by max */ 66 }; 67 cpu@1 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a15"; 70 reg = <0x1>; 71 }; 72 }; 73 74 thermal-zones { 75 #include "omap4-cpu-thermal.dtsi" 76 #include "omap5-gpu-thermal.dtsi" 77 #include "omap5-core-thermal.dtsi" 78 }; 79 80 timer { 81 compatible = "arm,armv7-timer"; 82 /* PPI secure/nonsecure IRQ */ 83 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 84 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 85 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, 86 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; 87 interrupt-parent = <&gic>; 88 }; 89 90 pmu { 91 compatible = "arm,cortex-a15-pmu"; 92 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 94 }; 95 96 gic: interrupt-controller@48211000 { 97 compatible = "arm,cortex-a15-gic"; 98 interrupt-controller; 99 #interrupt-cells = <3>; 100 reg = <0x48211000 0x1000>, 101 <0x48212000 0x1000>, 102 <0x48214000 0x2000>, 103 <0x48216000 0x2000>; 104 interrupt-parent = <&gic>; 105 }; 106 107 wakeupgen: interrupt-controller@48281000 { 108 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 109 interrupt-controller; 110 #interrupt-cells = <3>; 111 reg = <0x48281000 0x1000>; 112 interrupt-parent = <&gic>; 113 }; 114 115 /* 116 * The soc node represents the soc top level view. It is used for IPs 117 * that are not memory mapped in the MPU view or for the MPU itself. 118 */ 119 soc { 120 compatible = "ti,omap-infra"; 121 mpu { 122 compatible = "ti,omap4-mpu"; 123 ti,hwmods = "mpu"; 124 sram = <&ocmcram>; 125 }; 126 }; 127 128 /* 129 * XXX: Use a flat representation of the OMAP3 interconnect. 130 * The real OMAP interconnect network is quite complex. 131 * Since it will not bring real advantage to represent that in DT for 132 * the moment, just use a fake OCP bus entry to represent the whole bus 133 * hierarchy. 134 */ 135 ocp { 136 compatible = "ti,omap5-l3-noc", "simple-bus"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges; 140 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 141 reg = <0x44000000 0x2000>, 142 <0x44800000 0x3000>, 143 <0x45000000 0x4000>; 144 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 146 147 l4_cfg: l4@4a000000 { 148 compatible = "ti,omap5-l4-cfg", "simple-bus"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges = <0 0x4a000000 0x22a000>; 152 153 scm_core: scm@2000 { 154 compatible = "ti,omap5-scm-core", "simple-bus"; 155 reg = <0x2000 0x1000>; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges = <0 0x2000 0x800>; 159 160 scm_conf: scm_conf@0 { 161 compatible = "syscon"; 162 reg = <0x0 0x800>; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 }; 166 }; 167 168 scm_padconf_core: scm@2800 { 169 compatible = "ti,omap5-scm-padconf-core", 170 "simple-bus"; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 ranges = <0 0x2800 0x800>; 174 175 omap5_pmx_core: pinmux@40 { 176 compatible = "ti,omap5-padconf", 177 "pinctrl-single"; 178 reg = <0x40 0x01b6>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 #interrupt-cells = <1>; 182 interrupt-controller; 183 pinctrl-single,register-width = <16>; 184 pinctrl-single,function-mask = <0x7fff>; 185 }; 186 187 omap5_padconf_global: omap5_padconf_global@5a0 { 188 compatible = "syscon", 189 "simple-bus"; 190 reg = <0x5a0 0xec>; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0 0x5a0 0xec>; 194 195 pbias_regulator: pbias_regulator { 196 compatible = "ti,pbias-omap5", "ti,pbias-omap"; 197 reg = <0x60 0x4>; 198 syscon = <&omap5_padconf_global>; 199 pbias_mmc_reg: pbias_mmc_omap5 { 200 regulator-name = "pbias_mmc_omap5"; 201 regulator-min-microvolt = <1800000>; 202 regulator-max-microvolt = <3000000>; 203 }; 204 }; 205 }; 206 }; 207 208 cm_core_aon: cm_core_aon@4000 { 209 compatible = "ti,omap5-cm-core-aon"; 210 reg = <0x4000 0x2000>; 211 212 cm_core_aon_clocks: clocks { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 }; 216 217 cm_core_aon_clockdomains: clockdomains { 218 }; 219 }; 220 221 cm_core: cm_core@8000 { 222 compatible = "ti,omap5-cm-core"; 223 reg = <0x8000 0x3000>; 224 225 cm_core_clocks: clocks { 226 #address-cells = <1>; 227 #size-cells = <0>; 228 }; 229 230 cm_core_clockdomains: clockdomains { 231 }; 232 }; 233 }; 234 235 l4_wkup: l4@4ae00000 { 236 compatible = "ti,omap5-l4-wkup", "simple-bus"; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 ranges = <0 0x4ae00000 0x2b000>; 240 241 counter32k: counter@4000 { 242 compatible = "ti,omap-counter32k"; 243 reg = <0x4000 0x40>; 244 ti,hwmods = "counter_32k"; 245 }; 246 247 prm: prm@6000 { 248 compatible = "ti,omap5-prm"; 249 reg = <0x6000 0x3000>; 250 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 251 252 prm_clocks: clocks { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 }; 256 257 prm_clockdomains: clockdomains { 258 }; 259 }; 260 261 scrm: scrm@a000 { 262 compatible = "ti,omap5-scrm"; 263 reg = <0xa000 0x2000>; 264 265 scrm_clocks: clocks { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 }; 269 270 scrm_clockdomains: clockdomains { 271 }; 272 }; 273 274 omap5_pmx_wkup: pinmux@c840 { 275 compatible = "ti,omap5-padconf", 276 "pinctrl-single"; 277 reg = <0xc840 0x0038>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 #interrupt-cells = <1>; 281 interrupt-controller; 282 pinctrl-single,register-width = <16>; 283 pinctrl-single,function-mask = <0x7fff>; 284 }; 285 }; 286 287 ocmcram: ocmcram@40300000 { 288 compatible = "mmio-sram"; 289 reg = <0x40300000 0x20000>; /* 128k */ 290 }; 291 292 sdma: dma-controller@4a056000 { 293 compatible = "ti,omap4430-sdma"; 294 reg = <0x4a056000 0x1000>; 295 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 299 #dma-cells = <1>; 300 dma-channels = <32>; 301 dma-requests = <127>; 302 }; 303 304 gpio1: gpio@4ae10000 { 305 compatible = "ti,omap4-gpio"; 306 reg = <0x4ae10000 0x200>; 307 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 308 ti,hwmods = "gpio1"; 309 ti,gpio-always-on; 310 gpio-controller; 311 #gpio-cells = <2>; 312 interrupt-controller; 313 #interrupt-cells = <2>; 314 }; 315 316 gpio2: gpio@48055000 { 317 compatible = "ti,omap4-gpio"; 318 reg = <0x48055000 0x200>; 319 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 320 ti,hwmods = "gpio2"; 321 gpio-controller; 322 #gpio-cells = <2>; 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 }; 326 327 gpio3: gpio@48057000 { 328 compatible = "ti,omap4-gpio"; 329 reg = <0x48057000 0x200>; 330 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 331 ti,hwmods = "gpio3"; 332 gpio-controller; 333 #gpio-cells = <2>; 334 interrupt-controller; 335 #interrupt-cells = <2>; 336 }; 337 338 gpio4: gpio@48059000 { 339 compatible = "ti,omap4-gpio"; 340 reg = <0x48059000 0x200>; 341 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 342 ti,hwmods = "gpio4"; 343 gpio-controller; 344 #gpio-cells = <2>; 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 }; 348 349 gpio5: gpio@4805b000 { 350 compatible = "ti,omap4-gpio"; 351 reg = <0x4805b000 0x200>; 352 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 353 ti,hwmods = "gpio5"; 354 gpio-controller; 355 #gpio-cells = <2>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 }; 359 360 gpio6: gpio@4805d000 { 361 compatible = "ti,omap4-gpio"; 362 reg = <0x4805d000 0x200>; 363 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 364 ti,hwmods = "gpio6"; 365 gpio-controller; 366 #gpio-cells = <2>; 367 interrupt-controller; 368 #interrupt-cells = <2>; 369 }; 370 371 gpio7: gpio@48051000 { 372 compatible = "ti,omap4-gpio"; 373 reg = <0x48051000 0x200>; 374 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 375 ti,hwmods = "gpio7"; 376 gpio-controller; 377 #gpio-cells = <2>; 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 }; 381 382 gpio8: gpio@48053000 { 383 compatible = "ti,omap4-gpio"; 384 reg = <0x48053000 0x200>; 385 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 386 ti,hwmods = "gpio8"; 387 gpio-controller; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 }; 392 393 gpmc: gpmc@50000000 { 394 compatible = "ti,omap4430-gpmc"; 395 reg = <0x50000000 0x1000>; 396 #address-cells = <2>; 397 #size-cells = <1>; 398 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 399 gpmc,num-cs = <8>; 400 gpmc,num-waitpins = <4>; 401 ti,hwmods = "gpmc"; 402 clocks = <&l3_iclk_div>; 403 clock-names = "fck"; 404 }; 405 406 i2c1: i2c@48070000 { 407 compatible = "ti,omap4-i2c"; 408 reg = <0x48070000 0x100>; 409 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 ti,hwmods = "i2c1"; 413 }; 414 415 i2c2: i2c@48072000 { 416 compatible = "ti,omap4-i2c"; 417 reg = <0x48072000 0x100>; 418 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 ti,hwmods = "i2c2"; 422 }; 423 424 i2c3: i2c@48060000 { 425 compatible = "ti,omap4-i2c"; 426 reg = <0x48060000 0x100>; 427 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 ti,hwmods = "i2c3"; 431 }; 432 433 i2c4: i2c@4807a000 { 434 compatible = "ti,omap4-i2c"; 435 reg = <0x4807a000 0x100>; 436 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 ti,hwmods = "i2c4"; 440 }; 441 442 i2c5: i2c@4807c000 { 443 compatible = "ti,omap4-i2c"; 444 reg = <0x4807c000 0x100>; 445 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 ti,hwmods = "i2c5"; 449 }; 450 451 hwspinlock: spinlock@4a0f6000 { 452 compatible = "ti,omap4-hwspinlock"; 453 reg = <0x4a0f6000 0x1000>; 454 ti,hwmods = "spinlock"; 455 #hwlock-cells = <1>; 456 }; 457 458 mcspi1: spi@48098000 { 459 compatible = "ti,omap4-mcspi"; 460 reg = <0x48098000 0x200>; 461 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 ti,hwmods = "mcspi1"; 465 ti,spi-num-cs = <4>; 466 dmas = <&sdma 35>, 467 <&sdma 36>, 468 <&sdma 37>, 469 <&sdma 38>, 470 <&sdma 39>, 471 <&sdma 40>, 472 <&sdma 41>, 473 <&sdma 42>; 474 dma-names = "tx0", "rx0", "tx1", "rx1", 475 "tx2", "rx2", "tx3", "rx3"; 476 }; 477 478 mcspi2: spi@4809a000 { 479 compatible = "ti,omap4-mcspi"; 480 reg = <0x4809a000 0x200>; 481 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 ti,hwmods = "mcspi2"; 485 ti,spi-num-cs = <2>; 486 dmas = <&sdma 43>, 487 <&sdma 44>, 488 <&sdma 45>, 489 <&sdma 46>; 490 dma-names = "tx0", "rx0", "tx1", "rx1"; 491 }; 492 493 mcspi3: spi@480b8000 { 494 compatible = "ti,omap4-mcspi"; 495 reg = <0x480b8000 0x200>; 496 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 ti,hwmods = "mcspi3"; 500 ti,spi-num-cs = <2>; 501 dmas = <&sdma 15>, <&sdma 16>; 502 dma-names = "tx0", "rx0"; 503 }; 504 505 mcspi4: spi@480ba000 { 506 compatible = "ti,omap4-mcspi"; 507 reg = <0x480ba000 0x200>; 508 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 ti,hwmods = "mcspi4"; 512 ti,spi-num-cs = <1>; 513 dmas = <&sdma 70>, <&sdma 71>; 514 dma-names = "tx0", "rx0"; 515 }; 516 517 uart1: serial@4806a000 { 518 compatible = "ti,omap4-uart"; 519 reg = <0x4806a000 0x100>; 520 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 521 ti,hwmods = "uart1"; 522 clock-frequency = <48000000>; 523 }; 524 525 uart2: serial@4806c000 { 526 compatible = "ti,omap4-uart"; 527 reg = <0x4806c000 0x100>; 528 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 529 ti,hwmods = "uart2"; 530 clock-frequency = <48000000>; 531 }; 532 533 uart3: serial@48020000 { 534 compatible = "ti,omap4-uart"; 535 reg = <0x48020000 0x100>; 536 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 537 ti,hwmods = "uart3"; 538 clock-frequency = <48000000>; 539 }; 540 541 uart4: serial@4806e000 { 542 compatible = "ti,omap4-uart"; 543 reg = <0x4806e000 0x100>; 544 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 545 ti,hwmods = "uart4"; 546 clock-frequency = <48000000>; 547 }; 548 549 uart5: serial@48066000 { 550 compatible = "ti,omap4-uart"; 551 reg = <0x48066000 0x100>; 552 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 553 ti,hwmods = "uart5"; 554 clock-frequency = <48000000>; 555 }; 556 557 uart6: serial@48068000 { 558 compatible = "ti,omap4-uart"; 559 reg = <0x48068000 0x100>; 560 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 561 ti,hwmods = "uart6"; 562 clock-frequency = <48000000>; 563 }; 564 565 mmc1: mmc@4809c000 { 566 compatible = "ti,omap4-hsmmc"; 567 reg = <0x4809c000 0x400>; 568 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 569 ti,hwmods = "mmc1"; 570 ti,dual-volt; 571 ti,needs-special-reset; 572 dmas = <&sdma 61>, <&sdma 62>; 573 dma-names = "tx", "rx"; 574 pbias-supply = <&pbias_mmc_reg>; 575 }; 576 577 mmc2: mmc@480b4000 { 578 compatible = "ti,omap4-hsmmc"; 579 reg = <0x480b4000 0x400>; 580 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 581 ti,hwmods = "mmc2"; 582 ti,needs-special-reset; 583 dmas = <&sdma 47>, <&sdma 48>; 584 dma-names = "tx", "rx"; 585 }; 586 587 mmc3: mmc@480ad000 { 588 compatible = "ti,omap4-hsmmc"; 589 reg = <0x480ad000 0x400>; 590 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 591 ti,hwmods = "mmc3"; 592 ti,needs-special-reset; 593 dmas = <&sdma 77>, <&sdma 78>; 594 dma-names = "tx", "rx"; 595 }; 596 597 mmc4: mmc@480d1000 { 598 compatible = "ti,omap4-hsmmc"; 599 reg = <0x480d1000 0x400>; 600 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 601 ti,hwmods = "mmc4"; 602 ti,needs-special-reset; 603 dmas = <&sdma 57>, <&sdma 58>; 604 dma-names = "tx", "rx"; 605 }; 606 607 mmc5: mmc@480d5000 { 608 compatible = "ti,omap4-hsmmc"; 609 reg = <0x480d5000 0x400>; 610 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 611 ti,hwmods = "mmc5"; 612 ti,needs-special-reset; 613 dmas = <&sdma 59>, <&sdma 60>; 614 dma-names = "tx", "rx"; 615 }; 616 617 mmu_dsp: mmu@4a066000 { 618 compatible = "ti,omap4-iommu"; 619 reg = <0x4a066000 0x100>; 620 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 621 ti,hwmods = "mmu_dsp"; 622 #iommu-cells = <0>; 623 }; 624 625 mmu_ipu: mmu@55082000 { 626 compatible = "ti,omap4-iommu"; 627 reg = <0x55082000 0x100>; 628 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 629 ti,hwmods = "mmu_ipu"; 630 #iommu-cells = <0>; 631 ti,iommu-bus-err-back; 632 }; 633 634 keypad: keypad@4ae1c000 { 635 compatible = "ti,omap4-keypad"; 636 reg = <0x4ae1c000 0x400>; 637 ti,hwmods = "kbd"; 638 }; 639 640 mcpdm: mcpdm@40132000 { 641 compatible = "ti,omap4-mcpdm"; 642 reg = <0x40132000 0x7f>, /* MPU private access */ 643 <0x49032000 0x7f>; /* L3 Interconnect */ 644 reg-names = "mpu", "dma"; 645 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 646 ti,hwmods = "mcpdm"; 647 dmas = <&sdma 65>, 648 <&sdma 66>; 649 dma-names = "up_link", "dn_link"; 650 status = "disabled"; 651 }; 652 653 dmic: dmic@4012e000 { 654 compatible = "ti,omap4-dmic"; 655 reg = <0x4012e000 0x7f>, /* MPU private access */ 656 <0x4902e000 0x7f>; /* L3 Interconnect */ 657 reg-names = "mpu", "dma"; 658 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 659 ti,hwmods = "dmic"; 660 dmas = <&sdma 67>; 661 dma-names = "up_link"; 662 status = "disabled"; 663 }; 664 665 mcbsp1: mcbsp@40122000 { 666 compatible = "ti,omap4-mcbsp"; 667 reg = <0x40122000 0xff>, /* MPU private access */ 668 <0x49022000 0xff>; /* L3 Interconnect */ 669 reg-names = "mpu", "dma"; 670 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 671 interrupt-names = "common"; 672 ti,buffer-size = <128>; 673 ti,hwmods = "mcbsp1"; 674 dmas = <&sdma 33>, 675 <&sdma 34>; 676 dma-names = "tx", "rx"; 677 status = "disabled"; 678 }; 679 680 mcbsp2: mcbsp@40124000 { 681 compatible = "ti,omap4-mcbsp"; 682 reg = <0x40124000 0xff>, /* MPU private access */ 683 <0x49024000 0xff>; /* L3 Interconnect */ 684 reg-names = "mpu", "dma"; 685 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 686 interrupt-names = "common"; 687 ti,buffer-size = <128>; 688 ti,hwmods = "mcbsp2"; 689 dmas = <&sdma 17>, 690 <&sdma 18>; 691 dma-names = "tx", "rx"; 692 status = "disabled"; 693 }; 694 695 mcbsp3: mcbsp@40126000 { 696 compatible = "ti,omap4-mcbsp"; 697 reg = <0x40126000 0xff>, /* MPU private access */ 698 <0x49026000 0xff>; /* L3 Interconnect */ 699 reg-names = "mpu", "dma"; 700 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "common"; 702 ti,buffer-size = <128>; 703 ti,hwmods = "mcbsp3"; 704 dmas = <&sdma 19>, 705 <&sdma 20>; 706 dma-names = "tx", "rx"; 707 status = "disabled"; 708 }; 709 710 mailbox: mailbox@4a0f4000 { 711 compatible = "ti,omap4-mailbox"; 712 reg = <0x4a0f4000 0x200>; 713 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 714 ti,hwmods = "mailbox"; 715 #mbox-cells = <1>; 716 ti,mbox-num-users = <3>; 717 ti,mbox-num-fifos = <8>; 718 mbox_ipu: mbox_ipu { 719 ti,mbox-tx = <0 0 0>; 720 ti,mbox-rx = <1 0 0>; 721 }; 722 mbox_dsp: mbox_dsp { 723 ti,mbox-tx = <3 0 0>; 724 ti,mbox-rx = <2 0 0>; 725 }; 726 }; 727 728 timer1: timer@4ae18000 { 729 compatible = "ti,omap5430-timer"; 730 reg = <0x4ae18000 0x80>; 731 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 732 ti,hwmods = "timer1"; 733 ti,timer-alwon; 734 }; 735 736 timer2: timer@48032000 { 737 compatible = "ti,omap5430-timer"; 738 reg = <0x48032000 0x80>; 739 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 740 ti,hwmods = "timer2"; 741 }; 742 743 timer3: timer@48034000 { 744 compatible = "ti,omap5430-timer"; 745 reg = <0x48034000 0x80>; 746 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 747 ti,hwmods = "timer3"; 748 }; 749 750 timer4: timer@48036000 { 751 compatible = "ti,omap5430-timer"; 752 reg = <0x48036000 0x80>; 753 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 754 ti,hwmods = "timer4"; 755 }; 756 757 timer5: timer@40138000 { 758 compatible = "ti,omap5430-timer"; 759 reg = <0x40138000 0x80>, 760 <0x49038000 0x80>; 761 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 762 ti,hwmods = "timer5"; 763 ti,timer-dsp; 764 ti,timer-pwm; 765 }; 766 767 timer6: timer@4013a000 { 768 compatible = "ti,omap5430-timer"; 769 reg = <0x4013a000 0x80>, 770 <0x4903a000 0x80>; 771 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 772 ti,hwmods = "timer6"; 773 ti,timer-dsp; 774 ti,timer-pwm; 775 }; 776 777 timer7: timer@4013c000 { 778 compatible = "ti,omap5430-timer"; 779 reg = <0x4013c000 0x80>, 780 <0x4903c000 0x80>; 781 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 782 ti,hwmods = "timer7"; 783 ti,timer-dsp; 784 }; 785 786 timer8: timer@4013e000 { 787 compatible = "ti,omap5430-timer"; 788 reg = <0x4013e000 0x80>, 789 <0x4903e000 0x80>; 790 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 791 ti,hwmods = "timer8"; 792 ti,timer-dsp; 793 ti,timer-pwm; 794 }; 795 796 timer9: timer@4803e000 { 797 compatible = "ti,omap5430-timer"; 798 reg = <0x4803e000 0x80>; 799 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 800 ti,hwmods = "timer9"; 801 ti,timer-pwm; 802 }; 803 804 timer10: timer@48086000 { 805 compatible = "ti,omap5430-timer"; 806 reg = <0x48086000 0x80>; 807 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 808 ti,hwmods = "timer10"; 809 ti,timer-pwm; 810 }; 811 812 timer11: timer@48088000 { 813 compatible = "ti,omap5430-timer"; 814 reg = <0x48088000 0x80>; 815 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 816 ti,hwmods = "timer11"; 817 ti,timer-pwm; 818 }; 819 820 wdt2: wdt@4ae14000 { 821 compatible = "ti,omap5-wdt", "ti,omap3-wdt"; 822 reg = <0x4ae14000 0x80>; 823 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 824 ti,hwmods = "wd_timer2"; 825 }; 826 827 dmm@4e000000 { 828 compatible = "ti,omap5-dmm"; 829 reg = <0x4e000000 0x800>; 830 interrupts = <0 113 0x4>; 831 ti,hwmods = "dmm"; 832 }; 833 834 emif1: emif@4c000000 { 835 compatible = "ti,emif-4d5"; 836 ti,hwmods = "emif1"; 837 ti,no-idle-on-init; 838 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 839 reg = <0x4c000000 0x400>; 840 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 841 hw-caps-read-idle-ctrl; 842 hw-caps-ll-interface; 843 hw-caps-temp-alert; 844 }; 845 846 emif2: emif@4d000000 { 847 compatible = "ti,emif-4d5"; 848 ti,hwmods = "emif2"; 849 ti,no-idle-on-init; 850 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 851 reg = <0x4d000000 0x400>; 852 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 853 hw-caps-read-idle-ctrl; 854 hw-caps-ll-interface; 855 hw-caps-temp-alert; 856 }; 857 858 omap_control_usb2phy: control-phy@4a002300 { 859 compatible = "ti,control-phy-usb2"; 860 reg = <0x4a002300 0x4>; 861 reg-names = "power"; 862 }; 863 864 omap_control_usb3phy: control-phy@4a002370 { 865 compatible = "ti,control-phy-pipe3"; 866 reg = <0x4a002370 0x4>; 867 reg-names = "power"; 868 }; 869 870 usb3: omap_dwc3@4a020000 { 871 compatible = "ti,dwc3"; 872 ti,hwmods = "usb_otg_ss"; 873 reg = <0x4a020000 0x10000>; 874 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 875 #address-cells = <1>; 876 #size-cells = <1>; 877 utmi-mode = <2>; 878 ranges; 879 dwc3@4a030000 { 880 compatible = "snps,dwc3"; 881 reg = <0x4a030000 0x10000>; 882 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 885 interrupt-names = "peripheral", 886 "host", 887 "otg"; 888 phys = <&usb2_phy>, <&usb3_phy>; 889 phy-names = "usb2-phy", "usb3-phy"; 890 dr_mode = "peripheral"; 891 tx-fifo-resize; 892 }; 893 }; 894 895 ocp2scp@4a080000 { 896 compatible = "ti,omap-ocp2scp"; 897 #address-cells = <1>; 898 #size-cells = <1>; 899 reg = <0x4a080000 0x20>; 900 ranges; 901 ti,hwmods = "ocp2scp1"; 902 usb2_phy: usb2phy@4a084000 { 903 compatible = "ti,omap-usb2"; 904 reg = <0x4a084000 0x7c>; 905 ctrl-module = <&omap_control_usb2phy>; 906 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; 907 clock-names = "wkupclk", "refclk"; 908 #phy-cells = <0>; 909 }; 910 911 usb3_phy: usb3phy@4a084400 { 912 compatible = "ti,omap-usb3"; 913 reg = <0x4a084400 0x80>, 914 <0x4a084800 0x64>, 915 <0x4a084c00 0x40>; 916 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 917 ctrl-module = <&omap_control_usb3phy>; 918 clocks = <&usb_phy_cm_clk32k>, 919 <&sys_clkin>, 920 <&usb_otg_ss_refclk960m>; 921 clock-names = "wkupclk", 922 "sysclk", 923 "refclk"; 924 #phy-cells = <0>; 925 }; 926 }; 927 928 usbhstll: usbhstll@4a062000 { 929 compatible = "ti,usbhs-tll"; 930 reg = <0x4a062000 0x1000>; 931 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 932 ti,hwmods = "usb_tll_hs"; 933 }; 934 935 usbhshost: usbhshost@4a064000 { 936 compatible = "ti,usbhs-host"; 937 reg = <0x4a064000 0x800>; 938 ti,hwmods = "usb_host_hs"; 939 #address-cells = <1>; 940 #size-cells = <1>; 941 ranges; 942 clocks = <&l3init_60m_fclk>, 943 <&xclk60mhsp1_ck>, 944 <&xclk60mhsp2_ck>; 945 clock-names = "refclk_60m_int", 946 "refclk_60m_ext_p1", 947 "refclk_60m_ext_p2"; 948 949 usbhsohci: ohci@4a064800 { 950 compatible = "ti,ohci-omap3"; 951 reg = <0x4a064800 0x400>; 952 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 953 }; 954 955 usbhsehci: ehci@4a064c00 { 956 compatible = "ti,ehci-omap"; 957 reg = <0x4a064c00 0x400>; 958 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 959 }; 960 }; 961 962 bandgap: bandgap@4a0021e0 { 963 reg = <0x4a0021e0 0xc 964 0x4a00232c 0xc 965 0x4a002380 0x2c 966 0x4a0023C0 0x3c>; 967 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 968 compatible = "ti,omap5430-bandgap"; 969 970 #thermal-sensor-cells = <1>; 971 }; 972 973 omap_control_sata: control-phy@4a002374 { 974 compatible = "ti,control-phy-pipe3"; 975 reg = <0x4a002374 0x4>; 976 reg-names = "power"; 977 clocks = <&sys_clkin>; 978 clock-names = "sysclk"; 979 }; 980 981 /* OCP2SCP3 */ 982 ocp2scp@4a090000 { 983 compatible = "ti,omap-ocp2scp"; 984 #address-cells = <1>; 985 #size-cells = <1>; 986 reg = <0x4a090000 0x20>; 987 ranges; 988 ti,hwmods = "ocp2scp3"; 989 sata_phy: phy@4a096000 { 990 compatible = "ti,phy-pipe3-sata"; 991 reg = <0x4A096000 0x80>, /* phy_rx */ 992 <0x4A096400 0x64>, /* phy_tx */ 993 <0x4A096800 0x40>; /* pll_ctrl */ 994 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 995 ctrl-module = <&omap_control_sata>; 996 clocks = <&sys_clkin>, <&sata_ref_clk>; 997 clock-names = "sysclk", "refclk"; 998 #phy-cells = <0>; 999 }; 1000 }; 1001 1002 sata: sata@4a141100 { 1003 compatible = "snps,dwc-ahci"; 1004 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1005 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1006 phys = <&sata_phy>; 1007 phy-names = "sata-phy"; 1008 clocks = <&sata_ref_clk>; 1009 ti,hwmods = "sata"; 1010 }; 1011 1012 dss: dss@58000000 { 1013 compatible = "ti,omap5-dss"; 1014 reg = <0x58000000 0x80>; 1015 status = "disabled"; 1016 ti,hwmods = "dss_core"; 1017 clocks = <&dss_dss_clk>; 1018 clock-names = "fck"; 1019 #address-cells = <1>; 1020 #size-cells = <1>; 1021 ranges; 1022 1023 dispc@58001000 { 1024 compatible = "ti,omap5-dispc"; 1025 reg = <0x58001000 0x1000>; 1026 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1027 ti,hwmods = "dss_dispc"; 1028 clocks = <&dss_dss_clk>; 1029 clock-names = "fck"; 1030 }; 1031 1032 rfbi: encoder@58002000 { 1033 compatible = "ti,omap5-rfbi"; 1034 reg = <0x58002000 0x100>; 1035 status = "disabled"; 1036 ti,hwmods = "dss_rfbi"; 1037 clocks = <&dss_dss_clk>, <&l3_iclk_div>; 1038 clock-names = "fck", "ick"; 1039 }; 1040 1041 dsi1: encoder@58004000 { 1042 compatible = "ti,omap5-dsi"; 1043 reg = <0x58004000 0x200>, 1044 <0x58004200 0x40>, 1045 <0x58004300 0x40>; 1046 reg-names = "proto", "phy", "pll"; 1047 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1048 status = "disabled"; 1049 ti,hwmods = "dss_dsi1"; 1050 clocks = <&dss_dss_clk>, <&dss_sys_clk>; 1051 clock-names = "fck", "sys_clk"; 1052 }; 1053 1054 dsi2: encoder@58005000 { 1055 compatible = "ti,omap5-dsi"; 1056 reg = <0x58009000 0x200>, 1057 <0x58009200 0x40>, 1058 <0x58009300 0x40>; 1059 reg-names = "proto", "phy", "pll"; 1060 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1061 status = "disabled"; 1062 ti,hwmods = "dss_dsi2"; 1063 clocks = <&dss_dss_clk>, <&dss_sys_clk>; 1064 clock-names = "fck", "sys_clk"; 1065 }; 1066 1067 hdmi: encoder@58060000 { 1068 compatible = "ti,omap5-hdmi"; 1069 reg = <0x58040000 0x200>, 1070 <0x58040200 0x80>, 1071 <0x58040300 0x80>, 1072 <0x58060000 0x19000>; 1073 reg-names = "wp", "pll", "phy", "core"; 1074 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1075 status = "disabled"; 1076 ti,hwmods = "dss_hdmi"; 1077 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; 1078 clock-names = "fck", "sys_clk"; 1079 dmas = <&sdma 76>; 1080 dma-names = "audio_tx"; 1081 }; 1082 }; 1083 1084 abb_mpu: regulator-abb-mpu { 1085 compatible = "ti,abb-v2"; 1086 regulator-name = "abb_mpu"; 1087 #address-cells = <0>; 1088 #size-cells = <0>; 1089 clocks = <&sys_clkin>; 1090 ti,settling-time = <50>; 1091 ti,clock-cycles = <16>; 1092 1093 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, 1094 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; 1095 reg-names = "base-address", "int-address", 1096 "efuse-address", "ldo-address"; 1097 ti,tranxdone-status-mask = <0x80>; 1098 /* LDOVBBMPU_MUX_CTRL */ 1099 ti,ldovbb-override-mask = <0x400>; 1100 /* LDOVBBMPU_VSET_OUT */ 1101 ti,ldovbb-vset-mask = <0x1F>; 1102 1103 /* 1104 * NOTE: only FBB mode used but actual vset will 1105 * determine final biasing 1106 */ 1107 ti,abb_info = < 1108 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1109 1060000 0 0x0 0 0x02000000 0x01F00000 1110 1250000 0 0x4 0 0x02000000 0x01F00000 1111 >; 1112 }; 1113 1114 abb_mm: regulator-abb-mm { 1115 compatible = "ti,abb-v2"; 1116 regulator-name = "abb_mm"; 1117 #address-cells = <0>; 1118 #size-cells = <0>; 1119 clocks = <&sys_clkin>; 1120 ti,settling-time = <50>; 1121 ti,clock-cycles = <16>; 1122 1123 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, 1124 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; 1125 reg-names = "base-address", "int-address", 1126 "efuse-address", "ldo-address"; 1127 ti,tranxdone-status-mask = <0x80000000>; 1128 /* LDOVBBMM_MUX_CTRL */ 1129 ti,ldovbb-override-mask = <0x400>; 1130 /* LDOVBBMM_VSET_OUT */ 1131 ti,ldovbb-vset-mask = <0x1F>; 1132 1133 /* 1134 * NOTE: only FBB mode used but actual vset will 1135 * determine final biasing 1136 */ 1137 ti,abb_info = < 1138 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1139 1025000 0 0x0 0 0x02000000 0x01F00000 1140 1120000 0 0x4 0 0x02000000 0x01F00000 1141 >; 1142 }; 1143 }; 1144}; 1145 1146&cpu_thermal { 1147 polling-delay = <500>; /* milliseconds */ 1148}; 1149 1150/include/ "omap54xx-clocks.dtsi" 1151