1/* 2 * Device Tree Source for the r7s72100 SoC 3 * 4 * Copyright (C) 2013-14 Renesas Solutions Corp. 5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/r7s72100-clock.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14 15/ { 16 compatible = "renesas,r7s72100"; 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 aliases { 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 spi0 = &spi0; 27 spi1 = &spi1; 28 spi2 = &spi2; 29 spi3 = &spi3; 30 spi4 = &spi4; 31 }; 32 33 clocks { 34 ranges; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 /* External clocks */ 39 extal_clk: extal_clk { 40 #clock-cells = <0>; 41 compatible = "fixed-clock"; 42 /* If clk present, value must be set by board */ 43 clock-frequency = <0>; 44 clock-output-names = "extal"; 45 }; 46 47 usb_x1_clk: usb_x1_clk { 48 #clock-cells = <0>; 49 compatible = "fixed-clock"; 50 /* If clk present, value must be set by board */ 51 clock-frequency = <0>; 52 clock-output-names = "usb_x1"; 53 }; 54 55 /* Fixed factor clocks */ 56 b_clk: b_clk { 57 #clock-cells = <0>; 58 compatible = "fixed-factor-clock"; 59 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 60 clock-mult = <1>; 61 clock-div = <3>; 62 clock-output-names = "b"; 63 }; 64 p1_clk: p1_clk { 65 #clock-cells = <0>; 66 compatible = "fixed-factor-clock"; 67 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 68 clock-mult = <1>; 69 clock-div = <6>; 70 clock-output-names = "p1"; 71 }; 72 p0_clk: p0_clk { 73 #clock-cells = <0>; 74 compatible = "fixed-factor-clock"; 75 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 76 clock-mult = <1>; 77 clock-div = <12>; 78 clock-output-names = "p0"; 79 }; 80 81 /* Special CPG clocks */ 82 cpg_clocks: cpg_clocks@fcfe0000 { 83 #clock-cells = <1>; 84 compatible = "renesas,r7s72100-cpg-clocks", 85 "renesas,rz-cpg-clocks"; 86 reg = <0xfcfe0000 0x18>; 87 clocks = <&extal_clk>, <&usb_x1_clk>; 88 clock-output-names = "pll", "i", "g"; 89 #power-domain-cells = <0>; 90 }; 91 92 /* MSTP clocks */ 93 mstp3_clks: mstp3_clks@fcfe0420 { 94 #clock-cells = <1>; 95 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 96 reg = <0xfcfe0420 4>; 97 clocks = <&p0_clk>; 98 clock-indices = <R7S72100_CLK_MTU2>; 99 clock-output-names = "mtu2"; 100 }; 101 102 mstp4_clks: mstp4_clks@fcfe0424 { 103 #clock-cells = <1>; 104 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 105 reg = <0xfcfe0424 4>; 106 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 107 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; 108 clock-indices = < 109 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 110 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 111 >; 112 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; 113 }; 114 115 mstp9_clks: mstp9_clks@fcfe0438 { 116 #clock-cells = <1>; 117 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 118 reg = <0xfcfe0438 4>; 119 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; 120 clock-indices = < 121 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 122 >; 123 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; 124 }; 125 126 mstp10_clks: mstp10_clks@fcfe043c { 127 #clock-cells = <1>; 128 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 129 reg = <0xfcfe043c 4>; 130 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, 131 <&p1_clk>; 132 clock-indices = < 133 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 134 R7S72100_CLK_SPI4 135 >; 136 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; 137 }; 138 }; 139 140 cpus { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 cpu@0 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a9"; 147 reg = <0>; 148 clock-frequency = <400000000>; 149 }; 150 }; 151 152 scif0: serial@e8007000 { 153 compatible = "renesas,scif-r7s72100", "renesas,scif"; 154 reg = <0xe8007000 64>; 155 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>, 156 <0 191 IRQ_TYPE_LEVEL_HIGH>, 157 <0 192 IRQ_TYPE_LEVEL_HIGH>, 158 <0 189 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; 160 clock-names = "sci_ick"; 161 power-domains = <&cpg_clocks>; 162 status = "disabled"; 163 }; 164 165 scif1: serial@e8007800 { 166 compatible = "renesas,scif-r7s72100", "renesas,scif"; 167 reg = <0xe8007800 64>; 168 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>, 169 <0 195 IRQ_TYPE_LEVEL_HIGH>, 170 <0 196 IRQ_TYPE_LEVEL_HIGH>, 171 <0 193 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; 173 clock-names = "sci_ick"; 174 power-domains = <&cpg_clocks>; 175 status = "disabled"; 176 }; 177 178 scif2: serial@e8008000 { 179 compatible = "renesas,scif-r7s72100", "renesas,scif"; 180 reg = <0xe8008000 64>; 181 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, 182 <0 199 IRQ_TYPE_LEVEL_HIGH>, 183 <0 200 IRQ_TYPE_LEVEL_HIGH>, 184 <0 197 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; 186 clock-names = "sci_ick"; 187 power-domains = <&cpg_clocks>; 188 status = "disabled"; 189 }; 190 191 scif3: serial@e8008800 { 192 compatible = "renesas,scif-r7s72100", "renesas,scif"; 193 reg = <0xe8008800 64>; 194 interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>, 195 <0 203 IRQ_TYPE_LEVEL_HIGH>, 196 <0 204 IRQ_TYPE_LEVEL_HIGH>, 197 <0 201 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; 199 clock-names = "sci_ick"; 200 power-domains = <&cpg_clocks>; 201 status = "disabled"; 202 }; 203 204 scif4: serial@e8009000 { 205 compatible = "renesas,scif-r7s72100", "renesas,scif"; 206 reg = <0xe8009000 64>; 207 interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>, 208 <0 207 IRQ_TYPE_LEVEL_HIGH>, 209 <0 208 IRQ_TYPE_LEVEL_HIGH>, 210 <0 205 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; 212 clock-names = "sci_ick"; 213 power-domains = <&cpg_clocks>; 214 status = "disabled"; 215 }; 216 217 scif5: serial@e8009800 { 218 compatible = "renesas,scif-r7s72100", "renesas,scif"; 219 reg = <0xe8009800 64>; 220 interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>, 221 <0 211 IRQ_TYPE_LEVEL_HIGH>, 222 <0 212 IRQ_TYPE_LEVEL_HIGH>, 223 <0 209 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; 225 clock-names = "sci_ick"; 226 power-domains = <&cpg_clocks>; 227 status = "disabled"; 228 }; 229 230 scif6: serial@e800a000 { 231 compatible = "renesas,scif-r7s72100", "renesas,scif"; 232 reg = <0xe800a000 64>; 233 interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>, 234 <0 215 IRQ_TYPE_LEVEL_HIGH>, 235 <0 216 IRQ_TYPE_LEVEL_HIGH>, 236 <0 213 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; 238 clock-names = "sci_ick"; 239 power-domains = <&cpg_clocks>; 240 status = "disabled"; 241 }; 242 243 scif7: serial@e800a800 { 244 compatible = "renesas,scif-r7s72100", "renesas,scif"; 245 reg = <0xe800a800 64>; 246 interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>, 247 <0 219 IRQ_TYPE_LEVEL_HIGH>, 248 <0 220 IRQ_TYPE_LEVEL_HIGH>, 249 <0 217 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; 251 clock-names = "sci_ick"; 252 power-domains = <&cpg_clocks>; 253 status = "disabled"; 254 }; 255 256 spi0: spi@e800c800 { 257 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 258 reg = <0xe800c800 0x24>; 259 interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>, 260 <0 239 IRQ_TYPE_LEVEL_HIGH>, 261 <0 240 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-names = "error", "rx", "tx"; 263 clocks = <&mstp10_clks R7S72100_CLK_SPI0>; 264 power-domains = <&cpg_clocks>; 265 num-cs = <1>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 spi1: spi@e800d000 { 272 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 273 reg = <0xe800d000 0x24>; 274 interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>, 275 <0 242 IRQ_TYPE_LEVEL_HIGH>, 276 <0 243 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "error", "rx", "tx"; 278 clocks = <&mstp10_clks R7S72100_CLK_SPI1>; 279 power-domains = <&cpg_clocks>; 280 num-cs = <1>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 spi2: spi@e800d800 { 287 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 288 reg = <0xe800d800 0x24>; 289 interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>, 290 <0 245 IRQ_TYPE_LEVEL_HIGH>, 291 <0 246 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-names = "error", "rx", "tx"; 293 clocks = <&mstp10_clks R7S72100_CLK_SPI2>; 294 power-domains = <&cpg_clocks>; 295 num-cs = <1>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 status = "disabled"; 299 }; 300 301 spi3: spi@e800e000 { 302 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 303 reg = <0xe800e000 0x24>; 304 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>, 305 <0 248 IRQ_TYPE_LEVEL_HIGH>, 306 <0 249 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-names = "error", "rx", "tx"; 308 clocks = <&mstp10_clks R7S72100_CLK_SPI3>; 309 power-domains = <&cpg_clocks>; 310 num-cs = <1>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 status = "disabled"; 314 }; 315 316 spi4: spi@e800e800 { 317 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; 318 reg = <0xe800e800 0x24>; 319 interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>, 320 <0 251 IRQ_TYPE_LEVEL_HIGH>, 321 <0 252 IRQ_TYPE_LEVEL_HIGH>; 322 interrupt-names = "error", "rx", "tx"; 323 clocks = <&mstp10_clks R7S72100_CLK_SPI4>; 324 power-domains = <&cpg_clocks>; 325 num-cs = <1>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 gic: interrupt-controller@e8201000 { 332 compatible = "arm,cortex-a9-gic"; 333 #interrupt-cells = <3>; 334 #address-cells = <0>; 335 interrupt-controller; 336 reg = <0xe8201000 0x1000>, 337 <0xe8202000 0x1000>; 338 }; 339 340 i2c0: i2c@fcfee000 { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 344 reg = <0xfcfee000 0x44>; 345 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, 346 <0 158 IRQ_TYPE_EDGE_RISING>, 347 <0 159 IRQ_TYPE_EDGE_RISING>, 348 <0 160 IRQ_TYPE_LEVEL_HIGH>, 349 <0 161 IRQ_TYPE_LEVEL_HIGH>, 350 <0 162 IRQ_TYPE_LEVEL_HIGH>, 351 <0 163 IRQ_TYPE_LEVEL_HIGH>, 352 <0 164 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&mstp9_clks R7S72100_CLK_I2C0>; 354 clock-frequency = <100000>; 355 power-domains = <&cpg_clocks>; 356 status = "disabled"; 357 }; 358 359 i2c1: i2c@fcfee400 { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 363 reg = <0xfcfee400 0x44>; 364 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>, 365 <0 166 IRQ_TYPE_EDGE_RISING>, 366 <0 167 IRQ_TYPE_EDGE_RISING>, 367 <0 168 IRQ_TYPE_LEVEL_HIGH>, 368 <0 169 IRQ_TYPE_LEVEL_HIGH>, 369 <0 170 IRQ_TYPE_LEVEL_HIGH>, 370 <0 171 IRQ_TYPE_LEVEL_HIGH>, 371 <0 172 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&mstp9_clks R7S72100_CLK_I2C1>; 373 clock-frequency = <100000>; 374 power-domains = <&cpg_clocks>; 375 status = "disabled"; 376 }; 377 378 i2c2: i2c@fcfee800 { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 382 reg = <0xfcfee800 0x44>; 383 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>, 384 <0 174 IRQ_TYPE_EDGE_RISING>, 385 <0 175 IRQ_TYPE_EDGE_RISING>, 386 <0 176 IRQ_TYPE_LEVEL_HIGH>, 387 <0 177 IRQ_TYPE_LEVEL_HIGH>, 388 <0 178 IRQ_TYPE_LEVEL_HIGH>, 389 <0 179 IRQ_TYPE_LEVEL_HIGH>, 390 <0 180 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&mstp9_clks R7S72100_CLK_I2C2>; 392 clock-frequency = <100000>; 393 power-domains = <&cpg_clocks>; 394 status = "disabled"; 395 }; 396 397 i2c3: i2c@fcfeec00 { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; 401 reg = <0xfcfeec00 0x44>; 402 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>, 403 <0 182 IRQ_TYPE_EDGE_RISING>, 404 <0 183 IRQ_TYPE_EDGE_RISING>, 405 <0 184 IRQ_TYPE_LEVEL_HIGH>, 406 <0 185 IRQ_TYPE_LEVEL_HIGH>, 407 <0 186 IRQ_TYPE_LEVEL_HIGH>, 408 <0 187 IRQ_TYPE_LEVEL_HIGH>, 409 <0 188 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&mstp9_clks R7S72100_CLK_I2C3>; 411 clock-frequency = <100000>; 412 power-domains = <&cpg_clocks>; 413 status = "disabled"; 414 }; 415 416 mtu2: timer@fcff0000 { 417 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; 418 reg = <0xfcff0000 0x400>; 419 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 420 interrupt-names = "tgi0a"; 421 clocks = <&mstp3_clks R7S72100_CLK_MTU2>; 422 clock-names = "fck"; 423 power-domains = <&cpg_clocks>; 424 status = "disabled"; 425 }; 426}; 427