1/* 2 * Device Tree Source for Renesas r8a7778 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * based on r8a7779 8 * 9 * Copyright (C) 2013 Renesas Solutions Corp. 10 * Copyright (C) 2013 Simon Horman 11 * 12 * This file is licensed under the terms of the GNU General Public License 13 * version 2. This program is licensed "as is" without any warranty of any 14 * kind, whether express or implied. 15 */ 16 17/include/ "skeleton.dtsi" 18 19#include <dt-bindings/clock/r8a7778-clock.h> 20#include <dt-bindings/interrupt-controller/irq.h> 21 22/ { 23 compatible = "renesas,r8a7778"; 24 interrupt-parent = <&gic>; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a9"; 33 reg = <0>; 34 clock-frequency = <800000000>; 35 }; 36 }; 37 38 aliases { 39 spi0 = &hspi0; 40 spi1 = &hspi1; 41 spi2 = &hspi2; 42 }; 43 44 bsc: bus@1c000000 { 45 compatible = "simple-bus"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0 0 0x1c000000>; 49 }; 50 51 ether: ethernet@fde00000 { 52 compatible = "renesas,ether-r8a7778"; 53 reg = <0xfde00000 0x400>; 54 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>; 56 power-domains = <&cpg_clocks>; 57 phy-mode = "rmii"; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 status = "disabled"; 61 }; 62 63 gic: interrupt-controller@fe438000 { 64 compatible = "arm,cortex-a9-gic"; 65 #interrupt-cells = <3>; 66 interrupt-controller; 67 reg = <0xfe438000 0x1000>, 68 <0xfe430000 0x100>; 69 }; 70 71 /* irqpin: IRQ0 - IRQ3 */ 72 irqpin: interrupt-controller@fe78001c { 73 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; 74 #interrupt-cells = <2>; 75 interrupt-controller; 76 status = "disabled"; /* default off */ 77 reg = <0xfe78001c 4>, 78 <0xfe780010 4>, 79 <0xfe780024 4>, 80 <0xfe780044 4>, 81 <0xfe780064 4>; 82 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 83 0 28 IRQ_TYPE_LEVEL_HIGH 84 0 29 IRQ_TYPE_LEVEL_HIGH 85 0 30 IRQ_TYPE_LEVEL_HIGH>; 86 sense-bitfield-width = <2>; 87 }; 88 89 gpio0: gpio@ffc40000 { 90 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 91 reg = <0xffc40000 0x2c>; 92 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 93 #gpio-cells = <2>; 94 gpio-controller; 95 gpio-ranges = <&pfc 0 0 32>; 96 #interrupt-cells = <2>; 97 interrupt-controller; 98 }; 99 100 gpio1: gpio@ffc41000 { 101 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 102 reg = <0xffc41000 0x2c>; 103 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 104 #gpio-cells = <2>; 105 gpio-controller; 106 gpio-ranges = <&pfc 0 32 32>; 107 #interrupt-cells = <2>; 108 interrupt-controller; 109 }; 110 111 gpio2: gpio@ffc42000 { 112 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 113 reg = <0xffc42000 0x2c>; 114 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 115 #gpio-cells = <2>; 116 gpio-controller; 117 gpio-ranges = <&pfc 0 64 32>; 118 #interrupt-cells = <2>; 119 interrupt-controller; 120 }; 121 122 gpio3: gpio@ffc43000 { 123 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 124 reg = <0xffc43000 0x2c>; 125 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 126 #gpio-cells = <2>; 127 gpio-controller; 128 gpio-ranges = <&pfc 0 96 32>; 129 #interrupt-cells = <2>; 130 interrupt-controller; 131 }; 132 133 gpio4: gpio@ffc44000 { 134 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 135 reg = <0xffc44000 0x2c>; 136 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; 137 #gpio-cells = <2>; 138 gpio-controller; 139 gpio-ranges = <&pfc 0 128 27>; 140 #interrupt-cells = <2>; 141 interrupt-controller; 142 }; 143 144 pfc: pfc@fffc0000 { 145 compatible = "renesas,pfc-r8a7778"; 146 reg = <0xfffc0000 0x118>; 147 }; 148 149 i2c0: i2c@ffc70000 { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 compatible = "renesas,i2c-r8a7778"; 153 reg = <0xffc70000 0x1000>; 154 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&mstp0_clks R8A7778_CLK_I2C0>; 156 power-domains = <&cpg_clocks>; 157 status = "disabled"; 158 }; 159 160 i2c1: i2c@ffc71000 { 161 #address-cells = <1>; 162 #size-cells = <0>; 163 compatible = "renesas,i2c-r8a7778"; 164 reg = <0xffc71000 0x1000>; 165 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&mstp0_clks R8A7778_CLK_I2C1>; 167 power-domains = <&cpg_clocks>; 168 status = "disabled"; 169 }; 170 171 i2c2: i2c@ffc72000 { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 compatible = "renesas,i2c-r8a7778"; 175 reg = <0xffc72000 0x1000>; 176 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&mstp0_clks R8A7778_CLK_I2C2>; 178 power-domains = <&cpg_clocks>; 179 status = "disabled"; 180 }; 181 182 i2c3: i2c@ffc73000 { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 compatible = "renesas,i2c-r8a7778"; 186 reg = <0xffc73000 0x1000>; 187 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&mstp0_clks R8A7778_CLK_I2C3>; 189 power-domains = <&cpg_clocks>; 190 status = "disabled"; 191 }; 192 193 tmu0: timer@ffd80000 { 194 compatible = "renesas,tmu-r8a7778", "renesas,tmu"; 195 reg = <0xffd80000 0x30>; 196 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 197 <0 33 IRQ_TYPE_LEVEL_HIGH>, 198 <0 34 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&mstp0_clks R8A7778_CLK_TMU0>; 200 clock-names = "fck"; 201 power-domains = <&cpg_clocks>; 202 203 #renesas,channels = <3>; 204 205 status = "disabled"; 206 }; 207 208 tmu1: timer@ffd81000 { 209 compatible = "renesas,tmu-r8a7778", "renesas,tmu"; 210 reg = <0xffd81000 0x30>; 211 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 212 <0 37 IRQ_TYPE_LEVEL_HIGH>, 213 <0 38 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&mstp0_clks R8A7778_CLK_TMU1>; 215 clock-names = "fck"; 216 power-domains = <&cpg_clocks>; 217 218 #renesas,channels = <3>; 219 220 status = "disabled"; 221 }; 222 223 tmu2: timer@ffd82000 { 224 compatible = "renesas,tmu-r8a7778", "renesas,tmu"; 225 reg = <0xffd82000 0x30>; 226 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 227 <0 41 IRQ_TYPE_LEVEL_HIGH>, 228 <0 42 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&mstp0_clks R8A7778_CLK_TMU2>; 230 clock-names = "fck"; 231 power-domains = <&cpg_clocks>; 232 233 #renesas,channels = <3>; 234 235 status = "disabled"; 236 }; 237 238 rcar_sound: sound@ffd90000 { 239 #sound-dai-cells = <1>; 240 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1"; 241 reg = <0xffd90000 0x1000>, /* SRU */ 242 <0xffd91000 0x240>, /* SSI */ 243 <0xfffe0000 0x24>; /* ADG */ 244 clocks = <&mstp3_clks R8A7778_CLK_SSI8>, 245 <&mstp3_clks R8A7778_CLK_SSI7>, 246 <&mstp3_clks R8A7778_CLK_SSI6>, 247 <&mstp3_clks R8A7778_CLK_SSI5>, 248 <&mstp3_clks R8A7778_CLK_SSI4>, 249 <&mstp0_clks R8A7778_CLK_SSI3>, 250 <&mstp0_clks R8A7778_CLK_SSI2>, 251 <&mstp0_clks R8A7778_CLK_SSI1>, 252 <&mstp0_clks R8A7778_CLK_SSI0>, 253 <&mstp5_clks R8A7778_CLK_SRU_SRC8>, 254 <&mstp5_clks R8A7778_CLK_SRU_SRC7>, 255 <&mstp5_clks R8A7778_CLK_SRU_SRC6>, 256 <&mstp5_clks R8A7778_CLK_SRU_SRC5>, 257 <&mstp5_clks R8A7778_CLK_SRU_SRC4>, 258 <&mstp5_clks R8A7778_CLK_SRU_SRC3>, 259 <&mstp5_clks R8A7778_CLK_SRU_SRC2>, 260 <&mstp5_clks R8A7778_CLK_SRU_SRC1>, 261 <&mstp5_clks R8A7778_CLK_SRU_SRC0>, 262 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, 263 <&cpg_clocks R8A7778_CLK_S1>; 264 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", 265 "ssi.3", "ssi.2", "ssi.1", "ssi.0", 266 "src.8", "src.7", "src.6", "src.5", "src.4", 267 "src.3", "src.2", "src.1", "src.0", 268 "clk_a", "clk_b", "clk_c", "clk_i"; 269 270 status = "disabled"; 271 272 rcar_sound,src { 273 src3: src@3 { }; 274 src4: src@4 { }; 275 src5: src@5 { }; 276 src6: src@6 { }; 277 src7: src@7 { }; 278 src8: src@8 { }; 279 src9: src@9 { }; 280 }; 281 282 rcar_sound,ssi { 283 ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; 284 ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; 285 ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 286 ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 287 ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 288 ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 289 ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; 290 }; 291 }; 292 293 scif0: serial@ffe40000 { 294 compatible = "renesas,scif-r8a7778", "renesas,scif"; 295 reg = <0xffe40000 0x100>; 296 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>; 298 clock-names = "sci_ick"; 299 power-domains = <&cpg_clocks>; 300 status = "disabled"; 301 }; 302 303 scif1: serial@ffe41000 { 304 compatible = "renesas,scif-r8a7778", "renesas,scif"; 305 reg = <0xffe41000 0x100>; 306 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>; 308 clock-names = "sci_ick"; 309 power-domains = <&cpg_clocks>; 310 status = "disabled"; 311 }; 312 313 scif2: serial@ffe42000 { 314 compatible = "renesas,scif-r8a7778", "renesas,scif"; 315 reg = <0xffe42000 0x100>; 316 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>; 318 clock-names = "sci_ick"; 319 power-domains = <&cpg_clocks>; 320 status = "disabled"; 321 }; 322 323 scif3: serial@ffe43000 { 324 compatible = "renesas,scif-r8a7778", "renesas,scif"; 325 reg = <0xffe43000 0x100>; 326 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>; 328 clock-names = "sci_ick"; 329 power-domains = <&cpg_clocks>; 330 status = "disabled"; 331 }; 332 333 scif4: serial@ffe44000 { 334 compatible = "renesas,scif-r8a7778", "renesas,scif"; 335 reg = <0xffe44000 0x100>; 336 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>; 338 clock-names = "sci_ick"; 339 power-domains = <&cpg_clocks>; 340 status = "disabled"; 341 }; 342 343 scif5: serial@ffe45000 { 344 compatible = "renesas,scif-r8a7778", "renesas,scif"; 345 reg = <0xffe45000 0x100>; 346 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>; 348 clock-names = "sci_ick"; 349 power-domains = <&cpg_clocks>; 350 status = "disabled"; 351 }; 352 353 mmcif: mmc@ffe4e000 { 354 compatible = "renesas,sh-mmcif"; 355 reg = <0xffe4e000 0x100>; 356 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&mstp3_clks R8A7778_CLK_MMC>; 358 power-domains = <&cpg_clocks>; 359 status = "disabled"; 360 }; 361 362 sdhi0: sd@ffe4c000 { 363 compatible = "renesas,sdhi-r8a7778"; 364 reg = <0xffe4c000 0x100>; 365 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; 367 power-domains = <&cpg_clocks>; 368 status = "disabled"; 369 }; 370 371 sdhi1: sd@ffe4d000 { 372 compatible = "renesas,sdhi-r8a7778"; 373 reg = <0xffe4d000 0x100>; 374 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; 376 power-domains = <&cpg_clocks>; 377 status = "disabled"; 378 }; 379 380 sdhi2: sd@ffe4f000 { 381 compatible = "renesas,sdhi-r8a7778"; 382 reg = <0xffe4f000 0x100>; 383 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; 385 power-domains = <&cpg_clocks>; 386 status = "disabled"; 387 }; 388 389 hspi0: spi@fffc7000 { 390 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 391 reg = <0xfffc7000 0x18>; 392 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&mstp0_clks R8A7778_CLK_HSPI>; 394 power-domains = <&cpg_clocks>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 status = "disabled"; 398 }; 399 400 hspi1: spi@fffc8000 { 401 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 402 reg = <0xfffc8000 0x18>; 403 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&mstp0_clks R8A7778_CLK_HSPI>; 405 power-domains = <&cpg_clocks>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 status = "disabled"; 409 }; 410 411 hspi2: spi@fffc6000 { 412 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 413 reg = <0xfffc6000 0x18>; 414 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&mstp0_clks R8A7778_CLK_HSPI>; 416 power-domains = <&cpg_clocks>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 status = "disabled"; 420 }; 421 422 clocks { 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges; 426 427 /* External input clock */ 428 extal_clk: extal_clk { 429 compatible = "fixed-clock"; 430 #clock-cells = <0>; 431 clock-frequency = <0>; 432 clock-output-names = "extal"; 433 }; 434 435 /* Special CPG clocks */ 436 cpg_clocks: cpg_clocks@ffc80000 { 437 compatible = "renesas,r8a7778-cpg-clocks"; 438 reg = <0xffc80000 0x80>; 439 #clock-cells = <1>; 440 clocks = <&extal_clk>; 441 clock-output-names = "plla", "pllb", "b", 442 "out", "p", "s", "s1"; 443 #power-domain-cells = <0>; 444 }; 445 446 /* Audio clocks; frequencies are set by boards if applicable. */ 447 audio_clk_a: audio_clk_a { 448 compatible = "fixed-clock"; 449 #clock-cells = <0>; 450 clock-output-names = "audio_clk_a"; 451 }; 452 audio_clk_b: audio_clk_b { 453 compatible = "fixed-clock"; 454 #clock-cells = <0>; 455 clock-output-names = "audio_clk_b"; 456 }; 457 audio_clk_c: audio_clk_c { 458 compatible = "fixed-clock"; 459 #clock-cells = <0>; 460 clock-output-names = "audio_clk_c"; 461 }; 462 463 /* Fixed ratio clocks */ 464 g_clk: g_clk { 465 compatible = "fixed-factor-clock"; 466 clocks = <&cpg_clocks R8A7778_CLK_PLLA>; 467 #clock-cells = <0>; 468 clock-div = <12>; 469 clock-mult = <1>; 470 clock-output-names = "g"; 471 }; 472 i_clk: i_clk { 473 compatible = "fixed-factor-clock"; 474 clocks = <&cpg_clocks R8A7778_CLK_PLLA>; 475 #clock-cells = <0>; 476 clock-div = <1>; 477 clock-mult = <1>; 478 clock-output-names = "i"; 479 }; 480 s3_clk: s3_clk { 481 compatible = "fixed-factor-clock"; 482 clocks = <&cpg_clocks R8A7778_CLK_PLLA>; 483 #clock-cells = <0>; 484 clock-div = <4>; 485 clock-mult = <1>; 486 clock-output-names = "s3"; 487 }; 488 s4_clk: s4_clk { 489 compatible = "fixed-factor-clock"; 490 clocks = <&cpg_clocks R8A7778_CLK_PLLA>; 491 #clock-cells = <0>; 492 clock-div = <8>; 493 clock-mult = <1>; 494 clock-output-names = "s4"; 495 }; 496 z_clk: z_clk { 497 compatible = "fixed-factor-clock"; 498 clocks = <&cpg_clocks R8A7778_CLK_PLLB>; 499 #clock-cells = <0>; 500 clock-div = <1>; 501 clock-mult = <1>; 502 clock-output-names = "z"; 503 }; 504 505 /* Gate clocks */ 506 mstp0_clks: mstp0_clks@ffc80030 { 507 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; 508 reg = <0xffc80030 4>; 509 clocks = <&cpg_clocks R8A7778_CLK_P>, 510 <&cpg_clocks R8A7778_CLK_P>, 511 <&cpg_clocks R8A7778_CLK_P>, 512 <&cpg_clocks R8A7778_CLK_P>, 513 <&cpg_clocks R8A7778_CLK_P>, 514 <&cpg_clocks R8A7778_CLK_P>, 515 <&cpg_clocks R8A7778_CLK_P>, 516 <&cpg_clocks R8A7778_CLK_P>, 517 <&cpg_clocks R8A7778_CLK_P>, 518 <&cpg_clocks R8A7778_CLK_P>, 519 <&cpg_clocks R8A7778_CLK_P>, 520 <&cpg_clocks R8A7778_CLK_P>, 521 <&cpg_clocks R8A7778_CLK_P>, 522 <&cpg_clocks R8A7778_CLK_P>, 523 <&cpg_clocks R8A7778_CLK_P>, 524 <&cpg_clocks R8A7778_CLK_P>, 525 <&cpg_clocks R8A7778_CLK_P>, 526 <&cpg_clocks R8A7778_CLK_P>, 527 <&cpg_clocks R8A7778_CLK_S>; 528 #clock-cells = <1>; 529 clock-indices = < 530 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1 531 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3 532 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1 533 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3 534 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5 535 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1 536 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0 537 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2 538 R8A7778_CLK_SSI3 R8A7778_CLK_SRU 539 R8A7778_CLK_HSPI 540 >; 541 clock-output-names = 542 "i2c0", "i2c1", "i2c2", "i2c3", "scif0", 543 "scif1", "scif2", "scif3", "scif4", "scif5", 544 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1", 545 "ssi2", "ssi3", "sru", "hspi"; 546 }; 547 mstp1_clks: mstp1_clks@ffc80034 { 548 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; 549 reg = <0xffc80034 4>, <0xffc80044 4>; 550 clocks = <&cpg_clocks R8A7778_CLK_P>, 551 <&cpg_clocks R8A7778_CLK_S>, 552 <&cpg_clocks R8A7778_CLK_S>, 553 <&cpg_clocks R8A7778_CLK_P>; 554 #clock-cells = <1>; 555 clock-indices = < 556 R8A7778_CLK_ETHER R8A7778_CLK_VIN0 557 R8A7778_CLK_VIN1 R8A7778_CLK_USB 558 >; 559 clock-output-names = 560 "ether", "vin0", "vin1", "usb"; 561 }; 562 mstp3_clks: mstp3_clks@ffc8003c { 563 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; 564 reg = <0xffc8003c 4>; 565 clocks = <&s4_clk>, 566 <&cpg_clocks R8A7778_CLK_P>, 567 <&cpg_clocks R8A7778_CLK_P>, 568 <&cpg_clocks R8A7778_CLK_P>, 569 <&cpg_clocks R8A7778_CLK_P>, 570 <&cpg_clocks R8A7778_CLK_P>, 571 <&cpg_clocks R8A7778_CLK_P>, 572 <&cpg_clocks R8A7778_CLK_P>, 573 <&cpg_clocks R8A7778_CLK_P>; 574 #clock-cells = <1>; 575 clock-indices = < 576 R8A7778_CLK_MMC R8A7778_CLK_SDHI0 577 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2 578 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5 579 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7 580 R8A7778_CLK_SSI8 581 >; 582 clock-output-names = 583 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4", 584 "ssi5", "ssi6", "ssi7", "ssi8"; 585 }; 586 mstp5_clks: mstp5_clks@ffc80054 { 587 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks"; 588 reg = <0xffc80054 4>; 589 clocks = <&cpg_clocks R8A7778_CLK_P>, 590 <&cpg_clocks R8A7778_CLK_P>, 591 <&cpg_clocks R8A7778_CLK_P>, 592 <&cpg_clocks R8A7778_CLK_P>, 593 <&cpg_clocks R8A7778_CLK_P>, 594 <&cpg_clocks R8A7778_CLK_P>, 595 <&cpg_clocks R8A7778_CLK_P>, 596 <&cpg_clocks R8A7778_CLK_P>, 597 <&cpg_clocks R8A7778_CLK_P>; 598 #clock-cells = <1>; 599 clock-indices = < 600 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1 601 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3 602 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5 603 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7 604 R8A7778_CLK_SRU_SRC8 605 >; 606 clock-output-names = 607 "sru-src0", "sru-src1", "sru-src2", 608 "sru-src3", "sru-src4", "sru-src5", 609 "sru-src6", "sru-src7", "sru-src8"; 610 }; 611 }; 612}; 613