1/* 2 * Device Tree Source for Renesas r8a7779 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Simon Horman 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12/include/ "skeleton.dtsi" 13 14#include <dt-bindings/clock/r8a7779-clock.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/interrupt-controller/irq.h> 17 18/ { 19 compatible = "renesas,r8a7779"; 20 interrupt-parent = <&gic>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a9"; 29 reg = <0>; 30 clock-frequency = <1000000000>; 31 }; 32 cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a9"; 35 reg = <1>; 36 clock-frequency = <1000000000>; 37 }; 38 cpu@2 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 reg = <2>; 42 clock-frequency = <1000000000>; 43 }; 44 cpu@3 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a9"; 47 reg = <3>; 48 clock-frequency = <1000000000>; 49 }; 50 }; 51 52 aliases { 53 spi0 = &hspi0; 54 spi1 = &hspi1; 55 spi2 = &hspi2; 56 }; 57 58 gic: interrupt-controller@f0001000 { 59 compatible = "arm,cortex-a9-gic"; 60 #interrupt-cells = <3>; 61 interrupt-controller; 62 reg = <0xf0001000 0x1000>, 63 <0xf0000100 0x100>; 64 }; 65 66 timer@f0000200 { 67 compatible = "arm,cortex-a9-global-timer"; 68 reg = <0xf0000200 0x100>; 69 interrupts = <GIC_PPI 11 70 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 71 clocks = <&cpg_clocks R8A7779_CLK_ZS>; 72 }; 73 74 timer@f0000600 { 75 compatible = "arm,cortex-a9-twd-timer"; 76 reg = <0xf0000600 0x20>; 77 interrupts = <GIC_PPI 13 78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 79 clocks = <&cpg_clocks R8A7779_CLK_ZS>; 80 }; 81 82 gpio0: gpio@ffc40000 { 83 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 84 reg = <0xffc40000 0x2c>; 85 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; 86 #gpio-cells = <2>; 87 gpio-controller; 88 gpio-ranges = <&pfc 0 0 32>; 89 #interrupt-cells = <2>; 90 interrupt-controller; 91 }; 92 93 gpio1: gpio@ffc41000 { 94 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 95 reg = <0xffc41000 0x2c>; 96 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; 97 #gpio-cells = <2>; 98 gpio-controller; 99 gpio-ranges = <&pfc 0 32 32>; 100 #interrupt-cells = <2>; 101 interrupt-controller; 102 }; 103 104 gpio2: gpio@ffc42000 { 105 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 106 reg = <0xffc42000 0x2c>; 107 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 108 #gpio-cells = <2>; 109 gpio-controller; 110 gpio-ranges = <&pfc 0 64 32>; 111 #interrupt-cells = <2>; 112 interrupt-controller; 113 }; 114 115 gpio3: gpio@ffc43000 { 116 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 117 reg = <0xffc43000 0x2c>; 118 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 119 #gpio-cells = <2>; 120 gpio-controller; 121 gpio-ranges = <&pfc 0 96 32>; 122 #interrupt-cells = <2>; 123 interrupt-controller; 124 }; 125 126 gpio4: gpio@ffc44000 { 127 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 128 reg = <0xffc44000 0x2c>; 129 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 130 #gpio-cells = <2>; 131 gpio-controller; 132 gpio-ranges = <&pfc 0 128 32>; 133 #interrupt-cells = <2>; 134 interrupt-controller; 135 }; 136 137 gpio5: gpio@ffc45000 { 138 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 139 reg = <0xffc45000 0x2c>; 140 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; 141 #gpio-cells = <2>; 142 gpio-controller; 143 gpio-ranges = <&pfc 0 160 32>; 144 #interrupt-cells = <2>; 145 interrupt-controller; 146 }; 147 148 gpio6: gpio@ffc46000 { 149 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 150 reg = <0xffc46000 0x2c>; 151 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 192 9>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 }; 158 159 irqpin0: interrupt-controller@fe78001c { 160 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; 161 #interrupt-cells = <2>; 162 status = "disabled"; 163 interrupt-controller; 164 reg = <0xfe78001c 4>, 165 <0xfe780010 4>, 166 <0xfe780024 4>, 167 <0xfe780044 4>, 168 <0xfe780064 4>, 169 <0xfe780000 4>; 170 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 171 0 28 IRQ_TYPE_LEVEL_HIGH 172 0 29 IRQ_TYPE_LEVEL_HIGH 173 0 30 IRQ_TYPE_LEVEL_HIGH>; 174 sense-bitfield-width = <2>; 175 }; 176 177 i2c0: i2c@ffc70000 { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 compatible = "renesas,i2c-r8a7779"; 181 reg = <0xffc70000 0x1000>; 182 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&mstp0_clks R8A7779_CLK_I2C0>; 184 power-domains = <&cpg_clocks>; 185 status = "disabled"; 186 }; 187 188 i2c1: i2c@ffc71000 { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 compatible = "renesas,i2c-r8a7779"; 192 reg = <0xffc71000 0x1000>; 193 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&mstp0_clks R8A7779_CLK_I2C1>; 195 power-domains = <&cpg_clocks>; 196 status = "disabled"; 197 }; 198 199 i2c2: i2c@ffc72000 { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 compatible = "renesas,i2c-r8a7779"; 203 reg = <0xffc72000 0x1000>; 204 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&mstp0_clks R8A7779_CLK_I2C2>; 206 power-domains = <&cpg_clocks>; 207 status = "disabled"; 208 }; 209 210 i2c3: i2c@ffc73000 { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 compatible = "renesas,i2c-r8a7779"; 214 reg = <0xffc73000 0x1000>; 215 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&mstp0_clks R8A7779_CLK_I2C3>; 217 power-domains = <&cpg_clocks>; 218 status = "disabled"; 219 }; 220 221 scif0: serial@ffe40000 { 222 compatible = "renesas,scif-r8a7779", "renesas,scif"; 223 reg = <0xffe40000 0x100>; 224 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; 226 clock-names = "sci_ick"; 227 power-domains = <&cpg_clocks>; 228 status = "disabled"; 229 }; 230 231 scif1: serial@ffe41000 { 232 compatible = "renesas,scif-r8a7779", "renesas,scif"; 233 reg = <0xffe41000 0x100>; 234 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; 236 clock-names = "sci_ick"; 237 power-domains = <&cpg_clocks>; 238 status = "disabled"; 239 }; 240 241 scif2: serial@ffe42000 { 242 compatible = "renesas,scif-r8a7779", "renesas,scif"; 243 reg = <0xffe42000 0x100>; 244 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; 246 clock-names = "sci_ick"; 247 power-domains = <&cpg_clocks>; 248 status = "disabled"; 249 }; 250 251 scif3: serial@ffe43000 { 252 compatible = "renesas,scif-r8a7779", "renesas,scif"; 253 reg = <0xffe43000 0x100>; 254 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; 256 clock-names = "sci_ick"; 257 power-domains = <&cpg_clocks>; 258 status = "disabled"; 259 }; 260 261 scif4: serial@ffe44000 { 262 compatible = "renesas,scif-r8a7779", "renesas,scif"; 263 reg = <0xffe44000 0x100>; 264 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; 266 clock-names = "sci_ick"; 267 power-domains = <&cpg_clocks>; 268 status = "disabled"; 269 }; 270 271 scif5: serial@ffe45000 { 272 compatible = "renesas,scif-r8a7779", "renesas,scif"; 273 reg = <0xffe45000 0x100>; 274 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; 276 clock-names = "sci_ick"; 277 power-domains = <&cpg_clocks>; 278 status = "disabled"; 279 }; 280 281 pfc: pfc@fffc0000 { 282 compatible = "renesas,pfc-r8a7779"; 283 reg = <0xfffc0000 0x23c>; 284 }; 285 286 thermal@ffc48000 { 287 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; 288 reg = <0xffc48000 0x38>; 289 }; 290 291 tmu0: timer@ffd80000 { 292 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 293 reg = <0xffd80000 0x30>; 294 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 295 <0 33 IRQ_TYPE_LEVEL_HIGH>, 296 <0 34 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&mstp0_clks R8A7779_CLK_TMU0>; 298 clock-names = "fck"; 299 power-domains = <&cpg_clocks>; 300 301 #renesas,channels = <3>; 302 303 status = "disabled"; 304 }; 305 306 tmu1: timer@ffd81000 { 307 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 308 reg = <0xffd81000 0x30>; 309 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 310 <0 37 IRQ_TYPE_LEVEL_HIGH>, 311 <0 38 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&mstp0_clks R8A7779_CLK_TMU1>; 313 clock-names = "fck"; 314 power-domains = <&cpg_clocks>; 315 316 #renesas,channels = <3>; 317 318 status = "disabled"; 319 }; 320 321 tmu2: timer@ffd82000 { 322 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 323 reg = <0xffd82000 0x30>; 324 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 325 <0 41 IRQ_TYPE_LEVEL_HIGH>, 326 <0 42 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&mstp0_clks R8A7779_CLK_TMU2>; 328 clock-names = "fck"; 329 power-domains = <&cpg_clocks>; 330 331 #renesas,channels = <3>; 332 333 status = "disabled"; 334 }; 335 336 sata: sata@fc600000 { 337 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; 338 reg = <0xfc600000 0x2000>; 339 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&mstp1_clks R8A7779_CLK_SATA>; 341 power-domains = <&cpg_clocks>; 342 }; 343 344 sdhi0: sd@ffe4c000 { 345 compatible = "renesas,sdhi-r8a7779"; 346 reg = <0xffe4c000 0x100>; 347 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; 349 power-domains = <&cpg_clocks>; 350 status = "disabled"; 351 }; 352 353 sdhi1: sd@ffe4d000 { 354 compatible = "renesas,sdhi-r8a7779"; 355 reg = <0xffe4d000 0x100>; 356 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; 358 power-domains = <&cpg_clocks>; 359 status = "disabled"; 360 }; 361 362 sdhi2: sd@ffe4e000 { 363 compatible = "renesas,sdhi-r8a7779"; 364 reg = <0xffe4e000 0x100>; 365 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; 367 power-domains = <&cpg_clocks>; 368 status = "disabled"; 369 }; 370 371 sdhi3: sd@ffe4f000 { 372 compatible = "renesas,sdhi-r8a7779"; 373 reg = <0xffe4f000 0x100>; 374 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; 376 power-domains = <&cpg_clocks>; 377 status = "disabled"; 378 }; 379 380 hspi0: spi@fffc7000 { 381 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 382 reg = <0xfffc7000 0x18>; 383 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 387 power-domains = <&cpg_clocks>; 388 status = "disabled"; 389 }; 390 391 hspi1: spi@fffc8000 { 392 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 393 reg = <0xfffc8000 0x18>; 394 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 398 power-domains = <&cpg_clocks>; 399 status = "disabled"; 400 }; 401 402 hspi2: spi@fffc6000 { 403 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 404 reg = <0xfffc6000 0x18>; 405 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 409 power-domains = <&cpg_clocks>; 410 status = "disabled"; 411 }; 412 413 du: display@fff80000 { 414 compatible = "renesas,du-r8a7779"; 415 reg = <0 0xfff80000 0 0x40000>; 416 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&mstp1_clks R8A7779_CLK_DU>; 418 power-domains = <&cpg_clocks>; 419 status = "disabled"; 420 421 ports { 422 #address-cells = <1>; 423 #size-cells = <0>; 424 425 port@0 { 426 reg = <0>; 427 du_out_rgb0: endpoint { 428 }; 429 }; 430 port@1 { 431 reg = <1>; 432 du_out_rgb1: endpoint { 433 }; 434 }; 435 }; 436 }; 437 438 clocks { 439 #address-cells = <1>; 440 #size-cells = <1>; 441 ranges; 442 443 /* External root clock */ 444 extal_clk: extal_clk { 445 compatible = "fixed-clock"; 446 #clock-cells = <0>; 447 /* This value must be overriden by the board. */ 448 clock-frequency = <0>; 449 clock-output-names = "extal"; 450 }; 451 452 /* Special CPG clocks */ 453 cpg_clocks: clocks@ffc80000 { 454 compatible = "renesas,r8a7779-cpg-clocks"; 455 reg = <0xffc80000 0x30>; 456 clocks = <&extal_clk>; 457 #clock-cells = <1>; 458 clock-output-names = "plla", "z", "zs", "s", 459 "s1", "p", "b", "out"; 460 #power-domain-cells = <0>; 461 }; 462 463 /* Fixed factor clocks */ 464 i_clk: i_clk { 465 compatible = "fixed-factor-clock"; 466 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 467 #clock-cells = <0>; 468 clock-div = <2>; 469 clock-mult = <1>; 470 clock-output-names = "i"; 471 }; 472 s3_clk: s3_clk { 473 compatible = "fixed-factor-clock"; 474 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 475 #clock-cells = <0>; 476 clock-div = <8>; 477 clock-mult = <1>; 478 clock-output-names = "s3"; 479 }; 480 s4_clk: s4_clk { 481 compatible = "fixed-factor-clock"; 482 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 483 #clock-cells = <0>; 484 clock-div = <16>; 485 clock-mult = <1>; 486 clock-output-names = "s4"; 487 }; 488 g_clk: g_clk { 489 compatible = "fixed-factor-clock"; 490 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 491 #clock-cells = <0>; 492 clock-div = <24>; 493 clock-mult = <1>; 494 clock-output-names = "g"; 495 }; 496 497 /* Gate clocks */ 498 mstp0_clks: clocks@ffc80030 { 499 compatible = "renesas,r8a7779-mstp-clocks", 500 "renesas,cpg-mstp-clocks"; 501 reg = <0xffc80030 4>; 502 clocks = <&cpg_clocks R8A7779_CLK_S>, 503 <&cpg_clocks R8A7779_CLK_P>, 504 <&cpg_clocks R8A7779_CLK_P>, 505 <&cpg_clocks R8A7779_CLK_P>, 506 <&cpg_clocks R8A7779_CLK_S>, 507 <&cpg_clocks R8A7779_CLK_S>, 508 <&cpg_clocks R8A7779_CLK_P>, 509 <&cpg_clocks R8A7779_CLK_P>, 510 <&cpg_clocks R8A7779_CLK_P>, 511 <&cpg_clocks R8A7779_CLK_P>, 512 <&cpg_clocks R8A7779_CLK_P>, 513 <&cpg_clocks R8A7779_CLK_P>, 514 <&cpg_clocks R8A7779_CLK_P>, 515 <&cpg_clocks R8A7779_CLK_P>, 516 <&cpg_clocks R8A7779_CLK_P>, 517 <&cpg_clocks R8A7779_CLK_P>; 518 #clock-cells = <1>; 519 clock-indices = < 520 R8A7779_CLK_HSPI R8A7779_CLK_TMU2 521 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 522 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 523 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 524 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 525 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 526 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 527 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 528 >; 529 clock-output-names = 530 "hspi", "tmu2", "tmu1", "tmu0", "hscif1", 531 "hscif0", "scif5", "scif4", "scif3", "scif2", 532 "scif1", "scif0", "i2c3", "i2c2", "i2c1", 533 "i2c0"; 534 }; 535 mstp1_clks: clocks@ffc80034 { 536 compatible = "renesas,r8a7779-mstp-clocks", 537 "renesas,cpg-mstp-clocks"; 538 reg = <0xffc80034 4>, <0xffc80044 4>; 539 clocks = <&cpg_clocks R8A7779_CLK_P>, 540 <&cpg_clocks R8A7779_CLK_P>, 541 <&cpg_clocks R8A7779_CLK_S>, 542 <&cpg_clocks R8A7779_CLK_S>, 543 <&cpg_clocks R8A7779_CLK_S>, 544 <&cpg_clocks R8A7779_CLK_S>, 545 <&cpg_clocks R8A7779_CLK_P>, 546 <&cpg_clocks R8A7779_CLK_P>, 547 <&cpg_clocks R8A7779_CLK_P>, 548 <&cpg_clocks R8A7779_CLK_S>; 549 #clock-cells = <1>; 550 clock-indices = < 551 R8A7779_CLK_USB01 R8A7779_CLK_USB2 552 R8A7779_CLK_DU R8A7779_CLK_VIN2 553 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 554 R8A7779_CLK_ETHER R8A7779_CLK_SATA 555 R8A7779_CLK_PCIE R8A7779_CLK_VIN3 556 >; 557 clock-output-names = 558 "usb01", "usb2", 559 "du", "vin2", 560 "vin1", "vin0", 561 "ether", "sata", 562 "pcie", "vin3"; 563 }; 564 mstp3_clks: clocks@ffc8003c { 565 compatible = "renesas,r8a7779-mstp-clocks", 566 "renesas,cpg-mstp-clocks"; 567 reg = <0xffc8003c 4>; 568 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, 569 <&s4_clk>, <&s4_clk>; 570 #clock-cells = <1>; 571 clock-indices = < 572 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 573 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 574 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 575 >; 576 clock-output-names = 577 "sdhi3", "sdhi2", "sdhi1", "sdhi0", 578 "mmc1", "mmc0"; 579 }; 580 }; 581}; 582