1/* 2 * Device Tree Source for the r8a7793 SoC 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/clock/r8a7793-clock.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14 15/ { 16 compatible = "renesas,r8a7793"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a15"; 28 reg = <0>; 29 clock-frequency = <1500000000>; 30 voltage-tolerance = <1>; /* 1% */ 31 clocks = <&cpg_clocks R8A7793_CLK_Z>; 32 clock-latency = <300000>; /* 300 us */ 33 34 /* kHz - uV - OPPs unknown yet */ 35 operating-points = <1500000 1000000>, 36 <1312500 1000000>, 37 <1125000 1000000>, 38 < 937500 1000000>, 39 < 750000 1000000>, 40 < 375000 1000000>; 41 }; 42 }; 43 44 gic: interrupt-controller@f1001000 { 45 compatible = "arm,gic-400"; 46 #interrupt-cells = <3>; 47 #address-cells = <0>; 48 interrupt-controller; 49 reg = <0 0xf1001000 0 0x1000>, 50 <0 0xf1002000 0 0x1000>, 51 <0 0xf1004000 0 0x2000>, 52 <0 0xf1006000 0 0x2000>; 53 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 54 }; 55 56 timer { 57 compatible = "arm,armv7-timer"; 58 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 59 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 60 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 61 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 62 }; 63 64 cmt0: timer@ffca0000 { 65 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; 66 reg = <0 0xffca0000 0 0x1004>; 67 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, 68 <0 143 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&mstp1_clks R8A7793_CLK_CMT0>; 70 clock-names = "fck"; 71 power-domains = <&cpg_clocks>; 72 73 renesas,channels-mask = <0x60>; 74 75 status = "disabled"; 76 }; 77 78 cmt1: timer@e6130000 { 79 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; 80 reg = <0 0xe6130000 0 0x1004>; 81 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, 82 <0 121 IRQ_TYPE_LEVEL_HIGH>, 83 <0 122 IRQ_TYPE_LEVEL_HIGH>, 84 <0 123 IRQ_TYPE_LEVEL_HIGH>, 85 <0 124 IRQ_TYPE_LEVEL_HIGH>, 86 <0 125 IRQ_TYPE_LEVEL_HIGH>, 87 <0 126 IRQ_TYPE_LEVEL_HIGH>, 88 <0 127 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&mstp3_clks R8A7793_CLK_CMT1>; 90 clock-names = "fck"; 91 power-domains = <&cpg_clocks>; 92 93 renesas,channels-mask = <0xff>; 94 95 status = "disabled"; 96 }; 97 98 irqc0: interrupt-controller@e61c0000 { 99 compatible = "renesas,irqc-r8a7793", "renesas,irqc"; 100 #interrupt-cells = <2>; 101 interrupt-controller; 102 reg = <0 0xe61c0000 0 0x200>; 103 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 104 <0 1 IRQ_TYPE_LEVEL_HIGH>, 105 <0 2 IRQ_TYPE_LEVEL_HIGH>, 106 <0 3 IRQ_TYPE_LEVEL_HIGH>, 107 <0 12 IRQ_TYPE_LEVEL_HIGH>, 108 <0 13 IRQ_TYPE_LEVEL_HIGH>, 109 <0 14 IRQ_TYPE_LEVEL_HIGH>, 110 <0 15 IRQ_TYPE_LEVEL_HIGH>, 111 <0 16 IRQ_TYPE_LEVEL_HIGH>, 112 <0 17 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&mstp4_clks R8A7793_CLK_IRQC>; 114 power-domains = <&cpg_clocks>; 115 }; 116 117 scif0: serial@e6e60000 { 118 compatible = "renesas,scif-r8a7793", "renesas,scif"; 119 reg = <0 0xe6e60000 0 64>; 120 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>; 122 clock-names = "sci_ick"; 123 power-domains = <&cpg_clocks>; 124 status = "disabled"; 125 }; 126 127 scif1: serial@e6e68000 { 128 compatible = "renesas,scif-r8a7793", "renesas,scif"; 129 reg = <0 0xe6e68000 0 64>; 130 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>; 132 clock-names = "sci_ick"; 133 power-domains = <&cpg_clocks>; 134 status = "disabled"; 135 }; 136 137 ether: ethernet@ee700000 { 138 compatible = "renesas,ether-r8a7793"; 139 reg = <0 0xee700000 0 0x400>; 140 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&mstp8_clks R8A7793_CLK_ETHER>; 142 power-domains = <&cpg_clocks>; 143 phy-mode = "rmii"; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 status = "disabled"; 147 }; 148 149 clocks { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 /* External root clock */ 155 extal_clk: extal_clk { 156 compatible = "fixed-clock"; 157 #clock-cells = <0>; 158 /* This value must be overridden by the board. */ 159 clock-frequency = <0>; 160 clock-output-names = "extal"; 161 }; 162 163 /* Special CPG clocks */ 164 cpg_clocks: cpg_clocks@e6150000 { 165 compatible = "renesas,r8a7793-cpg-clocks", 166 "renesas,rcar-gen2-cpg-clocks"; 167 reg = <0 0xe6150000 0 0x1000>; 168 clocks = <&extal_clk>; 169 #clock-cells = <1>; 170 clock-output-names = "main", "pll0", "pll1", "pll3", 171 "lb", "qspi", "sdh", "sd0", "z", 172 "rcan", "adsp"; 173 #power-domain-cells = <0>; 174 }; 175 176 /* Variable factor clocks */ 177 sd2_clk: sd2_clk@e6150078 { 178 compatible = "renesas,r8a7793-div6-clock", 179 "renesas,cpg-div6-clock"; 180 reg = <0 0xe6150078 0 4>; 181 clocks = <&pll1_div2_clk>; 182 #clock-cells = <0>; 183 clock-output-names = "sd2"; 184 }; 185 sd3_clk: sd3_clk@e615026c { 186 compatible = "renesas,r8a7793-div6-clock", 187 "renesas,cpg-div6-clock"; 188 reg = <0 0xe615026c 0 4>; 189 clocks = <&pll1_div2_clk>; 190 #clock-cells = <0>; 191 clock-output-names = "sd3"; 192 }; 193 mmc0_clk: mmc0_clk@e6150240 { 194 compatible = "renesas,r8a7793-div6-clock", 195 "renesas,cpg-div6-clock"; 196 reg = <0 0xe6150240 0 4>; 197 clocks = <&pll1_div2_clk>; 198 #clock-cells = <0>; 199 clock-output-names = "mmc0"; 200 }; 201 202 /* Fixed factor clocks */ 203 pll1_div2_clk: pll1_div2_clk { 204 compatible = "fixed-factor-clock"; 205 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 206 #clock-cells = <0>; 207 clock-div = <2>; 208 clock-mult = <1>; 209 clock-output-names = "pll1_div2"; 210 }; 211 zg_clk: zg_clk { 212 compatible = "fixed-factor-clock"; 213 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 214 #clock-cells = <0>; 215 clock-div = <5>; 216 clock-mult = <1>; 217 clock-output-names = "zg"; 218 }; 219 zx_clk: zx_clk { 220 compatible = "fixed-factor-clock"; 221 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 222 #clock-cells = <0>; 223 clock-div = <3>; 224 clock-mult = <1>; 225 clock-output-names = "zx"; 226 }; 227 zs_clk: zs_clk { 228 compatible = "fixed-factor-clock"; 229 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 230 #clock-cells = <0>; 231 clock-div = <6>; 232 clock-mult = <1>; 233 clock-output-names = "zs"; 234 }; 235 hp_clk: hp_clk { 236 compatible = "fixed-factor-clock"; 237 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 238 #clock-cells = <0>; 239 clock-div = <12>; 240 clock-mult = <1>; 241 clock-output-names = "hp"; 242 }; 243 p_clk: p_clk { 244 compatible = "fixed-factor-clock"; 245 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 246 #clock-cells = <0>; 247 clock-div = <24>; 248 clock-mult = <1>; 249 clock-output-names = "p"; 250 }; 251 rclk_clk: rclk_clk { 252 compatible = "fixed-factor-clock"; 253 clocks = <&cpg_clocks R8A7793_CLK_PLL1>; 254 #clock-cells = <0>; 255 clock-div = <(48 * 1024)>; 256 clock-mult = <1>; 257 clock-output-names = "rclk"; 258 }; 259 mp_clk: mp_clk { 260 compatible = "fixed-factor-clock"; 261 clocks = <&pll1_div2_clk>; 262 #clock-cells = <0>; 263 clock-div = <15>; 264 clock-mult = <1>; 265 clock-output-names = "mp"; 266 }; 267 cp_clk: cp_clk { 268 compatible = "fixed-factor-clock"; 269 clocks = <&extal_clk>; 270 #clock-cells = <0>; 271 clock-div = <2>; 272 clock-mult = <1>; 273 clock-output-names = "cp"; 274 }; 275 276 /* Gate clocks */ 277 mstp1_clks: mstp1_clks@e6150134 { 278 compatible = "renesas,r8a7793-mstp-clocks", 279 "renesas,cpg-mstp-clocks"; 280 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 281 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, 282 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, 283 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, 284 <&zs_clk>, <&zs_clk>, <&zs_clk>; 285 #clock-cells = <1>; 286 clock-indices = < 287 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 288 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 289 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC 290 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 291 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 292 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 293 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 294 R8A7793_CLK_VSP1_S 295 >; 296 clock-output-names = 297 "vcp0", "vpc0", "ssp_dev", "tmu1", 298 "pvrsrvkm", "tddmac", "fdp1", "fdp0", 299 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 300 "vsp1-du0", "vsps"; 301 }; 302 mstp3_clks: mstp3_clks@e615013c { 303 compatible = "renesas,r8a7793-mstp-clocks", 304 "renesas,cpg-mstp-clocks"; 305 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 306 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, 307 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, 308 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, 309 <&rclk_clk>, <&hp_clk>, <&hp_clk>; 310 #clock-cells = <1>; 311 clock-indices = < 312 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 313 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 314 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 315 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 316 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 317 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 318 >; 319 clock-output-names = 320 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", 321 "i2c7", "pciec", "i2c8", "ssusb", "cmt1", 322 "usbdmac0", "usbdmac1"; 323 }; 324 mstp4_clks: mstp4_clks@e6150140 { 325 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; 326 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 327 clocks = <&cp_clk>; 328 #clock-cells = <1>; 329 clock-indices = <R8A7793_CLK_IRQC>; 330 clock-output-names = "irqc"; 331 }; 332 mstp7_clks: mstp7_clks@e615014c { 333 compatible = "renesas,r8a7793-mstp-clocks", 334 "renesas,cpg-mstp-clocks"; 335 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 336 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, 337 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, 338 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, 339 <&zx_clk>, <&zx_clk>; 340 #clock-cells = <1>; 341 clock-indices = < 342 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB 343 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 344 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 345 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 346 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 347 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 348 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 349 >; 350 clock-output-names = 351 "ehci", "hsusb", "hscif2", "scif5", "scif4", 352 "hscif1", "hscif0", "scif3", "scif2", 353 "scif1", "scif0", "du1", "du0", "lvds0"; 354 }; 355 mstp8_clks: mstp8_clks@e6150990 { 356 compatible = "renesas,r8a7793-mstp-clocks", 357 "renesas,cpg-mstp-clocks"; 358 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 359 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, 360 <&p_clk>, <&zs_clk>, <&zs_clk>; 361 #clock-cells = <1>; 362 clock-indices = < 363 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 364 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 365 R8A7793_CLK_ETHER R8A7793_CLK_SATA1 366 R8A7793_CLK_SATA0 367 >; 368 clock-output-names = 369 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", 370 "sata1", "sata0"; 371 }; 372 }; 373 374}; 375