1/* 2 * DTS file for all SPEAr1340 SoCs 3 * 4 * Copyright 2012 Viresh Kumar <vireshk@kernel.org> 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14/include/ "spear13xx.dtsi" 15 16/ { 17 compatible = "st,spear1340"; 18 19 ahb { 20 21 spics: spics@e0700000{ 22 compatible = "st,spear-spics-gpio"; 23 reg = <0xe0700000 0x1000>; 24 st-spics,peripcfg-reg = <0x42c>; 25 st-spics,sw-enable-bit = <21>; 26 st-spics,cs-value-bit = <20>; 27 st-spics,cs-enable-mask = <3>; 28 st-spics,cs-enable-shift = <18>; 29 gpio-controller; 30 #gpio-cells = <2>; 31 status = "disabled"; 32 }; 33 34 miphy0: miphy@eb800000 { 35 compatible = "st,spear1340-miphy"; 36 reg = <0xeb800000 0x4000>; 37 misc = <&misc>; 38 #phy-cells = <1>; 39 status = "disabled"; 40 }; 41 42 ahci0: ahci@b1000000 { 43 compatible = "snps,spear-ahci"; 44 reg = <0xb1000000 0x10000>; 45 interrupts = <0 72 0x4>; 46 phys = <&miphy0 0>; 47 phy-names = "sata-phy"; 48 status = "disabled"; 49 }; 50 51 pcie0: pcie@b1000000 { 52 compatible = "st,spear1340-pcie", "snps,dw-pcie"; 53 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; 54 reg-names = "dbi", "config"; 55 interrupts = <0 68 0x4>; 56 interrupt-map-mask = <0 0 0 0>; 57 interrupt-map = <0x0 0 &gic 0 68 0x4>; 58 num-lanes = <1>; 59 phys = <&miphy0 1>; 60 phy-names = "pcie-phy"; 61 #address-cells = <3>; 62 #size-cells = <2>; 63 device_type = "pci"; 64 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 65 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ 66 status = "disabled"; 67 }; 68 69 i2s-play@b2400000 { 70 compatible = "snps,designware-i2s"; 71 reg = <0xb2400000 0x10000>; 72 interrupt-names = "play_irq"; 73 interrupts = <0 98 0x4 74 0 99 0x4>; 75 play; 76 channel = <8>; 77 status = "disabled"; 78 }; 79 80 i2s-rec@b2000000 { 81 compatible = "snps,designware-i2s"; 82 reg = <0xb2000000 0x10000>; 83 interrupt-names = "record_irq"; 84 interrupts = <0 100 0x4 85 0 101 0x4>; 86 record; 87 channel = <8>; 88 status = "disabled"; 89 }; 90 91 pinmux: pinmux@e0700000 { 92 compatible = "st,spear1340-pinmux"; 93 reg = <0xe0700000 0x1000>; 94 #gpio-range-cells = <3>; 95 }; 96 97 pwm: pwm@e0180000 { 98 compatible ="st,spear13xx-pwm"; 99 reg = <0xe0180000 0x1000>; 100 #pwm-cells = <2>; 101 status = "disabled"; 102 }; 103 104 spdif-in@d0100000 { 105 compatible = "st,spdif-in"; 106 reg = < 0xd0100000 0x20000 107 0xd0110000 0x10000 >; 108 interrupts = <0 84 0x4>; 109 status = "disabled"; 110 }; 111 112 spdif-out@d0000000 { 113 compatible = "st,spdif-out"; 114 reg = <0xd0000000 0x20000>; 115 interrupts = <0 85 0x4>; 116 status = "disabled"; 117 }; 118 119 spi1: spi@5d400000 { 120 compatible = "arm,pl022", "arm,primecell"; 121 reg = <0x5d400000 0x1000>; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 interrupts = <0 99 0x4>; 125 status = "disabled"; 126 }; 127 128 apb { 129 i2c1: i2c@b4000000 { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 compatible = "snps,designware-i2c"; 133 reg = <0xb4000000 0x1000>; 134 interrupts = <0 104 0x4>; 135 write-16bit; 136 status = "disabled"; 137 }; 138 139 serial@b4100000 { 140 compatible = "arm,pl011", "arm,primecell"; 141 reg = <0xb4100000 0x1000>; 142 interrupts = <0 105 0x4>; 143 status = "disabled"; 144 dmas = <&dwdma0 12 0 1>, 145 <&dwdma0 13 1 0>; 146 dma-names = "tx", "rx"; 147 }; 148 149 thermal@e07008c4 { 150 st,thermal-flags = <0x2a00>; 151 }; 152 153 gpiopinctrl: gpio@e2800000 { 154 compatible = "st,spear-plgpio"; 155 reg = <0xe2800000 0x1000>; 156 interrupts = <0 107 0x4>; 157 #interrupt-cells = <1>; 158 interrupt-controller; 159 gpio-controller; 160 #gpio-cells = <2>; 161 gpio-ranges = <&pinmux 0 0 252>; 162 status = "disabled"; 163 164 st-plgpio,ngpio = <250>; 165 st-plgpio,wdata-reg = <0x40>; 166 st-plgpio,dir-reg = <0x00>; 167 st-plgpio,ie-reg = <0x80>; 168 st-plgpio,rdata-reg = <0x20>; 169 st-plgpio,mis-reg = <0xa0>; 170 st-plgpio,eit-reg = <0x60>; 171 }; 172 }; 173 }; 174}; 175