1/* 2 * Copyright (C) 2015 STMicroelectronics Limited. 3 * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * publishhed by the Free Software Foundation. 8 */ 9#include "stih407-clock.dtsi" 10#include "stih407-family.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12/ { 13 soc { 14 sti-display-subsystem { 15 compatible = "st,sti-display-subsystem"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 assigned-clocks = <&clk_s_d2_quadfs 0>, 20 <&clk_s_d2_quadfs 0>, 21 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, 22 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, 23 <&clk_s_d2_flexgen CLK_PIX_GDP1>, 24 <&clk_s_d2_flexgen CLK_PIX_GDP2>, 25 <&clk_s_d2_flexgen CLK_PIX_GDP3>, 26 <&clk_s_d2_flexgen CLK_PIX_GDP4>; 27 28 assigned-clock-parents = <0>, 29 <0>, 30 <&clk_s_d2_quadfs 0>, 31 <&clk_s_d2_quadfs 0>, 32 <&clk_s_d2_quadfs 0>, 33 <&clk_s_d2_quadfs 0>, 34 <&clk_s_d2_quadfs 0>, 35 <&clk_s_d2_quadfs 0>; 36 37 assigned-clock-rates = <297000000>, <297000000>; 38 39 ranges; 40 41 sti-compositor@9d11000 { 42 compatible = "st,stih407-compositor"; 43 reg = <0x9d11000 0x1000>; 44 45 clock-names = "compo_main", 46 "compo_aux", 47 "pix_main", 48 "pix_aux", 49 "pix_gdp1", 50 "pix_gdp2", 51 "pix_gdp3", 52 "pix_gdp4", 53 "main_parent", 54 "aux_parent"; 55 56 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, 57 <&clk_s_c0_flexgen CLK_COMPO_DVP>, 58 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, 59 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, 60 <&clk_s_d2_flexgen CLK_PIX_GDP1>, 61 <&clk_s_d2_flexgen CLK_PIX_GDP2>, 62 <&clk_s_d2_flexgen CLK_PIX_GDP3>, 63 <&clk_s_d2_flexgen CLK_PIX_GDP4>, 64 <&clk_s_d2_quadfs 0>, 65 <&clk_s_d2_quadfs 1>; 66 67 reset-names = "compo-main", "compo-aux"; 68 resets = <&softreset STIH407_COMPO_SOFTRESET>, 69 <&softreset STIH407_COMPO_SOFTRESET>; 70 st,vtg = <&vtg_main>, <&vtg_aux>; 71 }; 72 73 sti-tvout@8d08000 { 74 compatible = "st,stih407-tvout"; 75 reg = <0x8d08000 0x1000>; 76 reg-names = "tvout-reg"; 77 reset-names = "tvout"; 78 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; 79 #address-cells = <1>; 80 #size-cells = <1>; 81 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, 82 <&clk_s_d2_flexgen CLK_TMDS_HDMI>, 83 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, 84 <&clk_s_d0_flexgen CLK_PCM_0>, 85 <&clk_s_d2_flexgen CLK_PIX_HDDAC>, 86 <&clk_s_d2_flexgen CLK_HDDAC>; 87 88 assigned-clock-parents = <&clk_s_d2_quadfs 0>, 89 <&clk_tmdsout_hdmi>, 90 <&clk_s_d2_quadfs 0>, 91 <&clk_s_d0_quadfs 0>, 92 <&clk_s_d2_quadfs 0>, 93 <&clk_s_d2_quadfs 0>; 94 }; 95 96 sti-hdmi@8d04000 { 97 compatible = "st,stih407-hdmi"; 98 reg = <0x8d04000 0x1000>; 99 reg-names = "hdmi-reg"; 100 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>; 101 interrupt-names = "irq"; 102 clock-names = "pix", 103 "tmds", 104 "phy", 105 "audio", 106 "main_parent", 107 "aux_parent"; 108 109 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, 110 <&clk_s_d2_flexgen CLK_TMDS_HDMI>, 111 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, 112 <&clk_s_d0_flexgen CLK_PCM_0>, 113 <&clk_s_d2_quadfs 0>, 114 <&clk_s_d2_quadfs 1>; 115 116 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; 117 reset-names = "hdmi"; 118 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; 119 ddc = <&hdmiddc>; 120 }; 121 122 sti-hda@8d02000 { 123 compatible = "st,stih407-hda"; 124 reg = <0x8d02000 0x400>, <0x92b0120 0x4>; 125 reg-names = "hda-reg", "video-dacs-ctrl"; 126 clock-names = "pix", 127 "hddac", 128 "main_parent", 129 "aux_parent"; 130 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, 131 <&clk_s_d2_flexgen CLK_HDDAC>, 132 <&clk_s_d2_quadfs 0>, 133 <&clk_s_d2_quadfs 1>; 134 }; 135 }; 136 }; 137}; 138