1/dts-v1/; 2/include/ "skeleton.dtsi" 3 4/ { 5 model = "ARM Versatile AB"; 6 compatible = "arm,versatile-ab"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 serial0 = &uart0; 13 serial1 = &uart1; 14 serial2 = &uart2; 15 i2c0 = &i2c0; 16 }; 17 18 chosen { 19 stdout-path = &uart0; 20 }; 21 22 memory { 23 reg = <0x0 0x08000000>; 24 }; 25 26 xtal24mhz: xtal24mhz@24M { 27 #clock-cells = <0>; 28 compatible = "fixed-clock"; 29 clock-frequency = <24000000>; 30 }; 31 32 core-module@10000000 { 33 compatible = "arm,core-module-versatile", "syscon"; 34 reg = <0x10000000 0x200>; 35 36 /* OSC1 on AB, OSC4 on PB */ 37 osc1: cm_aux_osc@24M { 38 #clock-cells = <0>; 39 compatible = "arm,versatile-cm-auxosc"; 40 clocks = <&xtal24mhz>; 41 }; 42 43 /* The timer clock is the 24 MHz oscillator divided to 1MHz */ 44 timclk: timclk@1M { 45 #clock-cells = <0>; 46 compatible = "fixed-factor-clock"; 47 clock-div = <24>; 48 clock-mult = <1>; 49 clocks = <&xtal24mhz>; 50 }; 51 52 pclk: pclk@24M { 53 #clock-cells = <0>; 54 compatible = "fixed-factor-clock"; 55 clock-div = <1>; 56 clock-mult = <1>; 57 clocks = <&xtal24mhz>; 58 }; 59 }; 60 61 flash@34000000 { 62 compatible = "arm,versatile-flash"; 63 reg = <0x34000000 0x4000000>; 64 bank-width = <4>; 65 }; 66 67 i2c0: i2c@10002000 { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 compatible = "arm,versatile-i2c"; 71 reg = <0x10002000 0x1000>; 72 73 rtc@68 { 74 compatible = "dallas,ds1338"; 75 reg = <0x68>; 76 }; 77 }; 78 79 net@10010000 { 80 compatible = "smsc,lan91c111"; 81 reg = <0x10010000 0x10000>; 82 interrupts = <25>; 83 }; 84 85 lcd@10008000 { 86 compatible = "arm,versatile-lcd"; 87 reg = <0x10008000 0x1000>; 88 }; 89 90 amba { 91 compatible = "arm,amba-bus"; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges; 95 96 vic: interrupt-controller@10140000 { 97 compatible = "arm,versatile-vic"; 98 interrupt-controller; 99 #interrupt-cells = <1>; 100 reg = <0x10140000 0x1000>; 101 valid-mask = <0xffffffff>; 102 }; 103 104 sic: interrupt-controller@10003000 { 105 compatible = "arm,versatile-sic"; 106 interrupt-controller; 107 #interrupt-cells = <1>; 108 reg = <0x10003000 0x1000>; 109 interrupt-parent = <&vic>; 110 interrupts = <31>; /* Cascaded to vic */ 111 clear-mask = <0xffffffff>; 112 /* 113 * Valid interrupt lines mask according to 114 * table 4-36 page 4-50 of ARM DUI 0225D 115 */ 116 valid-mask = <0x0760031b>; 117 }; 118 119 dma@10130000 { 120 compatible = "arm,pl081", "arm,primecell"; 121 reg = <0x10130000 0x1000>; 122 interrupts = <17>; 123 clocks = <&pclk>; 124 clock-names = "apb_pclk"; 125 }; 126 127 uart0: uart@101f1000 { 128 compatible = "arm,pl011", "arm,primecell"; 129 reg = <0x101f1000 0x1000>; 130 interrupts = <12>; 131 clocks = <&xtal24mhz>, <&pclk>; 132 clock-names = "uartclk", "apb_pclk"; 133 }; 134 135 uart1: uart@101f2000 { 136 compatible = "arm,pl011", "arm,primecell"; 137 reg = <0x101f2000 0x1000>; 138 interrupts = <13>; 139 clocks = <&xtal24mhz>, <&pclk>; 140 clock-names = "uartclk", "apb_pclk"; 141 }; 142 143 uart2: uart@101f3000 { 144 compatible = "arm,pl011", "arm,primecell"; 145 reg = <0x101f3000 0x1000>; 146 interrupts = <14>; 147 clocks = <&xtal24mhz>, <&pclk>; 148 clock-names = "uartclk", "apb_pclk"; 149 }; 150 151 smc@10100000 { 152 compatible = "arm,primecell"; 153 reg = <0x10100000 0x1000>; 154 clocks = <&pclk>; 155 clock-names = "apb_pclk"; 156 }; 157 158 mpmc@10110000 { 159 compatible = "arm,primecell"; 160 reg = <0x10110000 0x1000>; 161 clocks = <&pclk>; 162 clock-names = "apb_pclk"; 163 }; 164 165 display@10120000 { 166 compatible = "arm,pl110", "arm,primecell"; 167 reg = <0x10120000 0x1000>; 168 interrupts = <16>; 169 clocks = <&osc1>, <&pclk>; 170 clock-names = "clcd", "apb_pclk"; 171 }; 172 173 sctl@101e0000 { 174 compatible = "arm,primecell"; 175 reg = <0x101e0000 0x1000>; 176 clocks = <&pclk>; 177 clock-names = "apb_pclk"; 178 }; 179 180 watchdog@101e1000 { 181 compatible = "arm,primecell"; 182 reg = <0x101e1000 0x1000>; 183 interrupts = <0>; 184 clocks = <&pclk>; 185 clock-names = "apb_pclk"; 186 }; 187 188 timer@101e2000 { 189 compatible = "arm,sp804", "arm,primecell"; 190 reg = <0x101e2000 0x1000>; 191 interrupts = <4>; 192 clocks = <&timclk>, <&timclk>, <&pclk>; 193 clock-names = "timer0", "timer1", "apb_pclk"; 194 }; 195 196 timer@101e3000 { 197 compatible = "arm,sp804", "arm,primecell"; 198 reg = <0x101e3000 0x1000>; 199 interrupts = <5>; 200 clocks = <&timclk>, <&timclk>, <&pclk>; 201 clock-names = "timer0", "timer1", "apb_pclk"; 202 }; 203 204 gpio0: gpio@101e4000 { 205 compatible = "arm,pl061", "arm,primecell"; 206 reg = <0x101e4000 0x1000>; 207 gpio-controller; 208 interrupts = <6>; 209 #gpio-cells = <2>; 210 interrupt-controller; 211 #interrupt-cells = <2>; 212 clocks = <&pclk>; 213 clock-names = "apb_pclk"; 214 }; 215 216 gpio1: gpio@101e5000 { 217 compatible = "arm,pl061", "arm,primecell"; 218 reg = <0x101e5000 0x1000>; 219 interrupts = <7>; 220 gpio-controller; 221 #gpio-cells = <2>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 clocks = <&pclk>; 225 clock-names = "apb_pclk"; 226 }; 227 228 rtc@101e8000 { 229 compatible = "arm,pl030", "arm,primecell"; 230 reg = <0x101e8000 0x1000>; 231 interrupts = <10>; 232 clocks = <&pclk>; 233 clock-names = "apb_pclk"; 234 }; 235 236 sci@101f0000 { 237 compatible = "arm,primecell"; 238 reg = <0x101f0000 0x1000>; 239 interrupts = <15>; 240 clocks = <&pclk>; 241 clock-names = "apb_pclk"; 242 }; 243 244 ssp@101f4000 { 245 compatible = "arm,pl022", "arm,primecell"; 246 reg = <0x101f4000 0x1000>; 247 interrupts = <11>; 248 clocks = <&xtal24mhz>, <&pclk>; 249 clock-names = "SSPCLK", "apb_pclk"; 250 }; 251 252 fpga { 253 compatible = "arm,versatile-fpga", "simple-bus"; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 ranges = <0 0x10000000 0x10000>; 257 258 sysreg@0 { 259 compatible = "arm,versatile-sysreg", "syscon"; 260 reg = <0x00000 0x1000>; 261 }; 262 263 aaci@4000 { 264 compatible = "arm,primecell"; 265 reg = <0x4000 0x1000>; 266 interrupts = <24>; 267 clocks = <&pclk>; 268 clock-names = "apb_pclk"; 269 }; 270 mmc@5000 { 271 compatible = "arm,pl180", "arm,primecell"; 272 reg = <0x5000 0x1000>; 273 interrupts-extended = <&vic 22 &sic 1>; 274 clocks = <&xtal24mhz>, <&pclk>; 275 clock-names = "mclk", "apb_pclk"; 276 }; 277 kmi@6000 { 278 compatible = "arm,pl050", "arm,primecell"; 279 reg = <0x6000 0x1000>; 280 interrupt-parent = <&sic>; 281 interrupts = <3>; 282 clocks = <&xtal24mhz>, <&pclk>; 283 clock-names = "KMIREFCLK", "apb_pclk"; 284 }; 285 kmi@7000 { 286 compatible = "arm,pl050", "arm,primecell"; 287 reg = <0x7000 0x1000>; 288 interrupt-parent = <&sic>; 289 interrupts = <4>; 290 clocks = <&xtal24mhz>, <&pclk>; 291 clock-names = "KMIREFCLK", "apb_pclk"; 292 }; 293 }; 294 }; 295}; 296