1 #ifndef _ARM_HW_BREAKPOINT_H
2 #define _ARM_HW_BREAKPOINT_H
3
4 #ifdef __KERNEL__
5
6 struct task_struct;
7
8 #ifdef CONFIG_HAVE_HW_BREAKPOINT
9
10 struct arch_hw_breakpoint_ctrl {
11 u32 __reserved : 9,
12 mismatch : 1,
13 : 9,
14 len : 8,
15 type : 2,
16 privilege : 2,
17 enabled : 1;
18 };
19
20 struct arch_hw_breakpoint {
21 u32 address;
22 u32 trigger;
23 struct arch_hw_breakpoint_ctrl step_ctrl;
24 struct arch_hw_breakpoint_ctrl ctrl;
25 };
26
encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)27 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
28 {
29 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
30 (ctrl.privilege << 1) | ctrl.enabled;
31 }
32
decode_ctrl_reg(u32 reg,struct arch_hw_breakpoint_ctrl * ctrl)33 static inline void decode_ctrl_reg(u32 reg,
34 struct arch_hw_breakpoint_ctrl *ctrl)
35 {
36 ctrl->enabled = reg & 0x1;
37 reg >>= 1;
38 ctrl->privilege = reg & 0x3;
39 reg >>= 2;
40 ctrl->type = reg & 0x3;
41 reg >>= 2;
42 ctrl->len = reg & 0xff;
43 reg >>= 17;
44 ctrl->mismatch = reg & 0x1;
45 }
46
47 /* Debug architecture numbers. */
48 #define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */
49 #define ARM_DEBUG_ARCH_V6 1
50 #define ARM_DEBUG_ARCH_V6_1 2
51 #define ARM_DEBUG_ARCH_V7_ECP14 3
52 #define ARM_DEBUG_ARCH_V7_MM 4
53 #define ARM_DEBUG_ARCH_V7_1 5
54 #define ARM_DEBUG_ARCH_V8 6
55
56 /* Breakpoint */
57 #define ARM_BREAKPOINT_EXECUTE 0
58
59 /* Watchpoints */
60 #define ARM_BREAKPOINT_LOAD 1
61 #define ARM_BREAKPOINT_STORE 2
62 #define ARM_FSR_ACCESS_MASK (1 << 11)
63
64 /* Privilege Levels */
65 #define ARM_BREAKPOINT_PRIV 1
66 #define ARM_BREAKPOINT_USER 2
67
68 /* Lengths */
69 #define ARM_BREAKPOINT_LEN_1 0x1
70 #define ARM_BREAKPOINT_LEN_2 0x3
71 #define ARM_BREAKPOINT_LEN_4 0xf
72 #define ARM_BREAKPOINT_LEN_8 0xff
73
74 /* Limits */
75 #define ARM_MAX_BRP 16
76 #define ARM_MAX_WRP 16
77 #define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP)
78
79 /* DSCR method of entry bits. */
80 #define ARM_DSCR_MOE(x) ((x >> 2) & 0xf)
81 #define ARM_ENTRY_BREAKPOINT 0x1
82 #define ARM_ENTRY_ASYNC_WATCHPOINT 0x2
83 #define ARM_ENTRY_SYNC_WATCHPOINT 0xa
84
85 /* DSCR monitor/halting bits. */
86 #define ARM_DSCR_HDBGEN (1 << 14)
87 #define ARM_DSCR_MDBGEN (1 << 15)
88
89 /* OSLSR os lock model bits */
90 #define ARM_OSLSR_OSLM0 (1 << 0)
91
92 /* opcode2 numbers for the co-processor instructions. */
93 #define ARM_OP2_BVR 4
94 #define ARM_OP2_BCR 5
95 #define ARM_OP2_WVR 6
96 #define ARM_OP2_WCR 7
97
98 /* Base register numbers for the debug registers. */
99 #define ARM_BASE_BVR 64
100 #define ARM_BASE_BCR 80
101 #define ARM_BASE_WVR 96
102 #define ARM_BASE_WCR 112
103
104 /* Accessor macros for the debug registers. */
105 #define ARM_DBG_READ(N, M, OP2, VAL) do {\
106 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
107 } while (0)
108
109 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
110 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
111 } while (0)
112
113 struct notifier_block;
114 struct perf_event;
115 struct pmu;
116
117 extern struct pmu perf_ops_bp;
118 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
119 int *gen_len, int *gen_type);
120 extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
121 extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
122 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
123 unsigned long val, void *data);
124
125 extern u8 arch_get_debug_arch(void);
126 extern u8 arch_get_max_wp_len(void);
127 extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
128
129 int arch_install_hw_breakpoint(struct perf_event *bp);
130 void arch_uninstall_hw_breakpoint(struct perf_event *bp);
131 void hw_breakpoint_pmu_read(struct perf_event *bp);
132 int hw_breakpoint_slots(int type);
133
134 #else
clear_ptrace_hw_breakpoint(struct task_struct * tsk)135 static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
136
137 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
138 #endif /* __KERNEL__ */
139 #endif /* _ARM_HW_BREAKPOINT_H */
140