1 /*
2 * linux/arch/arm/mach-omap2/clock.c
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/clk-provider.h>
25 #include <linux/io.h>
26 #include <linux/bitops.h>
27 #include <linux/of_address.h>
28 #include <asm/cpu.h>
29
30 #include <trace/events/power.h>
31
32 #include "soc.h"
33 #include "clockdomain.h"
34 #include "clock.h"
35 #include "cm.h"
36 #include "cm2xxx.h"
37 #include "cm3xxx.h"
38 #include "cm-regbits-24xx.h"
39 #include "cm-regbits-34xx.h"
40 #include "common.h"
41
42 u16 cpu_mask;
43
44 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
45 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000
46 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
47 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
48 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
49
50 /*
51 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
52 * From device data manual section 4.3 "DPLL and DLL Specifications".
53 */
54 #define OMAP3PLUS_DPLL_FINT_MIN 32000
55 #define OMAP3PLUS_DPLL_FINT_MAX 52000000
56
57 static struct ti_clk_ll_ops omap_clk_ll_ops = {
58 .clkdm_clk_enable = clkdm_clk_enable,
59 .clkdm_clk_disable = clkdm_clk_disable,
60 .cm_wait_module_ready = omap_cm_wait_module_ready,
61 .cm_split_idlest_reg = cm_split_idlest_reg,
62 };
63
64 /**
65 * omap2_clk_setup_ll_ops - setup clock driver low-level ops
66 *
67 * Sets up clock driver low-level platform ops. These are needed
68 * for register accesses and various other misc platform operations.
69 * Returns 0 on success, -EBUSY if low level ops have been registered
70 * already.
71 */
omap2_clk_setup_ll_ops(void)72 int __init omap2_clk_setup_ll_ops(void)
73 {
74 return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
75 }
76
77 /*
78 * OMAP2+ specific clock functions
79 */
80
81 /* Private functions */
82
83 /* Public functions */
84
85 /**
86 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
87 * @clk: OMAP clock struct ptr to use
88 *
89 * Convert a clockdomain name stored in a struct clk 'clk' into a
90 * clockdomain pointer, and save it into the struct clk. Intended to be
91 * called during clk_register(). No return value.
92 */
omap2_init_clk_clkdm(struct clk_hw * hw)93 void omap2_init_clk_clkdm(struct clk_hw *hw)
94 {
95 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
96 struct clockdomain *clkdm;
97 const char *clk_name;
98
99 if (!clk->clkdm_name)
100 return;
101
102 clk_name = __clk_get_name(hw->clk);
103
104 clkdm = clkdm_lookup(clk->clkdm_name);
105 if (clkdm) {
106 pr_debug("clock: associated clk %s to clkdm %s\n",
107 clk_name, clk->clkdm_name);
108 clk->clkdm = clkdm;
109 } else {
110 pr_debug("clock: could not associate clk %s to clkdm %s\n",
111 clk_name, clk->clkdm_name);
112 }
113 }
114
115 static int __initdata mpurate;
116
117 /*
118 * By default we use the rate set by the bootloader.
119 * You can override this with mpurate= cmdline option.
120 */
omap_clk_setup(char * str)121 static int __init omap_clk_setup(char *str)
122 {
123 get_option(&str, &mpurate);
124
125 if (!mpurate)
126 return 1;
127
128 if (mpurate < 1000)
129 mpurate *= 1000000;
130
131 return 1;
132 }
133 __setup("mpurate=", omap_clk_setup);
134
135 /**
136 * omap2_clk_print_new_rates - print summary of current clock tree rates
137 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
138 * @core_ck_name: clk name for the on-chip CORE_CLK
139 * @mpu_ck_name: clk name for the ARM MPU clock
140 *
141 * Prints a short message to the console with the HFCLKIN oscillator
142 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
143 * Called by the boot-time MPU rate switching code. XXX This is intended
144 * to be handled by the OPP layer code in the near future and should be
145 * removed from the clock code. No return value.
146 */
omap2_clk_print_new_rates(const char * hfclkin_ck_name,const char * core_ck_name,const char * mpu_ck_name)147 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
148 const char *core_ck_name,
149 const char *mpu_ck_name)
150 {
151 struct clk *hfclkin_ck, *core_ck, *mpu_ck;
152 unsigned long hfclkin_rate;
153
154 mpu_ck = clk_get(NULL, mpu_ck_name);
155 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
156 return;
157
158 core_ck = clk_get(NULL, core_ck_name);
159 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
160 return;
161
162 hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
163 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
164 return;
165
166 hfclkin_rate = clk_get_rate(hfclkin_ck);
167
168 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
169 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
170 (clk_get_rate(core_ck) / 1000000),
171 (clk_get_rate(mpu_ck) / 1000000));
172 }
173
174 /**
175 * ti_clk_init_features - init clock features struct for the SoC
176 *
177 * Initializes the clock features struct based on the SoC type.
178 */
ti_clk_init_features(void)179 void __init ti_clk_init_features(void)
180 {
181 struct ti_clk_features features = { 0 };
182 /* Fint setup for DPLLs */
183 if (cpu_is_omap3430()) {
184 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
185 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
186 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
187 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
188 } else {
189 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
190 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
191 }
192
193 /* Bypass value setup for DPLLs */
194 if (cpu_is_omap24xx()) {
195 features.dpll_bypass_vals |=
196 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
197 (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
198 } else if (cpu_is_omap34xx()) {
199 features.dpll_bypass_vals |=
200 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
201 (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
202 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
203 soc_is_omap54xx() || soc_is_dra7xx()) {
204 features.dpll_bypass_vals |=
205 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
206 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
207 (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
208 }
209
210 /* Jitter correction only available on OMAP343X */
211 if (cpu_is_omap343x())
212 features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
213
214 /* Idlest value for interface clocks.
215 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
216 * 34xx reverses this, just to keep us on our toes
217 * AM35xx uses both, depending on the module.
218 */
219 if (cpu_is_omap24xx())
220 features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
221 else if (cpu_is_omap34xx())
222 features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
223
224 /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
225 if (omap_rev() == OMAP3430_REV_ES1_0)
226 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
227
228 ti_clk_setup_features(&features);
229 }
230