1 /*
2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
3 *
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
6 * Tony Lindgren
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/string.h>
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/mtd/onenand_regs.h>
17 #include <linux/io.h>
18 #include <linux/omap-gpmc.h>
19 #include <linux/platform_data/mtd-onenand-omap2.h>
20 #include <linux/err.h>
21
22 #include <asm/mach/flash.h>
23
24 #include "soc.h"
25
26 #define ONENAND_IO_SIZE SZ_128K
27
28 #define ONENAND_FLAG_SYNCREAD (1 << 0)
29 #define ONENAND_FLAG_SYNCWRITE (1 << 1)
30 #define ONENAND_FLAG_HF (1 << 2)
31 #define ONENAND_FLAG_VHF (1 << 3)
32
33 static unsigned onenand_flags;
34 static unsigned latency;
35
36 static struct omap_onenand_platform_data *gpmc_onenand_data;
37
38 static struct resource gpmc_onenand_resource = {
39 .flags = IORESOURCE_MEM,
40 };
41
42 static struct platform_device gpmc_onenand_device = {
43 .name = "omap2-onenand",
44 .id = -1,
45 .num_resources = 1,
46 .resource = &gpmc_onenand_resource,
47 };
48
49 static struct gpmc_settings onenand_async = {
50 .device_width = GPMC_DEVWIDTH_16BIT,
51 .mux_add_data = GPMC_MUX_AD,
52 };
53
54 static struct gpmc_settings onenand_sync = {
55 .burst_read = true,
56 .burst_wrap = true,
57 .burst_len = GPMC_BURST_16,
58 .device_width = GPMC_DEVWIDTH_16BIT,
59 .mux_add_data = GPMC_MUX_AD,
60 .wait_pin = 0,
61 };
62
omap2_onenand_calc_async_timings(struct gpmc_timings * t)63 static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
64 {
65 struct gpmc_device_timings dev_t;
66 const int t_cer = 15;
67 const int t_avdp = 12;
68 const int t_aavdh = 7;
69 const int t_ce = 76;
70 const int t_aa = 76;
71 const int t_oe = 20;
72 const int t_cez = 20; /* max of t_cez, t_oez */
73 const int t_wpl = 40;
74 const int t_wph = 30;
75
76 memset(&dev_t, 0, sizeof(dev_t));
77
78 dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
79 dev_t.t_avdp_w = dev_t.t_avdp_r;
80 dev_t.t_aavdh = t_aavdh * 1000;
81 dev_t.t_aa = t_aa * 1000;
82 dev_t.t_ce = t_ce * 1000;
83 dev_t.t_oe = t_oe * 1000;
84 dev_t.t_cez_r = t_cez * 1000;
85 dev_t.t_cez_w = dev_t.t_cez_r;
86 dev_t.t_wpl = t_wpl * 1000;
87 dev_t.t_wph = t_wph * 1000;
88
89 gpmc_calc_timings(t, &onenand_async, &dev_t);
90 }
91
omap2_onenand_set_async_mode(void __iomem * onenand_base)92 static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
93 {
94 u32 reg;
95
96 /* Ensure sync read and sync write are disabled */
97 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
98 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
99 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
100 }
101
set_onenand_cfg(void __iomem * onenand_base)102 static void set_onenand_cfg(void __iomem *onenand_base)
103 {
104 u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
105
106 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
107 ONENAND_SYS_CFG1_BL_16;
108 if (onenand_flags & ONENAND_FLAG_SYNCREAD)
109 reg |= ONENAND_SYS_CFG1_SYNC_READ;
110 else
111 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
112 if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
113 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
114 else
115 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
116 if (onenand_flags & ONENAND_FLAG_HF)
117 reg |= ONENAND_SYS_CFG1_HF;
118 else
119 reg &= ~ONENAND_SYS_CFG1_HF;
120 if (onenand_flags & ONENAND_FLAG_VHF)
121 reg |= ONENAND_SYS_CFG1_VHF;
122 else
123 reg &= ~ONENAND_SYS_CFG1_VHF;
124
125 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
126 }
127
omap2_onenand_get_freq(struct omap_onenand_platform_data * cfg,void __iomem * onenand_base)128 static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
129 void __iomem *onenand_base)
130 {
131 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
132 int freq;
133
134 switch ((ver >> 4) & 0xf) {
135 case 0:
136 freq = 40;
137 break;
138 case 1:
139 freq = 54;
140 break;
141 case 2:
142 freq = 66;
143 break;
144 case 3:
145 freq = 83;
146 break;
147 case 4:
148 freq = 104;
149 break;
150 default:
151 pr_err("onenand rate not detected, bad GPMC async timings?\n");
152 freq = 0;
153 }
154
155 return freq;
156 }
157
omap2_onenand_calc_sync_timings(struct gpmc_timings * t,unsigned int flags,int freq)158 static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
159 unsigned int flags,
160 int freq)
161 {
162 struct gpmc_device_timings dev_t;
163 const int t_cer = 15;
164 const int t_avdp = 12;
165 const int t_cez = 20; /* max of t_cez, t_oez */
166 const int t_wpl = 40;
167 const int t_wph = 30;
168 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
169 int div, gpmc_clk_ns;
170
171 if (flags & ONENAND_SYNC_READ)
172 onenand_flags = ONENAND_FLAG_SYNCREAD;
173 else if (flags & ONENAND_SYNC_READWRITE)
174 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
175
176 switch (freq) {
177 case 104:
178 min_gpmc_clk_period = 9600; /* 104 MHz */
179 t_ces = 3;
180 t_avds = 4;
181 t_avdh = 2;
182 t_ach = 3;
183 t_aavdh = 6;
184 t_rdyo = 6;
185 break;
186 case 83:
187 min_gpmc_clk_period = 12000; /* 83 MHz */
188 t_ces = 5;
189 t_avds = 4;
190 t_avdh = 2;
191 t_ach = 6;
192 t_aavdh = 6;
193 t_rdyo = 9;
194 break;
195 case 66:
196 min_gpmc_clk_period = 15000; /* 66 MHz */
197 t_ces = 6;
198 t_avds = 5;
199 t_avdh = 2;
200 t_ach = 6;
201 t_aavdh = 6;
202 t_rdyo = 11;
203 break;
204 default:
205 min_gpmc_clk_period = 18500; /* 54 MHz */
206 t_ces = 7;
207 t_avds = 7;
208 t_avdh = 7;
209 t_ach = 9;
210 t_aavdh = 7;
211 t_rdyo = 15;
212 onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
213 break;
214 }
215
216 div = gpmc_calc_divider(min_gpmc_clk_period);
217 gpmc_clk_ns = gpmc_ticks_to_ns(div);
218 if (gpmc_clk_ns < 15) /* >66MHz */
219 onenand_flags |= ONENAND_FLAG_HF;
220 else
221 onenand_flags &= ~ONENAND_FLAG_HF;
222 if (gpmc_clk_ns < 12) /* >83MHz */
223 onenand_flags |= ONENAND_FLAG_VHF;
224 else
225 onenand_flags &= ~ONENAND_FLAG_VHF;
226 if (onenand_flags & ONENAND_FLAG_VHF)
227 latency = 8;
228 else if (onenand_flags & ONENAND_FLAG_HF)
229 latency = 6;
230 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
231 latency = 3;
232 else
233 latency = 4;
234
235 /* Set synchronous read timings */
236 memset(&dev_t, 0, sizeof(dev_t));
237
238 if (onenand_flags & ONENAND_FLAG_SYNCREAD)
239 onenand_sync.sync_read = true;
240 if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
241 onenand_sync.sync_write = true;
242 onenand_sync.burst_write = true;
243 } else {
244 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
245 dev_t.t_wpl = t_wpl * 1000;
246 dev_t.t_wph = t_wph * 1000;
247 dev_t.t_aavdh = t_aavdh * 1000;
248 }
249 dev_t.ce_xdelay = true;
250 dev_t.avd_xdelay = true;
251 dev_t.oe_xdelay = true;
252 dev_t.we_xdelay = true;
253 dev_t.clk = min_gpmc_clk_period;
254 dev_t.t_bacc = dev_t.clk;
255 dev_t.t_ces = t_ces * 1000;
256 dev_t.t_avds = t_avds * 1000;
257 dev_t.t_avdh = t_avdh * 1000;
258 dev_t.t_ach = t_ach * 1000;
259 dev_t.cyc_iaa = (latency + 1);
260 dev_t.t_cez_r = t_cez * 1000;
261 dev_t.t_cez_w = dev_t.t_cez_r;
262 dev_t.cyc_aavdh_oe = 1;
263 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
264
265 gpmc_calc_timings(t, &onenand_sync, &dev_t);
266 }
267
omap2_onenand_setup_async(void __iomem * onenand_base)268 static int omap2_onenand_setup_async(void __iomem *onenand_base)
269 {
270 struct gpmc_timings t;
271 int ret;
272
273 /*
274 * Note that we need to keep sync_write set for the call to
275 * omap2_onenand_set_async_mode() to work to detect the onenand
276 * supported clock rate for the sync timings.
277 */
278 if (gpmc_onenand_data->of_node) {
279 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
280 &onenand_async);
281 if (onenand_async.sync_read || onenand_async.sync_write) {
282 if (onenand_async.sync_write)
283 gpmc_onenand_data->flags |=
284 ONENAND_SYNC_READWRITE;
285 else
286 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
287 onenand_async.sync_read = false;
288 }
289 }
290
291 onenand_async.sync_write = true;
292 omap2_onenand_calc_async_timings(&t);
293
294 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
295 if (ret < 0)
296 return ret;
297
298 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
299 if (ret < 0)
300 return ret;
301
302 omap2_onenand_set_async_mode(onenand_base);
303
304 return 0;
305 }
306
omap2_onenand_setup_sync(void __iomem * onenand_base,int * freq_ptr)307 static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
308 {
309 int ret, freq = *freq_ptr;
310 struct gpmc_timings t;
311
312 if (!freq) {
313 /* Very first call freq is not known */
314 freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
315 if (!freq)
316 return -ENODEV;
317 set_onenand_cfg(onenand_base);
318 }
319
320 if (gpmc_onenand_data->of_node) {
321 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
322 &onenand_sync);
323 } else {
324 /*
325 * FIXME: Appears to be legacy code from initial ONENAND commit.
326 * Unclear what boards this is for and if this can be removed.
327 */
328 if (!cpu_is_omap34xx())
329 onenand_sync.wait_on_read = true;
330 }
331
332 omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
333
334 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
335 if (ret < 0)
336 return ret;
337
338 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
339 if (ret < 0)
340 return ret;
341
342 set_onenand_cfg(onenand_base);
343
344 *freq_ptr = freq;
345
346 return 0;
347 }
348
gpmc_onenand_setup(void __iomem * onenand_base,int * freq_ptr)349 static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
350 {
351 struct device *dev = &gpmc_onenand_device.dev;
352 unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
353 int ret;
354
355 ret = omap2_onenand_setup_async(onenand_base);
356 if (ret) {
357 dev_err(dev, "unable to set to async mode\n");
358 return ret;
359 }
360
361 if (!(gpmc_onenand_data->flags & l))
362 return 0;
363
364 ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
365 if (ret)
366 dev_err(dev, "unable to set to sync mode\n");
367 return ret;
368 }
369
gpmc_onenand_init(struct omap_onenand_platform_data * _onenand_data)370 int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
371 {
372 int err;
373 struct device *dev = &gpmc_onenand_device.dev;
374
375 gpmc_onenand_data = _onenand_data;
376 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
377 gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
378
379 if (cpu_is_omap24xx() &&
380 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
381 dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
382 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
383 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
384 }
385
386 if (cpu_is_omap34xx())
387 gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
388 else
389 gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
390
391 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
392 (unsigned long *)&gpmc_onenand_resource.start);
393 if (err < 0) {
394 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
395 gpmc_onenand_data->cs, err);
396 return err;
397 }
398
399 gpmc_onenand_resource.end = gpmc_onenand_resource.start +
400 ONENAND_IO_SIZE - 1;
401
402 err = platform_device_register(&gpmc_onenand_device);
403 if (err) {
404 dev_err(dev, "Unable to register OneNAND device\n");
405 gpmc_cs_free(gpmc_onenand_data->cs);
406 }
407
408 return err;
409 }
410