1/* 2 * Secondary CPU startup routine source file. 3 * 4 * Copyright (C) 2009-2014 Texas Instruments, Inc. 5 * 6 * Author: 7 * Santosh Shilimkar <santosh.shilimkar@ti.com> 8 * 9 * Interface functions needed for the SMP. This file is based on arm 10 * realview smp platform. 11 * Copyright (c) 2003 ARM Limited. 12 * 13 * This program is free software,you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18#include <linux/linkage.h> 19#include <linux/init.h> 20#include <asm/assembler.h> 21 22#include "omap44xx.h" 23 24/* Physical address needed since MMU not enabled yet on secondary core */ 25#define AUX_CORE_BOOT0_PA 0x48281800 26#define API_HYP_ENTRY 0x102 27 28/* 29 * OMAP5 specific entry point for secondary CPU to jump from ROM 30 * code. This routine also provides a holding flag into which 31 * secondary core is held until we're ready for it to initialise. 32 * The primary core will update this flag using a hardware 33 * register AuxCoreBoot0. 34 */ 35ENTRY(omap5_secondary_startup) 36wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 37 ldr r0, [r2] 38 mov r0, r0, lsr #5 39 mrc p15, 0, r4, c0, c0, 5 40 and r4, r4, #0x0f 41 cmp r0, r4 42 bne wait 43 b secondary_startup 44ENDPROC(omap5_secondary_startup) 45/* 46 * Same as omap5_secondary_startup except we call into the ROM to 47 * enable HYP mode first. This is called instead of 48 * omap5_secondary_startup if the primary CPU was put into HYP mode by 49 * the boot loader. 50 */ 51ENTRY(omap5_secondary_hyp_startup) 52wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 53 ldr r0, [r2] 54 mov r0, r0, lsr #5 55 mrc p15, 0, r4, c0, c0, 5 56 and r4, r4, #0x0f 57 cmp r0, r4 58 bne wait_2 59 ldr r12, =API_HYP_ENTRY 60 badr r0, hyp_boot 61 smc #0 62hyp_boot: 63 b secondary_startup 64ENDPROC(omap5_secondary_hyp_startup) 65/* 66 * OMAP4 specific entry point for secondary CPU to jump from ROM 67 * code. This routine also provides a holding flag into which 68 * secondary core is held until we're ready for it to initialise. 69 * The primary core will update this flag using a hardware 70 * register AuxCoreBoot0. 71 */ 72ENTRY(omap4_secondary_startup) 73hold: ldr r12,=0x103 74 dsb 75 smc #0 @ read from AuxCoreBoot0 76 mov r0, r0, lsr #9 77 mrc p15, 0, r4, c0, c0, 5 78 and r4, r4, #0x0f 79 cmp r0, r4 80 bne hold 81 82 /* 83 * we've been released from the wait loop,secondary_stack 84 * should now contain the SVC stack for this core 85 */ 86 b secondary_startup 87ENDPROC(omap4_secondary_startup) 88 89ENTRY(omap4460_secondary_startup) 90hold_2: ldr r12,=0x103 91 dsb 92 smc #0 @ read from AuxCoreBoot0 93 mov r0, r0, lsr #9 94 mrc p15, 0, r4, c0, c0, 5 95 and r4, r4, #0x0f 96 cmp r0, r4 97 bne hold_2 98 99 /* 100 * GIC distributor control register has changed between 101 * CortexA9 r1pX and r2pX. The Control Register secure 102 * banked version is now composed of 2 bits: 103 * bit 0 == Secure Enable 104 * bit 1 == Non-Secure Enable 105 * The Non-Secure banked register has not changed 106 * Because the ROM Code is based on the r1pX GIC, the CPU1 107 * GIC restoration will cause a problem to CPU0 Non-Secure SW. 108 * The workaround must be: 109 * 1) Before doing the CPU1 wakeup, CPU0 must disable 110 * the GIC distributor 111 * 2) CPU1 must re-enable the GIC distributor on 112 * it's wakeup path. 113 */ 114 ldr r1, =OMAP44XX_GIC_DIST_BASE 115 ldr r0, [r1] 116 orr r0, #1 117 str r0, [r1] 118 119 /* 120 * we've been released from the wait loop,secondary_stack 121 * should now contain the SVC stack for this core 122 */ 123 b secondary_startup 124ENDPROC(omap4460_secondary_startup) 125