1 /*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
17
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/hsmmc-omap.h>
22
23 #include <linux/omap-dma.h>
24 #include "l3_3xxx.h"
25 #include "l4_3xxx.h"
26 #include <linux/platform_data/asoc-ti-mcbsp.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/iommu-omap.h>
29 #include <plat/dmtimer.h>
30
31 #include "soc.h"
32 #include "omap_hwmod.h"
33 #include "omap_hwmod_common_data.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
36
37 #include "i2c.h"
38 #include "wd_timer.h"
39 #include "serial.h"
40
41 /*
42 * OMAP3xxx hardware module integration data
43 *
44 * All of the data in this section should be autogeneratable from the
45 * TI hardware database or other technical documentation. Data that
46 * is driver-specific or driver-kernel integration-specific belongs
47 * elsewhere.
48 */
49
50 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
51
52 /*
53 * IP blocks
54 */
55
56 /* L3 */
57 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
58 { .irq = 9 + OMAP_INTC_START, },
59 { .irq = 10 + OMAP_INTC_START, },
60 { .irq = -1 },
61 };
62
63 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
64 .name = "l3_main",
65 .class = &l3_hwmod_class,
66 .mpu_irqs = omap3xxx_l3_main_irqs,
67 .flags = HWMOD_NO_IDLEST,
68 };
69
70 /* L4 CORE */
71 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
72 .name = "l4_core",
73 .class = &l4_hwmod_class,
74 .flags = HWMOD_NO_IDLEST,
75 };
76
77 /* L4 PER */
78 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
79 .name = "l4_per",
80 .class = &l4_hwmod_class,
81 .flags = HWMOD_NO_IDLEST,
82 };
83
84 /* L4 WKUP */
85 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
86 .name = "l4_wkup",
87 .class = &l4_hwmod_class,
88 .flags = HWMOD_NO_IDLEST,
89 };
90
91 /* L4 SEC */
92 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
93 .name = "l4_sec",
94 .class = &l4_hwmod_class,
95 .flags = HWMOD_NO_IDLEST,
96 };
97
98 /* MPU */
99 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
100 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
101 { .irq = -1 }
102 };
103
104 static struct omap_hwmod omap3xxx_mpu_hwmod = {
105 .name = "mpu",
106 .mpu_irqs = omap3xxx_mpu_irqs,
107 .class = &mpu_hwmod_class,
108 .main_clk = "arm_fck",
109 };
110
111 /* IVA2 (IVA2) */
112 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
113 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
114 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
115 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
116 };
117
118 static struct omap_hwmod omap3xxx_iva_hwmod = {
119 .name = "iva",
120 .class = &iva_hwmod_class,
121 .clkdm_name = "iva2_clkdm",
122 .rst_lines = omap3xxx_iva_resets,
123 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
124 .main_clk = "iva2_ck",
125 .prcm = {
126 .omap2 = {
127 .module_offs = OMAP3430_IVA2_MOD,
128 .prcm_reg_id = 1,
129 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
130 .idlest_reg_id = 1,
131 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
132 }
133 },
134 };
135
136 /*
137 * 'debugss' class
138 * debug and emulation sub system
139 */
140
141 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
142 .name = "debugss",
143 };
144
145 /* debugss */
146 static struct omap_hwmod omap3xxx_debugss_hwmod = {
147 .name = "debugss",
148 .class = &omap3xxx_debugss_hwmod_class,
149 .clkdm_name = "emu_clkdm",
150 .main_clk = "emu_src_ck",
151 .flags = HWMOD_NO_IDLEST,
152 };
153
154 /* timer class */
155 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
156 .rev_offs = 0x0000,
157 .sysc_offs = 0x0010,
158 .syss_offs = 0x0014,
159 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
160 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
161 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
162 SYSS_HAS_RESET_STATUS),
163 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
164 .clockact = CLOCKACT_TEST_ICLK,
165 .sysc_fields = &omap_hwmod_sysc_type1,
166 };
167
168 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
169 .name = "timer",
170 .sysc = &omap3xxx_timer_sysc,
171 };
172
173 /* secure timers dev attribute */
174 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
175 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
176 };
177
178 /* always-on timers dev attribute */
179 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
180 .timer_capability = OMAP_TIMER_ALWON,
181 };
182
183 /* pwm timers dev attribute */
184 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
185 .timer_capability = OMAP_TIMER_HAS_PWM,
186 };
187
188 /* timers with DSP interrupt dev attribute */
189 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
190 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
191 };
192
193 /* pwm timers with DSP interrupt dev attribute */
194 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
195 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
196 };
197
198 /* timer1 */
199 static struct omap_hwmod omap3xxx_timer1_hwmod = {
200 .name = "timer1",
201 .mpu_irqs = omap2_timer1_mpu_irqs,
202 .main_clk = "gpt1_fck",
203 .prcm = {
204 .omap2 = {
205 .prcm_reg_id = 1,
206 .module_bit = OMAP3430_EN_GPT1_SHIFT,
207 .module_offs = WKUP_MOD,
208 .idlest_reg_id = 1,
209 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
210 },
211 },
212 .dev_attr = &capability_alwon_dev_attr,
213 .class = &omap3xxx_timer_hwmod_class,
214 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
215 };
216
217 /* timer2 */
218 static struct omap_hwmod omap3xxx_timer2_hwmod = {
219 .name = "timer2",
220 .mpu_irqs = omap2_timer2_mpu_irqs,
221 .main_clk = "gpt2_fck",
222 .prcm = {
223 .omap2 = {
224 .prcm_reg_id = 1,
225 .module_bit = OMAP3430_EN_GPT2_SHIFT,
226 .module_offs = OMAP3430_PER_MOD,
227 .idlest_reg_id = 1,
228 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
229 },
230 },
231 .class = &omap3xxx_timer_hwmod_class,
232 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
233 };
234
235 /* timer3 */
236 static struct omap_hwmod omap3xxx_timer3_hwmod = {
237 .name = "timer3",
238 .mpu_irqs = omap2_timer3_mpu_irqs,
239 .main_clk = "gpt3_fck",
240 .prcm = {
241 .omap2 = {
242 .prcm_reg_id = 1,
243 .module_bit = OMAP3430_EN_GPT3_SHIFT,
244 .module_offs = OMAP3430_PER_MOD,
245 .idlest_reg_id = 1,
246 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
247 },
248 },
249 .class = &omap3xxx_timer_hwmod_class,
250 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
251 };
252
253 /* timer4 */
254 static struct omap_hwmod omap3xxx_timer4_hwmod = {
255 .name = "timer4",
256 .mpu_irqs = omap2_timer4_mpu_irqs,
257 .main_clk = "gpt4_fck",
258 .prcm = {
259 .omap2 = {
260 .prcm_reg_id = 1,
261 .module_bit = OMAP3430_EN_GPT4_SHIFT,
262 .module_offs = OMAP3430_PER_MOD,
263 .idlest_reg_id = 1,
264 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
265 },
266 },
267 .class = &omap3xxx_timer_hwmod_class,
268 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
269 };
270
271 /* timer5 */
272 static struct omap_hwmod omap3xxx_timer5_hwmod = {
273 .name = "timer5",
274 .mpu_irqs = omap2_timer5_mpu_irqs,
275 .main_clk = "gpt5_fck",
276 .prcm = {
277 .omap2 = {
278 .prcm_reg_id = 1,
279 .module_bit = OMAP3430_EN_GPT5_SHIFT,
280 .module_offs = OMAP3430_PER_MOD,
281 .idlest_reg_id = 1,
282 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
283 },
284 },
285 .dev_attr = &capability_dsp_dev_attr,
286 .class = &omap3xxx_timer_hwmod_class,
287 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
288 };
289
290 /* timer6 */
291 static struct omap_hwmod omap3xxx_timer6_hwmod = {
292 .name = "timer6",
293 .mpu_irqs = omap2_timer6_mpu_irqs,
294 .main_clk = "gpt6_fck",
295 .prcm = {
296 .omap2 = {
297 .prcm_reg_id = 1,
298 .module_bit = OMAP3430_EN_GPT6_SHIFT,
299 .module_offs = OMAP3430_PER_MOD,
300 .idlest_reg_id = 1,
301 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
302 },
303 },
304 .dev_attr = &capability_dsp_dev_attr,
305 .class = &omap3xxx_timer_hwmod_class,
306 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
307 };
308
309 /* timer7 */
310 static struct omap_hwmod omap3xxx_timer7_hwmod = {
311 .name = "timer7",
312 .mpu_irqs = omap2_timer7_mpu_irqs,
313 .main_clk = "gpt7_fck",
314 .prcm = {
315 .omap2 = {
316 .prcm_reg_id = 1,
317 .module_bit = OMAP3430_EN_GPT7_SHIFT,
318 .module_offs = OMAP3430_PER_MOD,
319 .idlest_reg_id = 1,
320 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
321 },
322 },
323 .dev_attr = &capability_dsp_dev_attr,
324 .class = &omap3xxx_timer_hwmod_class,
325 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
326 };
327
328 /* timer8 */
329 static struct omap_hwmod omap3xxx_timer8_hwmod = {
330 .name = "timer8",
331 .mpu_irqs = omap2_timer8_mpu_irqs,
332 .main_clk = "gpt8_fck",
333 .prcm = {
334 .omap2 = {
335 .prcm_reg_id = 1,
336 .module_bit = OMAP3430_EN_GPT8_SHIFT,
337 .module_offs = OMAP3430_PER_MOD,
338 .idlest_reg_id = 1,
339 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
340 },
341 },
342 .dev_attr = &capability_dsp_pwm_dev_attr,
343 .class = &omap3xxx_timer_hwmod_class,
344 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
345 };
346
347 /* timer9 */
348 static struct omap_hwmod omap3xxx_timer9_hwmod = {
349 .name = "timer9",
350 .mpu_irqs = omap2_timer9_mpu_irqs,
351 .main_clk = "gpt9_fck",
352 .prcm = {
353 .omap2 = {
354 .prcm_reg_id = 1,
355 .module_bit = OMAP3430_EN_GPT9_SHIFT,
356 .module_offs = OMAP3430_PER_MOD,
357 .idlest_reg_id = 1,
358 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
359 },
360 },
361 .dev_attr = &capability_pwm_dev_attr,
362 .class = &omap3xxx_timer_hwmod_class,
363 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
364 };
365
366 /* timer10 */
367 static struct omap_hwmod omap3xxx_timer10_hwmod = {
368 .name = "timer10",
369 .mpu_irqs = omap2_timer10_mpu_irqs,
370 .main_clk = "gpt10_fck",
371 .prcm = {
372 .omap2 = {
373 .prcm_reg_id = 1,
374 .module_bit = OMAP3430_EN_GPT10_SHIFT,
375 .module_offs = CORE_MOD,
376 .idlest_reg_id = 1,
377 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
378 },
379 },
380 .dev_attr = &capability_pwm_dev_attr,
381 .class = &omap3xxx_timer_hwmod_class,
382 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
383 };
384
385 /* timer11 */
386 static struct omap_hwmod omap3xxx_timer11_hwmod = {
387 .name = "timer11",
388 .mpu_irqs = omap2_timer11_mpu_irqs,
389 .main_clk = "gpt11_fck",
390 .prcm = {
391 .omap2 = {
392 .prcm_reg_id = 1,
393 .module_bit = OMAP3430_EN_GPT11_SHIFT,
394 .module_offs = CORE_MOD,
395 .idlest_reg_id = 1,
396 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
397 },
398 },
399 .dev_attr = &capability_pwm_dev_attr,
400 .class = &omap3xxx_timer_hwmod_class,
401 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
402 };
403
404 /* timer12 */
405 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
406 { .irq = 95 + OMAP_INTC_START, },
407 { .irq = -1 },
408 };
409
410 static struct omap_hwmod omap3xxx_timer12_hwmod = {
411 .name = "timer12",
412 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
413 .main_clk = "gpt12_fck",
414 .prcm = {
415 .omap2 = {
416 .prcm_reg_id = 1,
417 .module_bit = OMAP3430_EN_GPT12_SHIFT,
418 .module_offs = WKUP_MOD,
419 .idlest_reg_id = 1,
420 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
421 },
422 },
423 .dev_attr = &capability_secure_dev_attr,
424 .class = &omap3xxx_timer_hwmod_class,
425 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
426 };
427
428 /*
429 * 'wd_timer' class
430 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
431 * overflow condition
432 */
433
434 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
435 .rev_offs = 0x0000,
436 .sysc_offs = 0x0010,
437 .syss_offs = 0x0014,
438 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
439 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
440 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
441 SYSS_HAS_RESET_STATUS),
442 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
443 .sysc_fields = &omap_hwmod_sysc_type1,
444 };
445
446 /* I2C common */
447 static struct omap_hwmod_class_sysconfig i2c_sysc = {
448 .rev_offs = 0x00,
449 .sysc_offs = 0x20,
450 .syss_offs = 0x10,
451 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
452 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
453 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
454 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
455 .clockact = CLOCKACT_TEST_ICLK,
456 .sysc_fields = &omap_hwmod_sysc_type1,
457 };
458
459 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
460 .name = "wd_timer",
461 .sysc = &omap3xxx_wd_timer_sysc,
462 .pre_shutdown = &omap2_wd_timer_disable,
463 .reset = &omap2_wd_timer_reset,
464 };
465
466 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
467 .name = "wd_timer2",
468 .class = &omap3xxx_wd_timer_hwmod_class,
469 .main_clk = "wdt2_fck",
470 .prcm = {
471 .omap2 = {
472 .prcm_reg_id = 1,
473 .module_bit = OMAP3430_EN_WDT2_SHIFT,
474 .module_offs = WKUP_MOD,
475 .idlest_reg_id = 1,
476 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
477 },
478 },
479 /*
480 * XXX: Use software supervised mode, HW supervised smartidle seems to
481 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
482 */
483 .flags = HWMOD_SWSUP_SIDLE,
484 };
485
486 /* UART1 */
487 static struct omap_hwmod omap3xxx_uart1_hwmod = {
488 .name = "uart1",
489 .mpu_irqs = omap2_uart1_mpu_irqs,
490 .sdma_reqs = omap2_uart1_sdma_reqs,
491 .main_clk = "uart1_fck",
492 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
493 .prcm = {
494 .omap2 = {
495 .module_offs = CORE_MOD,
496 .prcm_reg_id = 1,
497 .module_bit = OMAP3430_EN_UART1_SHIFT,
498 .idlest_reg_id = 1,
499 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
500 },
501 },
502 .class = &omap2_uart_class,
503 };
504
505 /* UART2 */
506 static struct omap_hwmod omap3xxx_uart2_hwmod = {
507 .name = "uart2",
508 .mpu_irqs = omap2_uart2_mpu_irqs,
509 .sdma_reqs = omap2_uart2_sdma_reqs,
510 .main_clk = "uart2_fck",
511 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
512 .prcm = {
513 .omap2 = {
514 .module_offs = CORE_MOD,
515 .prcm_reg_id = 1,
516 .module_bit = OMAP3430_EN_UART2_SHIFT,
517 .idlest_reg_id = 1,
518 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
519 },
520 },
521 .class = &omap2_uart_class,
522 };
523
524 /* UART3 */
525 static struct omap_hwmod omap3xxx_uart3_hwmod = {
526 .name = "uart3",
527 .mpu_irqs = omap2_uart3_mpu_irqs,
528 .sdma_reqs = omap2_uart3_sdma_reqs,
529 .main_clk = "uart3_fck",
530 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
531 HWMOD_SWSUP_SIDLE,
532 .prcm = {
533 .omap2 = {
534 .module_offs = OMAP3430_PER_MOD,
535 .prcm_reg_id = 1,
536 .module_bit = OMAP3430_EN_UART3_SHIFT,
537 .idlest_reg_id = 1,
538 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
539 },
540 },
541 .class = &omap2_uart_class,
542 };
543
544 /* UART4 */
545 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
546 { .irq = 80 + OMAP_INTC_START, },
547 { .irq = -1 },
548 };
549
550 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
551 { .name = "rx", .dma_req = 82, },
552 { .name = "tx", .dma_req = 81, },
553 { .dma_req = -1 }
554 };
555
556 static struct omap_hwmod omap36xx_uart4_hwmod = {
557 .name = "uart4",
558 .mpu_irqs = uart4_mpu_irqs,
559 .sdma_reqs = uart4_sdma_reqs,
560 .main_clk = "uart4_fck",
561 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
562 .prcm = {
563 .omap2 = {
564 .module_offs = OMAP3430_PER_MOD,
565 .prcm_reg_id = 1,
566 .module_bit = OMAP3630_EN_UART4_SHIFT,
567 .idlest_reg_id = 1,
568 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
569 },
570 },
571 .class = &omap2_uart_class,
572 };
573
574 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
575 { .irq = 84 + OMAP_INTC_START, },
576 { .irq = -1 },
577 };
578
579 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
580 { .name = "rx", .dma_req = 55, },
581 { .name = "tx", .dma_req = 54, },
582 { .dma_req = -1 }
583 };
584
585 /*
586 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
587 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
588 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
589 * should not be needed. The functional clock structure of the AM35xx
590 * UART4 is extremely unclear and opaque; it is unclear what the role
591 * of uart1/2_fck is for the UART4. Any clarification from either
592 * empirical testing or the AM3505/3517 hardware designers would be
593 * most welcome.
594 */
595 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
596 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
597 };
598
599 static struct omap_hwmod am35xx_uart4_hwmod = {
600 .name = "uart4",
601 .mpu_irqs = am35xx_uart4_mpu_irqs,
602 .sdma_reqs = am35xx_uart4_sdma_reqs,
603 .main_clk = "uart4_fck",
604 .prcm = {
605 .omap2 = {
606 .module_offs = CORE_MOD,
607 .prcm_reg_id = 1,
608 .module_bit = AM35XX_EN_UART4_SHIFT,
609 .idlest_reg_id = 1,
610 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
611 },
612 },
613 .opt_clks = am35xx_uart4_opt_clks,
614 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
615 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
616 .class = &omap2_uart_class,
617 };
618
619 static struct omap_hwmod_class i2c_class = {
620 .name = "i2c",
621 .sysc = &i2c_sysc,
622 .rev = OMAP_I2C_IP_VERSION_1,
623 .reset = &omap_i2c_reset,
624 };
625
626 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
627 { .name = "dispc", .dma_req = 5 },
628 { .name = "dsi1", .dma_req = 74 },
629 { .dma_req = -1 }
630 };
631
632 /* dss */
633 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
634 /*
635 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
636 * driver does not use these clocks.
637 */
638 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
639 { .role = "tv_clk", .clk = "dss_tv_fck" },
640 /* required only on OMAP3430 */
641 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
642 };
643
644 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
645 .name = "dss_core",
646 .class = &omap2_dss_hwmod_class,
647 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
648 .sdma_reqs = omap3xxx_dss_sdma_chs,
649 .prcm = {
650 .omap2 = {
651 .prcm_reg_id = 1,
652 .module_bit = OMAP3430_EN_DSS1_SHIFT,
653 .module_offs = OMAP3430_DSS_MOD,
654 .idlest_reg_id = 1,
655 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
656 },
657 },
658 .opt_clks = dss_opt_clks,
659 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
660 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
661 };
662
663 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
664 .name = "dss_core",
665 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
666 .class = &omap2_dss_hwmod_class,
667 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
668 .sdma_reqs = omap3xxx_dss_sdma_chs,
669 .prcm = {
670 .omap2 = {
671 .prcm_reg_id = 1,
672 .module_bit = OMAP3430_EN_DSS1_SHIFT,
673 .module_offs = OMAP3430_DSS_MOD,
674 .idlest_reg_id = 1,
675 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
676 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
677 },
678 },
679 .opt_clks = dss_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
681 };
682
683 /*
684 * 'dispc' class
685 * display controller
686 */
687
688 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
689 .rev_offs = 0x0000,
690 .sysc_offs = 0x0010,
691 .syss_offs = 0x0014,
692 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
693 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
694 SYSC_HAS_ENAWAKEUP),
695 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
696 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
697 .sysc_fields = &omap_hwmod_sysc_type1,
698 };
699
700 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
701 .name = "dispc",
702 .sysc = &omap3_dispc_sysc,
703 };
704
705 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
706 .name = "dss_dispc",
707 .class = &omap3_dispc_hwmod_class,
708 .mpu_irqs = omap2_dispc_irqs,
709 .main_clk = "dss1_alwon_fck",
710 .prcm = {
711 .omap2 = {
712 .prcm_reg_id = 1,
713 .module_bit = OMAP3430_EN_DSS1_SHIFT,
714 .module_offs = OMAP3430_DSS_MOD,
715 },
716 },
717 .flags = HWMOD_NO_IDLEST,
718 .dev_attr = &omap2_3_dss_dispc_dev_attr
719 };
720
721 /*
722 * 'dsi' class
723 * display serial interface controller
724 */
725
726 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
727 .rev_offs = 0x0000,
728 .sysc_offs = 0x0010,
729 .syss_offs = 0x0014,
730 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
731 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
732 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
733 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
734 .sysc_fields = &omap_hwmod_sysc_type1,
735 };
736
737 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
738 .name = "dsi",
739 .sysc = &omap3xxx_dsi_sysc,
740 };
741
742 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
743 { .irq = 25 + OMAP_INTC_START, },
744 { .irq = -1 },
745 };
746
747 /* dss_dsi1 */
748 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
749 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
750 };
751
752 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
753 .name = "dss_dsi1",
754 .class = &omap3xxx_dsi_hwmod_class,
755 .mpu_irqs = omap3xxx_dsi1_irqs,
756 .main_clk = "dss1_alwon_fck",
757 .prcm = {
758 .omap2 = {
759 .prcm_reg_id = 1,
760 .module_bit = OMAP3430_EN_DSS1_SHIFT,
761 .module_offs = OMAP3430_DSS_MOD,
762 },
763 },
764 .opt_clks = dss_dsi1_opt_clks,
765 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
766 .flags = HWMOD_NO_IDLEST,
767 };
768
769 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
770 { .role = "ick", .clk = "dss_ick" },
771 };
772
773 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
774 .name = "dss_rfbi",
775 .class = &omap2_rfbi_hwmod_class,
776 .main_clk = "dss1_alwon_fck",
777 .prcm = {
778 .omap2 = {
779 .prcm_reg_id = 1,
780 .module_bit = OMAP3430_EN_DSS1_SHIFT,
781 .module_offs = OMAP3430_DSS_MOD,
782 },
783 },
784 .opt_clks = dss_rfbi_opt_clks,
785 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
786 .flags = HWMOD_NO_IDLEST,
787 };
788
789 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
790 /* required only on OMAP3430 */
791 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
792 };
793
794 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
795 .name = "dss_venc",
796 .class = &omap2_venc_hwmod_class,
797 .main_clk = "dss_tv_fck",
798 .prcm = {
799 .omap2 = {
800 .prcm_reg_id = 1,
801 .module_bit = OMAP3430_EN_DSS1_SHIFT,
802 .module_offs = OMAP3430_DSS_MOD,
803 },
804 },
805 .opt_clks = dss_venc_opt_clks,
806 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
807 .flags = HWMOD_NO_IDLEST,
808 };
809
810 /* I2C1 */
811 static struct omap_i2c_dev_attr i2c1_dev_attr = {
812 .fifo_depth = 8, /* bytes */
813 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
814 };
815
816 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
817 .name = "i2c1",
818 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
819 .mpu_irqs = omap2_i2c1_mpu_irqs,
820 .sdma_reqs = omap2_i2c1_sdma_reqs,
821 .main_clk = "i2c1_fck",
822 .prcm = {
823 .omap2 = {
824 .module_offs = CORE_MOD,
825 .prcm_reg_id = 1,
826 .module_bit = OMAP3430_EN_I2C1_SHIFT,
827 .idlest_reg_id = 1,
828 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
829 },
830 },
831 .class = &i2c_class,
832 .dev_attr = &i2c1_dev_attr,
833 };
834
835 /* I2C2 */
836 static struct omap_i2c_dev_attr i2c2_dev_attr = {
837 .fifo_depth = 8, /* bytes */
838 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
839 };
840
841 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
842 .name = "i2c2",
843 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
844 .mpu_irqs = omap2_i2c2_mpu_irqs,
845 .sdma_reqs = omap2_i2c2_sdma_reqs,
846 .main_clk = "i2c2_fck",
847 .prcm = {
848 .omap2 = {
849 .module_offs = CORE_MOD,
850 .prcm_reg_id = 1,
851 .module_bit = OMAP3430_EN_I2C2_SHIFT,
852 .idlest_reg_id = 1,
853 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
854 },
855 },
856 .class = &i2c_class,
857 .dev_attr = &i2c2_dev_attr,
858 };
859
860 /* I2C3 */
861 static struct omap_i2c_dev_attr i2c3_dev_attr = {
862 .fifo_depth = 64, /* bytes */
863 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
864 };
865
866 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
867 { .irq = 61 + OMAP_INTC_START, },
868 { .irq = -1 },
869 };
870
871 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
872 { .name = "tx", .dma_req = 25 },
873 { .name = "rx", .dma_req = 26 },
874 { .dma_req = -1 }
875 };
876
877 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
878 .name = "i2c3",
879 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
880 .mpu_irqs = i2c3_mpu_irqs,
881 .sdma_reqs = i2c3_sdma_reqs,
882 .main_clk = "i2c3_fck",
883 .prcm = {
884 .omap2 = {
885 .module_offs = CORE_MOD,
886 .prcm_reg_id = 1,
887 .module_bit = OMAP3430_EN_I2C3_SHIFT,
888 .idlest_reg_id = 1,
889 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
890 },
891 },
892 .class = &i2c_class,
893 .dev_attr = &i2c3_dev_attr,
894 };
895
896 /*
897 * 'gpio' class
898 * general purpose io module
899 */
900
901 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
902 .rev_offs = 0x0000,
903 .sysc_offs = 0x0010,
904 .syss_offs = 0x0014,
905 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
906 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
907 SYSS_HAS_RESET_STATUS),
908 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
909 .sysc_fields = &omap_hwmod_sysc_type1,
910 };
911
912 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
913 .name = "gpio",
914 .sysc = &omap3xxx_gpio_sysc,
915 .rev = 1,
916 };
917
918 /* gpio_dev_attr */
919 static struct omap_gpio_dev_attr gpio_dev_attr = {
920 .bank_width = 32,
921 .dbck_flag = true,
922 };
923
924 /* gpio1 */
925 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
926 { .role = "dbclk", .clk = "gpio1_dbck", },
927 };
928
929 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
930 .name = "gpio1",
931 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
932 .mpu_irqs = omap2_gpio1_irqs,
933 .main_clk = "gpio1_ick",
934 .opt_clks = gpio1_opt_clks,
935 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
936 .prcm = {
937 .omap2 = {
938 .prcm_reg_id = 1,
939 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
940 .module_offs = WKUP_MOD,
941 .idlest_reg_id = 1,
942 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
943 },
944 },
945 .class = &omap3xxx_gpio_hwmod_class,
946 .dev_attr = &gpio_dev_attr,
947 };
948
949 /* gpio2 */
950 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
951 { .role = "dbclk", .clk = "gpio2_dbck", },
952 };
953
954 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
955 .name = "gpio2",
956 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
957 .mpu_irqs = omap2_gpio2_irqs,
958 .main_clk = "gpio2_ick",
959 .opt_clks = gpio2_opt_clks,
960 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
961 .prcm = {
962 .omap2 = {
963 .prcm_reg_id = 1,
964 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
965 .module_offs = OMAP3430_PER_MOD,
966 .idlest_reg_id = 1,
967 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
968 },
969 },
970 .class = &omap3xxx_gpio_hwmod_class,
971 .dev_attr = &gpio_dev_attr,
972 };
973
974 /* gpio3 */
975 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
976 { .role = "dbclk", .clk = "gpio3_dbck", },
977 };
978
979 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
980 .name = "gpio3",
981 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
982 .mpu_irqs = omap2_gpio3_irqs,
983 .main_clk = "gpio3_ick",
984 .opt_clks = gpio3_opt_clks,
985 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
986 .prcm = {
987 .omap2 = {
988 .prcm_reg_id = 1,
989 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
990 .module_offs = OMAP3430_PER_MOD,
991 .idlest_reg_id = 1,
992 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
993 },
994 },
995 .class = &omap3xxx_gpio_hwmod_class,
996 .dev_attr = &gpio_dev_attr,
997 };
998
999 /* gpio4 */
1000 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1001 { .role = "dbclk", .clk = "gpio4_dbck", },
1002 };
1003
1004 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1005 .name = "gpio4",
1006 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1007 .mpu_irqs = omap2_gpio4_irqs,
1008 .main_clk = "gpio4_ick",
1009 .opt_clks = gpio4_opt_clks,
1010 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1011 .prcm = {
1012 .omap2 = {
1013 .prcm_reg_id = 1,
1014 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1015 .module_offs = OMAP3430_PER_MOD,
1016 .idlest_reg_id = 1,
1017 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1018 },
1019 },
1020 .class = &omap3xxx_gpio_hwmod_class,
1021 .dev_attr = &gpio_dev_attr,
1022 };
1023
1024 /* gpio5 */
1025 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1026 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1027 { .irq = -1 },
1028 };
1029
1030 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1031 { .role = "dbclk", .clk = "gpio5_dbck", },
1032 };
1033
1034 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1035 .name = "gpio5",
1036 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1037 .mpu_irqs = omap3xxx_gpio5_irqs,
1038 .main_clk = "gpio5_ick",
1039 .opt_clks = gpio5_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1041 .prcm = {
1042 .omap2 = {
1043 .prcm_reg_id = 1,
1044 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1045 .module_offs = OMAP3430_PER_MOD,
1046 .idlest_reg_id = 1,
1047 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1048 },
1049 },
1050 .class = &omap3xxx_gpio_hwmod_class,
1051 .dev_attr = &gpio_dev_attr,
1052 };
1053
1054 /* gpio6 */
1055 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1056 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1057 { .irq = -1 },
1058 };
1059
1060 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1061 { .role = "dbclk", .clk = "gpio6_dbck", },
1062 };
1063
1064 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1065 .name = "gpio6",
1066 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1067 .mpu_irqs = omap3xxx_gpio6_irqs,
1068 .main_clk = "gpio6_ick",
1069 .opt_clks = gpio6_opt_clks,
1070 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1071 .prcm = {
1072 .omap2 = {
1073 .prcm_reg_id = 1,
1074 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1075 .module_offs = OMAP3430_PER_MOD,
1076 .idlest_reg_id = 1,
1077 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1078 },
1079 },
1080 .class = &omap3xxx_gpio_hwmod_class,
1081 .dev_attr = &gpio_dev_attr,
1082 };
1083
1084 /* dma attributes */
1085 static struct omap_dma_dev_attr dma_dev_attr = {
1086 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1087 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1088 .lch_count = 32,
1089 };
1090
1091 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1092 .rev_offs = 0x0000,
1093 .sysc_offs = 0x002c,
1094 .syss_offs = 0x0028,
1095 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1096 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1097 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1098 SYSS_HAS_RESET_STATUS),
1099 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1100 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1101 .sysc_fields = &omap_hwmod_sysc_type1,
1102 };
1103
1104 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1105 .name = "dma",
1106 .sysc = &omap3xxx_dma_sysc,
1107 };
1108
1109 /* dma_system */
1110 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1111 .name = "dma",
1112 .class = &omap3xxx_dma_hwmod_class,
1113 .mpu_irqs = omap2_dma_system_irqs,
1114 .main_clk = "core_l3_ick",
1115 .prcm = {
1116 .omap2 = {
1117 .module_offs = CORE_MOD,
1118 .prcm_reg_id = 1,
1119 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1120 .idlest_reg_id = 1,
1121 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1122 },
1123 },
1124 .dev_attr = &dma_dev_attr,
1125 .flags = HWMOD_NO_IDLEST,
1126 };
1127
1128 /*
1129 * 'mcbsp' class
1130 * multi channel buffered serial port controller
1131 */
1132
1133 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1134 .sysc_offs = 0x008c,
1135 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1136 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1137 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1138 .sysc_fields = &omap_hwmod_sysc_type1,
1139 .clockact = 0x2,
1140 };
1141
1142 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1143 .name = "mcbsp",
1144 .sysc = &omap3xxx_mcbsp_sysc,
1145 .rev = MCBSP_CONFIG_TYPE3,
1146 };
1147
1148 /* McBSP functional clock mapping */
1149 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1150 { .role = "pad_fck", .clk = "mcbsp_clks" },
1151 { .role = "prcm_fck", .clk = "core_96m_fck" },
1152 };
1153
1154 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1155 { .role = "pad_fck", .clk = "mcbsp_clks" },
1156 { .role = "prcm_fck", .clk = "per_96m_fck" },
1157 };
1158
1159 /* mcbsp1 */
1160 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1161 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1162 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1163 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1164 { .irq = -1 },
1165 };
1166
1167 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1168 .name = "mcbsp1",
1169 .class = &omap3xxx_mcbsp_hwmod_class,
1170 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1171 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1172 .main_clk = "mcbsp1_fck",
1173 .prcm = {
1174 .omap2 = {
1175 .prcm_reg_id = 1,
1176 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1177 .module_offs = CORE_MOD,
1178 .idlest_reg_id = 1,
1179 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1180 },
1181 },
1182 .opt_clks = mcbsp15_opt_clks,
1183 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1184 };
1185
1186 /* mcbsp2 */
1187 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1188 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1189 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1190 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1191 { .irq = -1 },
1192 };
1193
1194 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1195 .sidetone = "mcbsp2_sidetone",
1196 };
1197
1198 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1199 .name = "mcbsp2",
1200 .class = &omap3xxx_mcbsp_hwmod_class,
1201 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1202 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1203 .main_clk = "mcbsp2_fck",
1204 .prcm = {
1205 .omap2 = {
1206 .prcm_reg_id = 1,
1207 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1208 .module_offs = OMAP3430_PER_MOD,
1209 .idlest_reg_id = 1,
1210 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1211 },
1212 },
1213 .opt_clks = mcbsp234_opt_clks,
1214 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1215 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1216 };
1217
1218 /* mcbsp3 */
1219 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1220 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1221 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1222 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1223 { .irq = -1 },
1224 };
1225
1226 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1227 .sidetone = "mcbsp3_sidetone",
1228 };
1229
1230 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1231 .name = "mcbsp3",
1232 .class = &omap3xxx_mcbsp_hwmod_class,
1233 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1234 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1235 .main_clk = "mcbsp3_fck",
1236 .prcm = {
1237 .omap2 = {
1238 .prcm_reg_id = 1,
1239 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1240 .module_offs = OMAP3430_PER_MOD,
1241 .idlest_reg_id = 1,
1242 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1243 },
1244 },
1245 .opt_clks = mcbsp234_opt_clks,
1246 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1247 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1248 };
1249
1250 /* mcbsp4 */
1251 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1252 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1253 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1254 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1255 { .irq = -1 },
1256 };
1257
1258 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1259 { .name = "rx", .dma_req = 20 },
1260 { .name = "tx", .dma_req = 19 },
1261 { .dma_req = -1 }
1262 };
1263
1264 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1265 .name = "mcbsp4",
1266 .class = &omap3xxx_mcbsp_hwmod_class,
1267 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1268 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1269 .main_clk = "mcbsp4_fck",
1270 .prcm = {
1271 .omap2 = {
1272 .prcm_reg_id = 1,
1273 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1274 .module_offs = OMAP3430_PER_MOD,
1275 .idlest_reg_id = 1,
1276 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1277 },
1278 },
1279 .opt_clks = mcbsp234_opt_clks,
1280 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1281 };
1282
1283 /* mcbsp5 */
1284 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1285 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1286 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1287 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1288 { .irq = -1 },
1289 };
1290
1291 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1292 { .name = "rx", .dma_req = 22 },
1293 { .name = "tx", .dma_req = 21 },
1294 { .dma_req = -1 }
1295 };
1296
1297 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1298 .name = "mcbsp5",
1299 .class = &omap3xxx_mcbsp_hwmod_class,
1300 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1301 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1302 .main_clk = "mcbsp5_fck",
1303 .prcm = {
1304 .omap2 = {
1305 .prcm_reg_id = 1,
1306 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1307 .module_offs = CORE_MOD,
1308 .idlest_reg_id = 1,
1309 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1310 },
1311 },
1312 .opt_clks = mcbsp15_opt_clks,
1313 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1314 };
1315
1316 /* 'mcbsp sidetone' class */
1317 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1318 .sysc_offs = 0x0010,
1319 .sysc_flags = SYSC_HAS_AUTOIDLE,
1320 .sysc_fields = &omap_hwmod_sysc_type1,
1321 };
1322
1323 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1324 .name = "mcbsp_sidetone",
1325 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1326 };
1327
1328 /* mcbsp2_sidetone */
1329 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1330 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1331 { .irq = -1 },
1332 };
1333
1334 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1335 .name = "mcbsp2_sidetone",
1336 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1337 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1338 .main_clk = "mcbsp2_fck",
1339 .prcm = {
1340 .omap2 = {
1341 .prcm_reg_id = 1,
1342 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1343 .module_offs = OMAP3430_PER_MOD,
1344 .idlest_reg_id = 1,
1345 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1346 },
1347 },
1348 };
1349
1350 /* mcbsp3_sidetone */
1351 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1352 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1353 { .irq = -1 },
1354 };
1355
1356 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1357 .name = "mcbsp3_sidetone",
1358 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1359 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1360 .main_clk = "mcbsp3_fck",
1361 .prcm = {
1362 .omap2 = {
1363 .prcm_reg_id = 1,
1364 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1365 .module_offs = OMAP3430_PER_MOD,
1366 .idlest_reg_id = 1,
1367 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1368 },
1369 },
1370 };
1371
1372 /* SR common */
1373 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1374 .clkact_shift = 20,
1375 };
1376
1377 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1378 .sysc_offs = 0x24,
1379 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1380 .clockact = CLOCKACT_TEST_ICLK,
1381 .sysc_fields = &omap34xx_sr_sysc_fields,
1382 };
1383
1384 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1385 .name = "smartreflex",
1386 .sysc = &omap34xx_sr_sysc,
1387 .rev = 1,
1388 };
1389
1390 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1391 .sidle_shift = 24,
1392 .enwkup_shift = 26,
1393 };
1394
1395 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1396 .sysc_offs = 0x38,
1397 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1398 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1399 SYSC_NO_CACHE),
1400 .sysc_fields = &omap36xx_sr_sysc_fields,
1401 };
1402
1403 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1404 .name = "smartreflex",
1405 .sysc = &omap36xx_sr_sysc,
1406 .rev = 2,
1407 };
1408
1409 /* SR1 */
1410 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1411 .sensor_voltdm_name = "mpu_iva",
1412 };
1413
1414 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1415 { .irq = 18 + OMAP_INTC_START, },
1416 { .irq = -1 },
1417 };
1418
1419 static struct omap_hwmod omap34xx_sr1_hwmod = {
1420 .name = "smartreflex_mpu_iva",
1421 .class = &omap34xx_smartreflex_hwmod_class,
1422 .main_clk = "sr1_fck",
1423 .prcm = {
1424 .omap2 = {
1425 .prcm_reg_id = 1,
1426 .module_bit = OMAP3430_EN_SR1_SHIFT,
1427 .module_offs = WKUP_MOD,
1428 .idlest_reg_id = 1,
1429 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1430 },
1431 },
1432 .dev_attr = &sr1_dev_attr,
1433 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1434 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1435 };
1436
1437 static struct omap_hwmod omap36xx_sr1_hwmod = {
1438 .name = "smartreflex_mpu_iva",
1439 .class = &omap36xx_smartreflex_hwmod_class,
1440 .main_clk = "sr1_fck",
1441 .prcm = {
1442 .omap2 = {
1443 .prcm_reg_id = 1,
1444 .module_bit = OMAP3430_EN_SR1_SHIFT,
1445 .module_offs = WKUP_MOD,
1446 .idlest_reg_id = 1,
1447 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1448 },
1449 },
1450 .dev_attr = &sr1_dev_attr,
1451 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1452 };
1453
1454 /* SR2 */
1455 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1456 .sensor_voltdm_name = "core",
1457 };
1458
1459 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1460 { .irq = 19 + OMAP_INTC_START, },
1461 { .irq = -1 },
1462 };
1463
1464 static struct omap_hwmod omap34xx_sr2_hwmod = {
1465 .name = "smartreflex_core",
1466 .class = &omap34xx_smartreflex_hwmod_class,
1467 .main_clk = "sr2_fck",
1468 .prcm = {
1469 .omap2 = {
1470 .prcm_reg_id = 1,
1471 .module_bit = OMAP3430_EN_SR2_SHIFT,
1472 .module_offs = WKUP_MOD,
1473 .idlest_reg_id = 1,
1474 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1475 },
1476 },
1477 .dev_attr = &sr2_dev_attr,
1478 .mpu_irqs = omap3_smartreflex_core_irqs,
1479 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1480 };
1481
1482 static struct omap_hwmod omap36xx_sr2_hwmod = {
1483 .name = "smartreflex_core",
1484 .class = &omap36xx_smartreflex_hwmod_class,
1485 .main_clk = "sr2_fck",
1486 .prcm = {
1487 .omap2 = {
1488 .prcm_reg_id = 1,
1489 .module_bit = OMAP3430_EN_SR2_SHIFT,
1490 .module_offs = WKUP_MOD,
1491 .idlest_reg_id = 1,
1492 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1493 },
1494 },
1495 .dev_attr = &sr2_dev_attr,
1496 .mpu_irqs = omap3_smartreflex_core_irqs,
1497 };
1498
1499 /*
1500 * 'mailbox' class
1501 * mailbox module allowing communication between the on-chip processors
1502 * using a queued mailbox-interrupt mechanism.
1503 */
1504
1505 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1506 .rev_offs = 0x000,
1507 .sysc_offs = 0x010,
1508 .syss_offs = 0x014,
1509 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1510 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1511 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1512 .sysc_fields = &omap_hwmod_sysc_type1,
1513 };
1514
1515 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1516 .name = "mailbox",
1517 .sysc = &omap3xxx_mailbox_sysc,
1518 };
1519
1520 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1521 .name = "mailbox",
1522 .class = &omap3xxx_mailbox_hwmod_class,
1523 .main_clk = "mailboxes_ick",
1524 .prcm = {
1525 .omap2 = {
1526 .prcm_reg_id = 1,
1527 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1528 .module_offs = CORE_MOD,
1529 .idlest_reg_id = 1,
1530 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1531 },
1532 },
1533 };
1534
1535 /*
1536 * 'mcspi' class
1537 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1538 * bus
1539 */
1540
1541 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1542 .rev_offs = 0x0000,
1543 .sysc_offs = 0x0010,
1544 .syss_offs = 0x0014,
1545 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1546 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1547 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1548 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1549 .sysc_fields = &omap_hwmod_sysc_type1,
1550 };
1551
1552 static struct omap_hwmod_class omap34xx_mcspi_class = {
1553 .name = "mcspi",
1554 .sysc = &omap34xx_mcspi_sysc,
1555 .rev = OMAP3_MCSPI_REV,
1556 };
1557
1558 /* mcspi1 */
1559 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1560 .num_chipselect = 4,
1561 };
1562
1563 static struct omap_hwmod omap34xx_mcspi1 = {
1564 .name = "mcspi1",
1565 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1566 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1567 .main_clk = "mcspi1_fck",
1568 .prcm = {
1569 .omap2 = {
1570 .module_offs = CORE_MOD,
1571 .prcm_reg_id = 1,
1572 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1573 .idlest_reg_id = 1,
1574 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1575 },
1576 },
1577 .class = &omap34xx_mcspi_class,
1578 .dev_attr = &omap_mcspi1_dev_attr,
1579 };
1580
1581 /* mcspi2 */
1582 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1583 .num_chipselect = 2,
1584 };
1585
1586 static struct omap_hwmod omap34xx_mcspi2 = {
1587 .name = "mcspi2",
1588 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1589 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1590 .main_clk = "mcspi2_fck",
1591 .prcm = {
1592 .omap2 = {
1593 .module_offs = CORE_MOD,
1594 .prcm_reg_id = 1,
1595 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1596 .idlest_reg_id = 1,
1597 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1598 },
1599 },
1600 .class = &omap34xx_mcspi_class,
1601 .dev_attr = &omap_mcspi2_dev_attr,
1602 };
1603
1604 /* mcspi3 */
1605 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1606 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1607 { .irq = -1 },
1608 };
1609
1610 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1611 { .name = "tx0", .dma_req = 15 },
1612 { .name = "rx0", .dma_req = 16 },
1613 { .name = "tx1", .dma_req = 23 },
1614 { .name = "rx1", .dma_req = 24 },
1615 { .dma_req = -1 }
1616 };
1617
1618 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1619 .num_chipselect = 2,
1620 };
1621
1622 static struct omap_hwmod omap34xx_mcspi3 = {
1623 .name = "mcspi3",
1624 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1625 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1626 .main_clk = "mcspi3_fck",
1627 .prcm = {
1628 .omap2 = {
1629 .module_offs = CORE_MOD,
1630 .prcm_reg_id = 1,
1631 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1632 .idlest_reg_id = 1,
1633 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1634 },
1635 },
1636 .class = &omap34xx_mcspi_class,
1637 .dev_attr = &omap_mcspi3_dev_attr,
1638 };
1639
1640 /* mcspi4 */
1641 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1642 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1643 { .irq = -1 },
1644 };
1645
1646 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1647 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1648 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1649 { .dma_req = -1 }
1650 };
1651
1652 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1653 .num_chipselect = 1,
1654 };
1655
1656 static struct omap_hwmod omap34xx_mcspi4 = {
1657 .name = "mcspi4",
1658 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1659 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1660 .main_clk = "mcspi4_fck",
1661 .prcm = {
1662 .omap2 = {
1663 .module_offs = CORE_MOD,
1664 .prcm_reg_id = 1,
1665 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1666 .idlest_reg_id = 1,
1667 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1668 },
1669 },
1670 .class = &omap34xx_mcspi_class,
1671 .dev_attr = &omap_mcspi4_dev_attr,
1672 };
1673
1674 /* usbhsotg */
1675 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1676 .rev_offs = 0x0400,
1677 .sysc_offs = 0x0404,
1678 .syss_offs = 0x0408,
1679 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1680 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1681 SYSC_HAS_AUTOIDLE),
1682 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1683 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1684 .sysc_fields = &omap_hwmod_sysc_type1,
1685 };
1686
1687 static struct omap_hwmod_class usbotg_class = {
1688 .name = "usbotg",
1689 .sysc = &omap3xxx_usbhsotg_sysc,
1690 };
1691
1692 /* usb_otg_hs */
1693 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1694
1695 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1696 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1697 { .irq = -1 },
1698 };
1699
1700 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1701 .name = "usb_otg_hs",
1702 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1703 .main_clk = "hsotgusb_ick",
1704 .prcm = {
1705 .omap2 = {
1706 .prcm_reg_id = 1,
1707 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1708 .module_offs = CORE_MOD,
1709 .idlest_reg_id = 1,
1710 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1711 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1712 },
1713 },
1714 .class = &usbotg_class,
1715
1716 /*
1717 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1718 * broken when autoidle is enabled
1719 * workaround is to disable the autoidle bit at module level.
1720 *
1721 * Enabling the device in any other MIDLEMODE setting but force-idle
1722 * causes core_pwrdm not enter idle states at least on OMAP3630.
1723 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1724 * signal when MIDLEMODE is set to force-idle.
1725 */
1726 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1727 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1728 };
1729
1730 /* usb_otg_hs */
1731 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1732 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1733 { .irq = -1 },
1734 };
1735
1736 static struct omap_hwmod_class am35xx_usbotg_class = {
1737 .name = "am35xx_usbotg",
1738 };
1739
1740 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1741 .name = "am35x_otg_hs",
1742 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1743 .main_clk = "hsotgusb_fck",
1744 .class = &am35xx_usbotg_class,
1745 .flags = HWMOD_NO_IDLEST,
1746 };
1747
1748 /* MMC/SD/SDIO common */
1749 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1750 .rev_offs = 0x1fc,
1751 .sysc_offs = 0x10,
1752 .syss_offs = 0x14,
1753 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1754 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1755 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1756 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1757 .sysc_fields = &omap_hwmod_sysc_type1,
1758 };
1759
1760 static struct omap_hwmod_class omap34xx_mmc_class = {
1761 .name = "mmc",
1762 .sysc = &omap34xx_mmc_sysc,
1763 };
1764
1765 /* MMC/SD/SDIO1 */
1766
1767 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1768 { .irq = 83 + OMAP_INTC_START, },
1769 { .irq = -1 },
1770 };
1771
1772 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1773 { .name = "tx", .dma_req = 61, },
1774 { .name = "rx", .dma_req = 62, },
1775 { .dma_req = -1 }
1776 };
1777
1778 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1779 { .role = "dbck", .clk = "omap_32k_fck", },
1780 };
1781
1782 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1783 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1784 };
1785
1786 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1787 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1788 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1789 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1790 };
1791
1792 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1793 .name = "mmc1",
1794 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1795 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1796 .opt_clks = omap34xx_mmc1_opt_clks,
1797 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1798 .main_clk = "mmchs1_fck",
1799 .prcm = {
1800 .omap2 = {
1801 .module_offs = CORE_MOD,
1802 .prcm_reg_id = 1,
1803 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1804 .idlest_reg_id = 1,
1805 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1806 },
1807 },
1808 .dev_attr = &mmc1_pre_es3_dev_attr,
1809 .class = &omap34xx_mmc_class,
1810 };
1811
1812 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1813 .name = "mmc1",
1814 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1815 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1816 .opt_clks = omap34xx_mmc1_opt_clks,
1817 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1818 .main_clk = "mmchs1_fck",
1819 .prcm = {
1820 .omap2 = {
1821 .module_offs = CORE_MOD,
1822 .prcm_reg_id = 1,
1823 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1824 .idlest_reg_id = 1,
1825 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1826 },
1827 },
1828 .dev_attr = &mmc1_dev_attr,
1829 .class = &omap34xx_mmc_class,
1830 };
1831
1832 /* MMC/SD/SDIO2 */
1833
1834 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1835 { .irq = 86 + OMAP_INTC_START, },
1836 { .irq = -1 },
1837 };
1838
1839 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1840 { .name = "tx", .dma_req = 47, },
1841 { .name = "rx", .dma_req = 48, },
1842 { .dma_req = -1 }
1843 };
1844
1845 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1846 { .role = "dbck", .clk = "omap_32k_fck", },
1847 };
1848
1849 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1850 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1851 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1852 };
1853
1854 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1855 .name = "mmc2",
1856 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1857 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1858 .opt_clks = omap34xx_mmc2_opt_clks,
1859 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1860 .main_clk = "mmchs2_fck",
1861 .prcm = {
1862 .omap2 = {
1863 .module_offs = CORE_MOD,
1864 .prcm_reg_id = 1,
1865 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1866 .idlest_reg_id = 1,
1867 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1868 },
1869 },
1870 .dev_attr = &mmc2_pre_es3_dev_attr,
1871 .class = &omap34xx_mmc_class,
1872 };
1873
1874 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1875 .name = "mmc2",
1876 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1877 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1878 .opt_clks = omap34xx_mmc2_opt_clks,
1879 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1880 .main_clk = "mmchs2_fck",
1881 .prcm = {
1882 .omap2 = {
1883 .module_offs = CORE_MOD,
1884 .prcm_reg_id = 1,
1885 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1886 .idlest_reg_id = 1,
1887 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1888 },
1889 },
1890 .class = &omap34xx_mmc_class,
1891 };
1892
1893 /* MMC/SD/SDIO3 */
1894
1895 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1896 { .irq = 94 + OMAP_INTC_START, },
1897 { .irq = -1 },
1898 };
1899
1900 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1901 { .name = "tx", .dma_req = 77, },
1902 { .name = "rx", .dma_req = 78, },
1903 { .dma_req = -1 }
1904 };
1905
1906 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1907 { .role = "dbck", .clk = "omap_32k_fck", },
1908 };
1909
1910 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1911 .name = "mmc3",
1912 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1913 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1914 .opt_clks = omap34xx_mmc3_opt_clks,
1915 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1916 .main_clk = "mmchs3_fck",
1917 .prcm = {
1918 .omap2 = {
1919 .prcm_reg_id = 1,
1920 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1921 .idlest_reg_id = 1,
1922 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1923 },
1924 },
1925 .class = &omap34xx_mmc_class,
1926 };
1927
1928 /*
1929 * 'usb_host_hs' class
1930 * high-speed multi-port usb host controller
1931 */
1932
1933 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1934 .rev_offs = 0x0000,
1935 .sysc_offs = 0x0010,
1936 .syss_offs = 0x0014,
1937 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1938 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1939 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1940 SYSS_HAS_RESET_STATUS),
1941 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1942 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1943 .sysc_fields = &omap_hwmod_sysc_type1,
1944 };
1945
1946 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1947 .name = "usb_host_hs",
1948 .sysc = &omap3xxx_usb_host_hs_sysc,
1949 };
1950
1951 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1952 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1953 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1954 { .irq = -1 },
1955 };
1956
1957 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1958 .name = "usb_host_hs",
1959 .class = &omap3xxx_usb_host_hs_hwmod_class,
1960 .clkdm_name = "usbhost_clkdm",
1961 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1962 .main_clk = "usbhost_48m_fck",
1963 .prcm = {
1964 .omap2 = {
1965 .module_offs = OMAP3430ES2_USBHOST_MOD,
1966 .prcm_reg_id = 1,
1967 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1968 .idlest_reg_id = 1,
1969 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1970 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1971 },
1972 },
1973
1974 /*
1975 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1976 * id: i660
1977 *
1978 * Description:
1979 * In the following configuration :
1980 * - USBHOST module is set to smart-idle mode
1981 * - PRCM asserts idle_req to the USBHOST module ( This typically
1982 * happens when the system is going to a low power mode : all ports
1983 * have been suspended, the master part of the USBHOST module has
1984 * entered the standby state, and SW has cut the functional clocks)
1985 * - an USBHOST interrupt occurs before the module is able to answer
1986 * idle_ack, typically a remote wakeup IRQ.
1987 * Then the USB HOST module will enter a deadlock situation where it
1988 * is no more accessible nor functional.
1989 *
1990 * Workaround:
1991 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1992 */
1993
1994 /*
1995 * Errata: USB host EHCI may stall when entering smart-standby mode
1996 * Id: i571
1997 *
1998 * Description:
1999 * When the USBHOST module is set to smart-standby mode, and when it is
2000 * ready to enter the standby state (i.e. all ports are suspended and
2001 * all attached devices are in suspend mode), then it can wrongly assert
2002 * the Mstandby signal too early while there are still some residual OCP
2003 * transactions ongoing. If this condition occurs, the internal state
2004 * machine may go to an undefined state and the USB link may be stuck
2005 * upon the next resume.
2006 *
2007 * Workaround:
2008 * Don't use smart standby; use only force standby,
2009 * hence HWMOD_SWSUP_MSTANDBY
2010 */
2011
2012 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2013 };
2014
2015 /*
2016 * 'usb_tll_hs' class
2017 * usb_tll_hs module is the adapter on the usb_host_hs ports
2018 */
2019 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2020 .rev_offs = 0x0000,
2021 .sysc_offs = 0x0010,
2022 .syss_offs = 0x0014,
2023 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2024 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2025 SYSC_HAS_AUTOIDLE),
2026 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2027 .sysc_fields = &omap_hwmod_sysc_type1,
2028 };
2029
2030 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2031 .name = "usb_tll_hs",
2032 .sysc = &omap3xxx_usb_tll_hs_sysc,
2033 };
2034
2035 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2036 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2037 { .irq = -1 },
2038 };
2039
2040 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2041 .name = "usb_tll_hs",
2042 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2043 .clkdm_name = "core_l4_clkdm",
2044 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2045 .main_clk = "usbtll_fck",
2046 .prcm = {
2047 .omap2 = {
2048 .module_offs = CORE_MOD,
2049 .prcm_reg_id = 3,
2050 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2051 .idlest_reg_id = 3,
2052 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2053 },
2054 },
2055 };
2056
2057 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2058 .name = "hdq1w",
2059 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2060 .main_clk = "hdq_fck",
2061 .prcm = {
2062 .omap2 = {
2063 .module_offs = CORE_MOD,
2064 .prcm_reg_id = 1,
2065 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2066 .idlest_reg_id = 1,
2067 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2068 },
2069 },
2070 .class = &omap2_hdq1w_class,
2071 };
2072
2073 /* SAD2D */
2074 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2075 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2076 { .name = "rst_modem_sw", .rst_shift = 1 },
2077 };
2078
2079 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2080 .name = "sad2d",
2081 };
2082
2083 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2084 .name = "sad2d",
2085 .rst_lines = omap3xxx_sad2d_resets,
2086 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2087 .main_clk = "sad2d_ick",
2088 .prcm = {
2089 .omap2 = {
2090 .module_offs = CORE_MOD,
2091 .prcm_reg_id = 1,
2092 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2093 .idlest_reg_id = 1,
2094 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2095 },
2096 },
2097 .class = &omap3xxx_sad2d_class,
2098 };
2099
2100 /*
2101 * '32K sync counter' class
2102 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2103 */
2104 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2105 .rev_offs = 0x0000,
2106 .sysc_offs = 0x0004,
2107 .sysc_flags = SYSC_HAS_SIDLEMODE,
2108 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2109 .sysc_fields = &omap_hwmod_sysc_type1,
2110 };
2111
2112 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2113 .name = "counter",
2114 .sysc = &omap3xxx_counter_sysc,
2115 };
2116
2117 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2118 .name = "counter_32k",
2119 .class = &omap3xxx_counter_hwmod_class,
2120 .clkdm_name = "wkup_clkdm",
2121 .flags = HWMOD_SWSUP_SIDLE,
2122 .main_clk = "wkup_32k_fck",
2123 .prcm = {
2124 .omap2 = {
2125 .module_offs = WKUP_MOD,
2126 .prcm_reg_id = 1,
2127 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2128 .idlest_reg_id = 1,
2129 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2130 },
2131 },
2132 };
2133
2134 /*
2135 * 'gpmc' class
2136 * general purpose memory controller
2137 */
2138
2139 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2140 .rev_offs = 0x0000,
2141 .sysc_offs = 0x0010,
2142 .syss_offs = 0x0014,
2143 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2144 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2145 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2146 .sysc_fields = &omap_hwmod_sysc_type1,
2147 };
2148
2149 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2150 .name = "gpmc",
2151 .sysc = &omap3xxx_gpmc_sysc,
2152 };
2153
2154 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2155 { .irq = 20 + OMAP_INTC_START, },
2156 { .irq = -1 }
2157 };
2158
2159 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2160 .name = "gpmc",
2161 .class = &omap3xxx_gpmc_hwmod_class,
2162 .clkdm_name = "core_l3_clkdm",
2163 .mpu_irqs = omap3xxx_gpmc_irqs,
2164 .main_clk = "gpmc_fck",
2165 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
2166 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
2167 };
2168
2169 /*
2170 * interfaces
2171 */
2172
2173 /* L3 -> L4_CORE interface */
2174 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2175 .master = &omap3xxx_l3_main_hwmod,
2176 .slave = &omap3xxx_l4_core_hwmod,
2177 .user = OCP_USER_MPU | OCP_USER_SDMA,
2178 };
2179
2180 /* L3 -> L4_PER interface */
2181 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2182 .master = &omap3xxx_l3_main_hwmod,
2183 .slave = &omap3xxx_l4_per_hwmod,
2184 .user = OCP_USER_MPU | OCP_USER_SDMA,
2185 };
2186
2187 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2188 {
2189 .pa_start = 0x68000000,
2190 .pa_end = 0x6800ffff,
2191 .flags = ADDR_TYPE_RT,
2192 },
2193 { }
2194 };
2195
2196 /* MPU -> L3 interface */
2197 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2198 .master = &omap3xxx_mpu_hwmod,
2199 .slave = &omap3xxx_l3_main_hwmod,
2200 .addr = omap3xxx_l3_main_addrs,
2201 .user = OCP_USER_MPU,
2202 };
2203
2204 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2205 {
2206 .pa_start = 0x54000000,
2207 .pa_end = 0x547fffff,
2208 .flags = ADDR_TYPE_RT,
2209 },
2210 { }
2211 };
2212
2213 /* l3 -> debugss */
2214 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2215 .master = &omap3xxx_l3_main_hwmod,
2216 .slave = &omap3xxx_debugss_hwmod,
2217 .addr = omap3xxx_l4_emu_addrs,
2218 .user = OCP_USER_MPU,
2219 };
2220
2221 /* DSS -> l3 */
2222 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2223 .master = &omap3430es1_dss_core_hwmod,
2224 .slave = &omap3xxx_l3_main_hwmod,
2225 .user = OCP_USER_MPU | OCP_USER_SDMA,
2226 };
2227
2228 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2229 .master = &omap3xxx_dss_core_hwmod,
2230 .slave = &omap3xxx_l3_main_hwmod,
2231 .fw = {
2232 .omap2 = {
2233 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2234 .flags = OMAP_FIREWALL_L3,
2235 }
2236 },
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2238 };
2239
2240 /* l3_core -> usbhsotg interface */
2241 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2242 .master = &omap3xxx_usbhsotg_hwmod,
2243 .slave = &omap3xxx_l3_main_hwmod,
2244 .clk = "core_l3_ick",
2245 .user = OCP_USER_MPU,
2246 };
2247
2248 /* l3_core -> am35xx_usbhsotg interface */
2249 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2250 .master = &am35xx_usbhsotg_hwmod,
2251 .slave = &omap3xxx_l3_main_hwmod,
2252 .clk = "hsotgusb_ick",
2253 .user = OCP_USER_MPU,
2254 };
2255
2256 /* l3_core -> sad2d interface */
2257 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2258 .master = &omap3xxx_sad2d_hwmod,
2259 .slave = &omap3xxx_l3_main_hwmod,
2260 .clk = "core_l3_ick",
2261 .user = OCP_USER_MPU,
2262 };
2263
2264 /* L4_CORE -> L4_WKUP interface */
2265 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2266 .master = &omap3xxx_l4_core_hwmod,
2267 .slave = &omap3xxx_l4_wkup_hwmod,
2268 .user = OCP_USER_MPU | OCP_USER_SDMA,
2269 };
2270
2271 /* L4 CORE -> MMC1 interface */
2272 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2275 .clk = "mmchs1_ick",
2276 .addr = omap2430_mmc1_addr_space,
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2278 .flags = OMAP_FIREWALL_L4
2279 };
2280
2281 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2282 .master = &omap3xxx_l4_core_hwmod,
2283 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2284 .clk = "mmchs1_ick",
2285 .addr = omap2430_mmc1_addr_space,
2286 .user = OCP_USER_MPU | OCP_USER_SDMA,
2287 .flags = OMAP_FIREWALL_L4
2288 };
2289
2290 /* L4 CORE -> MMC2 interface */
2291 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2292 .master = &omap3xxx_l4_core_hwmod,
2293 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2294 .clk = "mmchs2_ick",
2295 .addr = omap2430_mmc2_addr_space,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 .flags = OMAP_FIREWALL_L4
2298 };
2299
2300 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2301 .master = &omap3xxx_l4_core_hwmod,
2302 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2303 .clk = "mmchs2_ick",
2304 .addr = omap2430_mmc2_addr_space,
2305 .user = OCP_USER_MPU | OCP_USER_SDMA,
2306 .flags = OMAP_FIREWALL_L4
2307 };
2308
2309 /* L4 CORE -> MMC3 interface */
2310 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2311 {
2312 .pa_start = 0x480ad000,
2313 .pa_end = 0x480ad1ff,
2314 .flags = ADDR_TYPE_RT,
2315 },
2316 { }
2317 };
2318
2319 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2320 .master = &omap3xxx_l4_core_hwmod,
2321 .slave = &omap3xxx_mmc3_hwmod,
2322 .clk = "mmchs3_ick",
2323 .addr = omap3xxx_mmc3_addr_space,
2324 .user = OCP_USER_MPU | OCP_USER_SDMA,
2325 .flags = OMAP_FIREWALL_L4
2326 };
2327
2328 /* L4 CORE -> UART1 interface */
2329 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2330 {
2331 .pa_start = OMAP3_UART1_BASE,
2332 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2333 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2334 },
2335 { }
2336 };
2337
2338 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2339 .master = &omap3xxx_l4_core_hwmod,
2340 .slave = &omap3xxx_uart1_hwmod,
2341 .clk = "uart1_ick",
2342 .addr = omap3xxx_uart1_addr_space,
2343 .user = OCP_USER_MPU | OCP_USER_SDMA,
2344 };
2345
2346 /* L4 CORE -> UART2 interface */
2347 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2348 {
2349 .pa_start = OMAP3_UART2_BASE,
2350 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2351 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2352 },
2353 { }
2354 };
2355
2356 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2357 .master = &omap3xxx_l4_core_hwmod,
2358 .slave = &omap3xxx_uart2_hwmod,
2359 .clk = "uart2_ick",
2360 .addr = omap3xxx_uart2_addr_space,
2361 .user = OCP_USER_MPU | OCP_USER_SDMA,
2362 };
2363
2364 /* L4 PER -> UART3 interface */
2365 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2366 {
2367 .pa_start = OMAP3_UART3_BASE,
2368 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2369 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2370 },
2371 { }
2372 };
2373
2374 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2375 .master = &omap3xxx_l4_per_hwmod,
2376 .slave = &omap3xxx_uart3_hwmod,
2377 .clk = "uart3_ick",
2378 .addr = omap3xxx_uart3_addr_space,
2379 .user = OCP_USER_MPU | OCP_USER_SDMA,
2380 };
2381
2382 /* L4 PER -> UART4 interface */
2383 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2384 {
2385 .pa_start = OMAP3_UART4_BASE,
2386 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2387 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2388 },
2389 { }
2390 };
2391
2392 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2393 .master = &omap3xxx_l4_per_hwmod,
2394 .slave = &omap36xx_uart4_hwmod,
2395 .clk = "uart4_ick",
2396 .addr = omap36xx_uart4_addr_space,
2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2398 };
2399
2400 /* AM35xx: L4 CORE -> UART4 interface */
2401 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2402 {
2403 .pa_start = OMAP3_UART4_AM35XX_BASE,
2404 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2405 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2406 },
2407 { }
2408 };
2409
2410 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2411 .master = &omap3xxx_l4_core_hwmod,
2412 .slave = &am35xx_uart4_hwmod,
2413 .clk = "uart4_ick",
2414 .addr = am35xx_uart4_addr_space,
2415 .user = OCP_USER_MPU | OCP_USER_SDMA,
2416 };
2417
2418 /* L4 CORE -> I2C1 interface */
2419 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2420 .master = &omap3xxx_l4_core_hwmod,
2421 .slave = &omap3xxx_i2c1_hwmod,
2422 .clk = "i2c1_ick",
2423 .addr = omap2_i2c1_addr_space,
2424 .fw = {
2425 .omap2 = {
2426 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2427 .l4_prot_group = 7,
2428 .flags = OMAP_FIREWALL_L4,
2429 }
2430 },
2431 .user = OCP_USER_MPU | OCP_USER_SDMA,
2432 };
2433
2434 /* L4 CORE -> I2C2 interface */
2435 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2436 .master = &omap3xxx_l4_core_hwmod,
2437 .slave = &omap3xxx_i2c2_hwmod,
2438 .clk = "i2c2_ick",
2439 .addr = omap2_i2c2_addr_space,
2440 .fw = {
2441 .omap2 = {
2442 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2443 .l4_prot_group = 7,
2444 .flags = OMAP_FIREWALL_L4,
2445 }
2446 },
2447 .user = OCP_USER_MPU | OCP_USER_SDMA,
2448 };
2449
2450 /* L4 CORE -> I2C3 interface */
2451 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2452 {
2453 .pa_start = 0x48060000,
2454 .pa_end = 0x48060000 + SZ_128 - 1,
2455 .flags = ADDR_TYPE_RT,
2456 },
2457 { }
2458 };
2459
2460 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2461 .master = &omap3xxx_l4_core_hwmod,
2462 .slave = &omap3xxx_i2c3_hwmod,
2463 .clk = "i2c3_ick",
2464 .addr = omap3xxx_i2c3_addr_space,
2465 .fw = {
2466 .omap2 = {
2467 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2468 .l4_prot_group = 7,
2469 .flags = OMAP_FIREWALL_L4,
2470 }
2471 },
2472 .user = OCP_USER_MPU | OCP_USER_SDMA,
2473 };
2474
2475 /* L4 CORE -> SR1 interface */
2476 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2477 {
2478 .pa_start = OMAP34XX_SR1_BASE,
2479 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2480 .flags = ADDR_TYPE_RT,
2481 },
2482 { }
2483 };
2484
2485 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2486 .master = &omap3xxx_l4_core_hwmod,
2487 .slave = &omap34xx_sr1_hwmod,
2488 .clk = "sr_l4_ick",
2489 .addr = omap3_sr1_addr_space,
2490 .user = OCP_USER_MPU,
2491 };
2492
2493 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2494 .master = &omap3xxx_l4_core_hwmod,
2495 .slave = &omap36xx_sr1_hwmod,
2496 .clk = "sr_l4_ick",
2497 .addr = omap3_sr1_addr_space,
2498 .user = OCP_USER_MPU,
2499 };
2500
2501 /* L4 CORE -> SR1 interface */
2502 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2503 {
2504 .pa_start = OMAP34XX_SR2_BASE,
2505 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2506 .flags = ADDR_TYPE_RT,
2507 },
2508 { }
2509 };
2510
2511 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2512 .master = &omap3xxx_l4_core_hwmod,
2513 .slave = &omap34xx_sr2_hwmod,
2514 .clk = "sr_l4_ick",
2515 .addr = omap3_sr2_addr_space,
2516 .user = OCP_USER_MPU,
2517 };
2518
2519 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2520 .master = &omap3xxx_l4_core_hwmod,
2521 .slave = &omap36xx_sr2_hwmod,
2522 .clk = "sr_l4_ick",
2523 .addr = omap3_sr2_addr_space,
2524 .user = OCP_USER_MPU,
2525 };
2526
2527 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2528 {
2529 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2530 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2531 .flags = ADDR_TYPE_RT
2532 },
2533 { }
2534 };
2535
2536 /* l4_core -> usbhsotg */
2537 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2538 .master = &omap3xxx_l4_core_hwmod,
2539 .slave = &omap3xxx_usbhsotg_hwmod,
2540 .clk = "l4_ick",
2541 .addr = omap3xxx_usbhsotg_addrs,
2542 .user = OCP_USER_MPU,
2543 };
2544
2545 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2546 {
2547 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2548 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2549 .flags = ADDR_TYPE_RT
2550 },
2551 { }
2552 };
2553
2554 /* l4_core -> usbhsotg */
2555 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2556 .master = &omap3xxx_l4_core_hwmod,
2557 .slave = &am35xx_usbhsotg_hwmod,
2558 .clk = "hsotgusb_ick",
2559 .addr = am35xx_usbhsotg_addrs,
2560 .user = OCP_USER_MPU,
2561 };
2562
2563 /* L4_WKUP -> L4_SEC interface */
2564 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2565 .master = &omap3xxx_l4_wkup_hwmod,
2566 .slave = &omap3xxx_l4_sec_hwmod,
2567 .user = OCP_USER_MPU | OCP_USER_SDMA,
2568 };
2569
2570 /* IVA2 <- L3 interface */
2571 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2572 .master = &omap3xxx_l3_main_hwmod,
2573 .slave = &omap3xxx_iva_hwmod,
2574 .clk = "core_l3_ick",
2575 .user = OCP_USER_MPU | OCP_USER_SDMA,
2576 };
2577
2578 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2579 {
2580 .pa_start = 0x48318000,
2581 .pa_end = 0x48318000 + SZ_1K - 1,
2582 .flags = ADDR_TYPE_RT
2583 },
2584 { }
2585 };
2586
2587 /* l4_wkup -> timer1 */
2588 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2589 .master = &omap3xxx_l4_wkup_hwmod,
2590 .slave = &omap3xxx_timer1_hwmod,
2591 .clk = "gpt1_ick",
2592 .addr = omap3xxx_timer1_addrs,
2593 .user = OCP_USER_MPU | OCP_USER_SDMA,
2594 };
2595
2596 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2597 {
2598 .pa_start = 0x49032000,
2599 .pa_end = 0x49032000 + SZ_1K - 1,
2600 .flags = ADDR_TYPE_RT
2601 },
2602 { }
2603 };
2604
2605 /* l4_per -> timer2 */
2606 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2607 .master = &omap3xxx_l4_per_hwmod,
2608 .slave = &omap3xxx_timer2_hwmod,
2609 .clk = "gpt2_ick",
2610 .addr = omap3xxx_timer2_addrs,
2611 .user = OCP_USER_MPU | OCP_USER_SDMA,
2612 };
2613
2614 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2615 {
2616 .pa_start = 0x49034000,
2617 .pa_end = 0x49034000 + SZ_1K - 1,
2618 .flags = ADDR_TYPE_RT
2619 },
2620 { }
2621 };
2622
2623 /* l4_per -> timer3 */
2624 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2625 .master = &omap3xxx_l4_per_hwmod,
2626 .slave = &omap3xxx_timer3_hwmod,
2627 .clk = "gpt3_ick",
2628 .addr = omap3xxx_timer3_addrs,
2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
2630 };
2631
2632 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2633 {
2634 .pa_start = 0x49036000,
2635 .pa_end = 0x49036000 + SZ_1K - 1,
2636 .flags = ADDR_TYPE_RT
2637 },
2638 { }
2639 };
2640
2641 /* l4_per -> timer4 */
2642 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2643 .master = &omap3xxx_l4_per_hwmod,
2644 .slave = &omap3xxx_timer4_hwmod,
2645 .clk = "gpt4_ick",
2646 .addr = omap3xxx_timer4_addrs,
2647 .user = OCP_USER_MPU | OCP_USER_SDMA,
2648 };
2649
2650 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2651 {
2652 .pa_start = 0x49038000,
2653 .pa_end = 0x49038000 + SZ_1K - 1,
2654 .flags = ADDR_TYPE_RT
2655 },
2656 { }
2657 };
2658
2659 /* l4_per -> timer5 */
2660 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2661 .master = &omap3xxx_l4_per_hwmod,
2662 .slave = &omap3xxx_timer5_hwmod,
2663 .clk = "gpt5_ick",
2664 .addr = omap3xxx_timer5_addrs,
2665 .user = OCP_USER_MPU | OCP_USER_SDMA,
2666 };
2667
2668 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2669 {
2670 .pa_start = 0x4903A000,
2671 .pa_end = 0x4903A000 + SZ_1K - 1,
2672 .flags = ADDR_TYPE_RT
2673 },
2674 { }
2675 };
2676
2677 /* l4_per -> timer6 */
2678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2679 .master = &omap3xxx_l4_per_hwmod,
2680 .slave = &omap3xxx_timer6_hwmod,
2681 .clk = "gpt6_ick",
2682 .addr = omap3xxx_timer6_addrs,
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2684 };
2685
2686 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2687 {
2688 .pa_start = 0x4903C000,
2689 .pa_end = 0x4903C000 + SZ_1K - 1,
2690 .flags = ADDR_TYPE_RT
2691 },
2692 { }
2693 };
2694
2695 /* l4_per -> timer7 */
2696 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2697 .master = &omap3xxx_l4_per_hwmod,
2698 .slave = &omap3xxx_timer7_hwmod,
2699 .clk = "gpt7_ick",
2700 .addr = omap3xxx_timer7_addrs,
2701 .user = OCP_USER_MPU | OCP_USER_SDMA,
2702 };
2703
2704 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2705 {
2706 .pa_start = 0x4903E000,
2707 .pa_end = 0x4903E000 + SZ_1K - 1,
2708 .flags = ADDR_TYPE_RT
2709 },
2710 { }
2711 };
2712
2713 /* l4_per -> timer8 */
2714 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2715 .master = &omap3xxx_l4_per_hwmod,
2716 .slave = &omap3xxx_timer8_hwmod,
2717 .clk = "gpt8_ick",
2718 .addr = omap3xxx_timer8_addrs,
2719 .user = OCP_USER_MPU | OCP_USER_SDMA,
2720 };
2721
2722 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2723 {
2724 .pa_start = 0x49040000,
2725 .pa_end = 0x49040000 + SZ_1K - 1,
2726 .flags = ADDR_TYPE_RT
2727 },
2728 { }
2729 };
2730
2731 /* l4_per -> timer9 */
2732 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2733 .master = &omap3xxx_l4_per_hwmod,
2734 .slave = &omap3xxx_timer9_hwmod,
2735 .clk = "gpt9_ick",
2736 .addr = omap3xxx_timer9_addrs,
2737 .user = OCP_USER_MPU | OCP_USER_SDMA,
2738 };
2739
2740 /* l4_core -> timer10 */
2741 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2742 .master = &omap3xxx_l4_core_hwmod,
2743 .slave = &omap3xxx_timer10_hwmod,
2744 .clk = "gpt10_ick",
2745 .addr = omap2_timer10_addrs,
2746 .user = OCP_USER_MPU | OCP_USER_SDMA,
2747 };
2748
2749 /* l4_core -> timer11 */
2750 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2751 .master = &omap3xxx_l4_core_hwmod,
2752 .slave = &omap3xxx_timer11_hwmod,
2753 .clk = "gpt11_ick",
2754 .addr = omap2_timer11_addrs,
2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
2756 };
2757
2758 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2759 {
2760 .pa_start = 0x48304000,
2761 .pa_end = 0x48304000 + SZ_1K - 1,
2762 .flags = ADDR_TYPE_RT
2763 },
2764 { }
2765 };
2766
2767 /* l4_core -> timer12 */
2768 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2769 .master = &omap3xxx_l4_sec_hwmod,
2770 .slave = &omap3xxx_timer12_hwmod,
2771 .clk = "gpt12_ick",
2772 .addr = omap3xxx_timer12_addrs,
2773 .user = OCP_USER_MPU | OCP_USER_SDMA,
2774 };
2775
2776 /* l4_wkup -> wd_timer2 */
2777 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2778 {
2779 .pa_start = 0x48314000,
2780 .pa_end = 0x4831407f,
2781 .flags = ADDR_TYPE_RT
2782 },
2783 { }
2784 };
2785
2786 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2787 .master = &omap3xxx_l4_wkup_hwmod,
2788 .slave = &omap3xxx_wd_timer2_hwmod,
2789 .clk = "wdt2_ick",
2790 .addr = omap3xxx_wd_timer2_addrs,
2791 .user = OCP_USER_MPU | OCP_USER_SDMA,
2792 };
2793
2794 /* l4_core -> dss */
2795 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2796 .master = &omap3xxx_l4_core_hwmod,
2797 .slave = &omap3430es1_dss_core_hwmod,
2798 .clk = "dss_ick",
2799 .addr = omap2_dss_addrs,
2800 .fw = {
2801 .omap2 = {
2802 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2803 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2804 .flags = OMAP_FIREWALL_L4,
2805 }
2806 },
2807 .user = OCP_USER_MPU | OCP_USER_SDMA,
2808 };
2809
2810 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2811 .master = &omap3xxx_l4_core_hwmod,
2812 .slave = &omap3xxx_dss_core_hwmod,
2813 .clk = "dss_ick",
2814 .addr = omap2_dss_addrs,
2815 .fw = {
2816 .omap2 = {
2817 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2818 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2819 .flags = OMAP_FIREWALL_L4,
2820 }
2821 },
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2823 };
2824
2825 /* l4_core -> dss_dispc */
2826 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2827 .master = &omap3xxx_l4_core_hwmod,
2828 .slave = &omap3xxx_dss_dispc_hwmod,
2829 .clk = "dss_ick",
2830 .addr = omap2_dss_dispc_addrs,
2831 .fw = {
2832 .omap2 = {
2833 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2834 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2835 .flags = OMAP_FIREWALL_L4,
2836 }
2837 },
2838 .user = OCP_USER_MPU | OCP_USER_SDMA,
2839 };
2840
2841 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2842 {
2843 .pa_start = 0x4804FC00,
2844 .pa_end = 0x4804FFFF,
2845 .flags = ADDR_TYPE_RT
2846 },
2847 { }
2848 };
2849
2850 /* l4_core -> dss_dsi1 */
2851 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2852 .master = &omap3xxx_l4_core_hwmod,
2853 .slave = &omap3xxx_dss_dsi1_hwmod,
2854 .clk = "dss_ick",
2855 .addr = omap3xxx_dss_dsi1_addrs,
2856 .fw = {
2857 .omap2 = {
2858 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2859 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2860 .flags = OMAP_FIREWALL_L4,
2861 }
2862 },
2863 .user = OCP_USER_MPU | OCP_USER_SDMA,
2864 };
2865
2866 /* l4_core -> dss_rfbi */
2867 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2868 .master = &omap3xxx_l4_core_hwmod,
2869 .slave = &omap3xxx_dss_rfbi_hwmod,
2870 .clk = "dss_ick",
2871 .addr = omap2_dss_rfbi_addrs,
2872 .fw = {
2873 .omap2 = {
2874 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2875 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2876 .flags = OMAP_FIREWALL_L4,
2877 }
2878 },
2879 .user = OCP_USER_MPU | OCP_USER_SDMA,
2880 };
2881
2882 /* l4_core -> dss_venc */
2883 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2884 .master = &omap3xxx_l4_core_hwmod,
2885 .slave = &omap3xxx_dss_venc_hwmod,
2886 .clk = "dss_ick",
2887 .addr = omap2_dss_venc_addrs,
2888 .fw = {
2889 .omap2 = {
2890 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2891 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2892 .flags = OMAP_FIREWALL_L4,
2893 }
2894 },
2895 .flags = OCPIF_SWSUP_IDLE,
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897 };
2898
2899 /* l4_wkup -> gpio1 */
2900 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2901 {
2902 .pa_start = 0x48310000,
2903 .pa_end = 0x483101ff,
2904 .flags = ADDR_TYPE_RT
2905 },
2906 { }
2907 };
2908
2909 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2910 .master = &omap3xxx_l4_wkup_hwmod,
2911 .slave = &omap3xxx_gpio1_hwmod,
2912 .addr = omap3xxx_gpio1_addrs,
2913 .user = OCP_USER_MPU | OCP_USER_SDMA,
2914 };
2915
2916 /* l4_per -> gpio2 */
2917 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2918 {
2919 .pa_start = 0x49050000,
2920 .pa_end = 0x490501ff,
2921 .flags = ADDR_TYPE_RT
2922 },
2923 { }
2924 };
2925
2926 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2927 .master = &omap3xxx_l4_per_hwmod,
2928 .slave = &omap3xxx_gpio2_hwmod,
2929 .addr = omap3xxx_gpio2_addrs,
2930 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931 };
2932
2933 /* l4_per -> gpio3 */
2934 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2935 {
2936 .pa_start = 0x49052000,
2937 .pa_end = 0x490521ff,
2938 .flags = ADDR_TYPE_RT
2939 },
2940 { }
2941 };
2942
2943 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2944 .master = &omap3xxx_l4_per_hwmod,
2945 .slave = &omap3xxx_gpio3_hwmod,
2946 .addr = omap3xxx_gpio3_addrs,
2947 .user = OCP_USER_MPU | OCP_USER_SDMA,
2948 };
2949
2950 /*
2951 * 'mmu' class
2952 * The memory management unit performs virtual to physical address translation
2953 * for its requestors.
2954 */
2955
2956 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2957 .rev_offs = 0x000,
2958 .sysc_offs = 0x010,
2959 .syss_offs = 0x014,
2960 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2961 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2962 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2963 .sysc_fields = &omap_hwmod_sysc_type1,
2964 };
2965
2966 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2967 .name = "mmu",
2968 .sysc = &mmu_sysc,
2969 };
2970
2971 /* mmu isp */
2972
2973 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2974 .nr_tlb_entries = 8,
2975 };
2976
2977 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2978 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2979 { .irq = 24 + OMAP_INTC_START, },
2980 { .irq = -1 }
2981 };
2982
2983 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2984 {
2985 .pa_start = 0x480bd400,
2986 .pa_end = 0x480bd47f,
2987 .flags = ADDR_TYPE_RT,
2988 },
2989 { }
2990 };
2991
2992 /* l4_core -> mmu isp */
2993 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2994 .master = &omap3xxx_l4_core_hwmod,
2995 .slave = &omap3xxx_mmu_isp_hwmod,
2996 .addr = omap3xxx_mmu_isp_addrs,
2997 .user = OCP_USER_MPU | OCP_USER_SDMA,
2998 };
2999
3000 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3001 .name = "mmu_isp",
3002 .class = &omap3xxx_mmu_hwmod_class,
3003 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3004 .main_clk = "cam_ick",
3005 .dev_attr = &mmu_isp_dev_attr,
3006 .flags = HWMOD_NO_IDLEST,
3007 };
3008
3009 /* mmu iva */
3010
3011 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3012 .nr_tlb_entries = 32,
3013 };
3014
3015 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3016 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3017 { .irq = 28 + OMAP_INTC_START, },
3018 { .irq = -1 }
3019 };
3020
3021 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3022 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3023 };
3024
3025 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3026 {
3027 .pa_start = 0x5d000000,
3028 .pa_end = 0x5d00007f,
3029 .flags = ADDR_TYPE_RT,
3030 },
3031 { }
3032 };
3033
3034 /* l3_main -> iva mmu */
3035 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3036 .master = &omap3xxx_l3_main_hwmod,
3037 .slave = &omap3xxx_mmu_iva_hwmod,
3038 .addr = omap3xxx_mmu_iva_addrs,
3039 .user = OCP_USER_MPU | OCP_USER_SDMA,
3040 };
3041
3042 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3043 .name = "mmu_iva",
3044 .class = &omap3xxx_mmu_hwmod_class,
3045 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3046 .clkdm_name = "iva2_clkdm",
3047 .rst_lines = omap3xxx_mmu_iva_resets,
3048 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3049 .main_clk = "iva2_ck",
3050 .prcm = {
3051 .omap2 = {
3052 .module_offs = OMAP3430_IVA2_MOD,
3053 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
3054 .idlest_reg_id = 1,
3055 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
3056 },
3057 },
3058 .dev_attr = &mmu_iva_dev_attr,
3059 .flags = HWMOD_NO_IDLEST,
3060 };
3061
3062 /* l4_per -> gpio4 */
3063 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3064 {
3065 .pa_start = 0x49054000,
3066 .pa_end = 0x490541ff,
3067 .flags = ADDR_TYPE_RT
3068 },
3069 { }
3070 };
3071
3072 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3073 .master = &omap3xxx_l4_per_hwmod,
3074 .slave = &omap3xxx_gpio4_hwmod,
3075 .addr = omap3xxx_gpio4_addrs,
3076 .user = OCP_USER_MPU | OCP_USER_SDMA,
3077 };
3078
3079 /* l4_per -> gpio5 */
3080 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3081 {
3082 .pa_start = 0x49056000,
3083 .pa_end = 0x490561ff,
3084 .flags = ADDR_TYPE_RT
3085 },
3086 { }
3087 };
3088
3089 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3090 .master = &omap3xxx_l4_per_hwmod,
3091 .slave = &omap3xxx_gpio5_hwmod,
3092 .addr = omap3xxx_gpio5_addrs,
3093 .user = OCP_USER_MPU | OCP_USER_SDMA,
3094 };
3095
3096 /* l4_per -> gpio6 */
3097 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3098 {
3099 .pa_start = 0x49058000,
3100 .pa_end = 0x490581ff,
3101 .flags = ADDR_TYPE_RT
3102 },
3103 { }
3104 };
3105
3106 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3107 .master = &omap3xxx_l4_per_hwmod,
3108 .slave = &omap3xxx_gpio6_hwmod,
3109 .addr = omap3xxx_gpio6_addrs,
3110 .user = OCP_USER_MPU | OCP_USER_SDMA,
3111 };
3112
3113 /* dma_system -> L3 */
3114 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3115 .master = &omap3xxx_dma_system_hwmod,
3116 .slave = &omap3xxx_l3_main_hwmod,
3117 .clk = "core_l3_ick",
3118 .user = OCP_USER_MPU | OCP_USER_SDMA,
3119 };
3120
3121 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3122 {
3123 .pa_start = 0x48056000,
3124 .pa_end = 0x48056fff,
3125 .flags = ADDR_TYPE_RT
3126 },
3127 { }
3128 };
3129
3130 /* l4_cfg -> dma_system */
3131 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3132 .master = &omap3xxx_l4_core_hwmod,
3133 .slave = &omap3xxx_dma_system_hwmod,
3134 .clk = "core_l4_ick",
3135 .addr = omap3xxx_dma_system_addrs,
3136 .user = OCP_USER_MPU | OCP_USER_SDMA,
3137 };
3138
3139 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3140 {
3141 .name = "mpu",
3142 .pa_start = 0x48074000,
3143 .pa_end = 0x480740ff,
3144 .flags = ADDR_TYPE_RT
3145 },
3146 { }
3147 };
3148
3149 /* l4_core -> mcbsp1 */
3150 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3151 .master = &omap3xxx_l4_core_hwmod,
3152 .slave = &omap3xxx_mcbsp1_hwmod,
3153 .clk = "mcbsp1_ick",
3154 .addr = omap3xxx_mcbsp1_addrs,
3155 .user = OCP_USER_MPU | OCP_USER_SDMA,
3156 };
3157
3158 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3159 {
3160 .name = "mpu",
3161 .pa_start = 0x49022000,
3162 .pa_end = 0x490220ff,
3163 .flags = ADDR_TYPE_RT
3164 },
3165 { }
3166 };
3167
3168 /* l4_per -> mcbsp2 */
3169 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3170 .master = &omap3xxx_l4_per_hwmod,
3171 .slave = &omap3xxx_mcbsp2_hwmod,
3172 .clk = "mcbsp2_ick",
3173 .addr = omap3xxx_mcbsp2_addrs,
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175 };
3176
3177 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3178 {
3179 .name = "mpu",
3180 .pa_start = 0x49024000,
3181 .pa_end = 0x490240ff,
3182 .flags = ADDR_TYPE_RT
3183 },
3184 { }
3185 };
3186
3187 /* l4_per -> mcbsp3 */
3188 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3189 .master = &omap3xxx_l4_per_hwmod,
3190 .slave = &omap3xxx_mcbsp3_hwmod,
3191 .clk = "mcbsp3_ick",
3192 .addr = omap3xxx_mcbsp3_addrs,
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3194 };
3195
3196 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3197 {
3198 .name = "mpu",
3199 .pa_start = 0x49026000,
3200 .pa_end = 0x490260ff,
3201 .flags = ADDR_TYPE_RT
3202 },
3203 { }
3204 };
3205
3206 /* l4_per -> mcbsp4 */
3207 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3208 .master = &omap3xxx_l4_per_hwmod,
3209 .slave = &omap3xxx_mcbsp4_hwmod,
3210 .clk = "mcbsp4_ick",
3211 .addr = omap3xxx_mcbsp4_addrs,
3212 .user = OCP_USER_MPU | OCP_USER_SDMA,
3213 };
3214
3215 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3216 {
3217 .name = "mpu",
3218 .pa_start = 0x48096000,
3219 .pa_end = 0x480960ff,
3220 .flags = ADDR_TYPE_RT
3221 },
3222 { }
3223 };
3224
3225 /* l4_core -> mcbsp5 */
3226 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3227 .master = &omap3xxx_l4_core_hwmod,
3228 .slave = &omap3xxx_mcbsp5_hwmod,
3229 .clk = "mcbsp5_ick",
3230 .addr = omap3xxx_mcbsp5_addrs,
3231 .user = OCP_USER_MPU | OCP_USER_SDMA,
3232 };
3233
3234 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3235 {
3236 .name = "sidetone",
3237 .pa_start = 0x49028000,
3238 .pa_end = 0x490280ff,
3239 .flags = ADDR_TYPE_RT
3240 },
3241 { }
3242 };
3243
3244 /* l4_per -> mcbsp2_sidetone */
3245 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3246 .master = &omap3xxx_l4_per_hwmod,
3247 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3248 .clk = "mcbsp2_ick",
3249 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3250 .user = OCP_USER_MPU,
3251 };
3252
3253 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3254 {
3255 .name = "sidetone",
3256 .pa_start = 0x4902A000,
3257 .pa_end = 0x4902A0ff,
3258 .flags = ADDR_TYPE_RT
3259 },
3260 { }
3261 };
3262
3263 /* l4_per -> mcbsp3_sidetone */
3264 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3265 .master = &omap3xxx_l4_per_hwmod,
3266 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3267 .clk = "mcbsp3_ick",
3268 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3269 .user = OCP_USER_MPU,
3270 };
3271
3272 /* l4_core -> mailbox */
3273 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3274 .master = &omap3xxx_l4_core_hwmod,
3275 .slave = &omap3xxx_mailbox_hwmod,
3276 .user = OCP_USER_MPU | OCP_USER_SDMA,
3277 };
3278
3279 /* l4 core -> mcspi1 interface */
3280 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3281 .master = &omap3xxx_l4_core_hwmod,
3282 .slave = &omap34xx_mcspi1,
3283 .clk = "mcspi1_ick",
3284 .addr = omap2_mcspi1_addr_space,
3285 .user = OCP_USER_MPU | OCP_USER_SDMA,
3286 };
3287
3288 /* l4 core -> mcspi2 interface */
3289 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3290 .master = &omap3xxx_l4_core_hwmod,
3291 .slave = &omap34xx_mcspi2,
3292 .clk = "mcspi2_ick",
3293 .addr = omap2_mcspi2_addr_space,
3294 .user = OCP_USER_MPU | OCP_USER_SDMA,
3295 };
3296
3297 /* l4 core -> mcspi3 interface */
3298 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3299 .master = &omap3xxx_l4_core_hwmod,
3300 .slave = &omap34xx_mcspi3,
3301 .clk = "mcspi3_ick",
3302 .addr = omap2430_mcspi3_addr_space,
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3305
3306 /* l4 core -> mcspi4 interface */
3307 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3308 {
3309 .pa_start = 0x480ba000,
3310 .pa_end = 0x480ba0ff,
3311 .flags = ADDR_TYPE_RT,
3312 },
3313 { }
3314 };
3315
3316 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3317 .master = &omap3xxx_l4_core_hwmod,
3318 .slave = &omap34xx_mcspi4,
3319 .clk = "mcspi4_ick",
3320 .addr = omap34xx_mcspi4_addr_space,
3321 .user = OCP_USER_MPU | OCP_USER_SDMA,
3322 };
3323
3324 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3325 .master = &omap3xxx_usb_host_hs_hwmod,
3326 .slave = &omap3xxx_l3_main_hwmod,
3327 .clk = "core_l3_ick",
3328 .user = OCP_USER_MPU,
3329 };
3330
3331 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3332 {
3333 .name = "uhh",
3334 .pa_start = 0x48064000,
3335 .pa_end = 0x480643ff,
3336 .flags = ADDR_TYPE_RT
3337 },
3338 {
3339 .name = "ohci",
3340 .pa_start = 0x48064400,
3341 .pa_end = 0x480647ff,
3342 },
3343 {
3344 .name = "ehci",
3345 .pa_start = 0x48064800,
3346 .pa_end = 0x48064cff,
3347 },
3348 {}
3349 };
3350
3351 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3352 .master = &omap3xxx_l4_core_hwmod,
3353 .slave = &omap3xxx_usb_host_hs_hwmod,
3354 .clk = "usbhost_ick",
3355 .addr = omap3xxx_usb_host_hs_addrs,
3356 .user = OCP_USER_MPU | OCP_USER_SDMA,
3357 };
3358
3359 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3360 {
3361 .name = "tll",
3362 .pa_start = 0x48062000,
3363 .pa_end = 0x48062fff,
3364 .flags = ADDR_TYPE_RT
3365 },
3366 {}
3367 };
3368
3369 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3370 .master = &omap3xxx_l4_core_hwmod,
3371 .slave = &omap3xxx_usb_tll_hs_hwmod,
3372 .clk = "usbtll_ick",
3373 .addr = omap3xxx_usb_tll_hs_addrs,
3374 .user = OCP_USER_MPU | OCP_USER_SDMA,
3375 };
3376
3377 /* l4_core -> hdq1w interface */
3378 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3379 .master = &omap3xxx_l4_core_hwmod,
3380 .slave = &omap3xxx_hdq1w_hwmod,
3381 .clk = "hdq_ick",
3382 .addr = omap2_hdq1w_addr_space,
3383 .user = OCP_USER_MPU | OCP_USER_SDMA,
3384 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3385 };
3386
3387 /* l4_wkup -> 32ksync_counter */
3388 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3389 {
3390 .pa_start = 0x48320000,
3391 .pa_end = 0x4832001f,
3392 .flags = ADDR_TYPE_RT
3393 },
3394 { }
3395 };
3396
3397 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3398 {
3399 .pa_start = 0x6e000000,
3400 .pa_end = 0x6e000fff,
3401 .flags = ADDR_TYPE_RT
3402 },
3403 { }
3404 };
3405
3406 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3407 .master = &omap3xxx_l4_wkup_hwmod,
3408 .slave = &omap3xxx_counter_32k_hwmod,
3409 .clk = "omap_32ksync_ick",
3410 .addr = omap3xxx_counter_32k_addrs,
3411 .user = OCP_USER_MPU | OCP_USER_SDMA,
3412 };
3413
3414 /* am35xx has Davinci MDIO & EMAC */
3415 static struct omap_hwmod_class am35xx_mdio_class = {
3416 .name = "davinci_mdio",
3417 };
3418
3419 static struct omap_hwmod am35xx_mdio_hwmod = {
3420 .name = "davinci_mdio",
3421 .class = &am35xx_mdio_class,
3422 .flags = HWMOD_NO_IDLEST,
3423 };
3424
3425 /*
3426 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3427 * but this will probably require some additional hwmod core support,
3428 * so is left as a future to-do item.
3429 */
3430 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3431 .master = &am35xx_mdio_hwmod,
3432 .slave = &omap3xxx_l3_main_hwmod,
3433 .clk = "emac_fck",
3434 .user = OCP_USER_MPU,
3435 };
3436
3437 /* l4_core -> davinci mdio */
3438 /*
3439 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3440 * but this will probably require some additional hwmod core support,
3441 * so is left as a future to-do item.
3442 */
3443 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3444 .master = &omap3xxx_l4_core_hwmod,
3445 .slave = &am35xx_mdio_hwmod,
3446 .clk = "emac_fck",
3447 .user = OCP_USER_MPU,
3448 };
3449
3450 static struct omap_hwmod_class am35xx_emac_class = {
3451 .name = "davinci_emac",
3452 };
3453
3454 static struct omap_hwmod am35xx_emac_hwmod = {
3455 .name = "davinci_emac",
3456 .class = &am35xx_emac_class,
3457 /*
3458 * According to Mark Greer, the MPU will not return from WFI
3459 * when the EMAC signals an interrupt.
3460 * http://www.spinics.net/lists/arm-kernel/msg174734.html
3461 */
3462 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3463 };
3464
3465 /* l3_core -> davinci emac interface */
3466 /*
3467 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3468 * but this will probably require some additional hwmod core support,
3469 * so is left as a future to-do item.
3470 */
3471 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3472 .master = &am35xx_emac_hwmod,
3473 .slave = &omap3xxx_l3_main_hwmod,
3474 .clk = "emac_ick",
3475 .user = OCP_USER_MPU,
3476 };
3477
3478 /* l4_core -> davinci emac */
3479 /*
3480 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3481 * but this will probably require some additional hwmod core support,
3482 * so is left as a future to-do item.
3483 */
3484 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3485 .master = &omap3xxx_l4_core_hwmod,
3486 .slave = &am35xx_emac_hwmod,
3487 .clk = "emac_ick",
3488 .user = OCP_USER_MPU,
3489 };
3490
3491 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3492 .master = &omap3xxx_l3_main_hwmod,
3493 .slave = &omap3xxx_gpmc_hwmod,
3494 .clk = "core_l3_ick",
3495 .addr = omap3xxx_gpmc_addrs,
3496 .user = OCP_USER_MPU | OCP_USER_SDMA,
3497 };
3498
3499 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3500 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3501 .sidle_shift = 4,
3502 .srst_shift = 1,
3503 .autoidle_shift = 0,
3504 };
3505
3506 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3507 .rev_offs = 0x5c,
3508 .sysc_offs = 0x60,
3509 .syss_offs = 0x64,
3510 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3511 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3512 .sysc_fields = &omap3_sham_sysc_fields,
3513 };
3514
3515 static struct omap_hwmod_class omap3xxx_sham_class = {
3516 .name = "sham",
3517 .sysc = &omap3_sham_sysc,
3518 };
3519
3520 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3521 { .irq = 49 + OMAP_INTC_START, },
3522 { .irq = -1 }
3523 };
3524
3525 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3526 { .name = "rx", .dma_req = 69, },
3527 { .dma_req = -1 }
3528 };
3529
3530 static struct omap_hwmod omap3xxx_sham_hwmod = {
3531 .name = "sham",
3532 .mpu_irqs = omap3_sham_mpu_irqs,
3533 .sdma_reqs = omap3_sham_sdma_reqs,
3534 .main_clk = "sha12_ick",
3535 .prcm = {
3536 .omap2 = {
3537 .module_offs = CORE_MOD,
3538 .prcm_reg_id = 1,
3539 .module_bit = OMAP3430_EN_SHA12_SHIFT,
3540 .idlest_reg_id = 1,
3541 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3542 },
3543 },
3544 .class = &omap3xxx_sham_class,
3545 };
3546
3547 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3548 {
3549 .pa_start = 0x480c3000,
3550 .pa_end = 0x480c3000 + 0x64 - 1,
3551 .flags = ADDR_TYPE_RT
3552 },
3553 { }
3554 };
3555
3556 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3557 .master = &omap3xxx_l4_core_hwmod,
3558 .slave = &omap3xxx_sham_hwmod,
3559 .clk = "sha12_ick",
3560 .addr = omap3xxx_sham_addrs,
3561 .user = OCP_USER_MPU | OCP_USER_SDMA,
3562 };
3563
3564 /* l4_core -> AES */
3565 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3566 .sidle_shift = 6,
3567 .srst_shift = 1,
3568 .autoidle_shift = 0,
3569 };
3570
3571 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3572 .rev_offs = 0x44,
3573 .sysc_offs = 0x48,
3574 .syss_offs = 0x4c,
3575 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3576 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3577 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3578 .sysc_fields = &omap3xxx_aes_sysc_fields,
3579 };
3580
3581 static struct omap_hwmod_class omap3xxx_aes_class = {
3582 .name = "aes",
3583 .sysc = &omap3_aes_sysc,
3584 };
3585
3586 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3587 { .name = "tx", .dma_req = 65, },
3588 { .name = "rx", .dma_req = 66, },
3589 { .dma_req = -1 }
3590 };
3591
3592 static struct omap_hwmod omap3xxx_aes_hwmod = {
3593 .name = "aes",
3594 .sdma_reqs = omap3_aes_sdma_reqs,
3595 .main_clk = "aes2_ick",
3596 .prcm = {
3597 .omap2 = {
3598 .module_offs = CORE_MOD,
3599 .prcm_reg_id = 1,
3600 .module_bit = OMAP3430_EN_AES2_SHIFT,
3601 .idlest_reg_id = 1,
3602 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3603 },
3604 },
3605 .class = &omap3xxx_aes_class,
3606 };
3607
3608 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3609 {
3610 .pa_start = 0x480c5000,
3611 .pa_end = 0x480c5000 + 0x50 - 1,
3612 .flags = ADDR_TYPE_RT
3613 },
3614 { }
3615 };
3616
3617 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3618 .master = &omap3xxx_l4_core_hwmod,
3619 .slave = &omap3xxx_aes_hwmod,
3620 .clk = "aes2_ick",
3621 .addr = omap3xxx_aes_addrs,
3622 .user = OCP_USER_MPU | OCP_USER_SDMA,
3623 };
3624
3625 /*
3626 * 'ssi' class
3627 * synchronous serial interface (multichannel and full-duplex serial if)
3628 */
3629
3630 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
3631 .rev_offs = 0x0000,
3632 .sysc_offs = 0x0010,
3633 .syss_offs = 0x0014,
3634 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
3635 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3636 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3637 .sysc_fields = &omap_hwmod_sysc_type1,
3638 };
3639
3640 static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
3641 .name = "ssi",
3642 .sysc = &omap34xx_ssi_sysc,
3643 };
3644
3645 static struct omap_hwmod omap34xx_ssi_hwmod = {
3646 .name = "ssi",
3647 .class = &omap34xx_ssi_hwmod_class,
3648 .clkdm_name = "core_l4_clkdm",
3649 .main_clk = "ssi_ssr_fck",
3650 .prcm = {
3651 .omap2 = {
3652 .prcm_reg_id = 1,
3653 .module_bit = OMAP3430_EN_SSI_SHIFT,
3654 .module_offs = CORE_MOD,
3655 .idlest_reg_id = 1,
3656 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
3657 },
3658 },
3659 };
3660
3661 /* L4 CORE -> SSI */
3662 static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
3663 .master = &omap3xxx_l4_core_hwmod,
3664 .slave = &omap34xx_ssi_hwmod,
3665 .clk = "ssi_ick",
3666 .user = OCP_USER_MPU | OCP_USER_SDMA,
3667 };
3668
3669 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3670 &omap3xxx_l3_main__l4_core,
3671 &omap3xxx_l3_main__l4_per,
3672 &omap3xxx_mpu__l3_main,
3673 &omap3xxx_l3_main__l4_debugss,
3674 &omap3xxx_l4_core__l4_wkup,
3675 &omap3xxx_l4_core__mmc3,
3676 &omap3_l4_core__uart1,
3677 &omap3_l4_core__uart2,
3678 &omap3_l4_per__uart3,
3679 &omap3_l4_core__i2c1,
3680 &omap3_l4_core__i2c2,
3681 &omap3_l4_core__i2c3,
3682 &omap3xxx_l4_wkup__l4_sec,
3683 &omap3xxx_l4_wkup__timer1,
3684 &omap3xxx_l4_per__timer2,
3685 &omap3xxx_l4_per__timer3,
3686 &omap3xxx_l4_per__timer4,
3687 &omap3xxx_l4_per__timer5,
3688 &omap3xxx_l4_per__timer6,
3689 &omap3xxx_l4_per__timer7,
3690 &omap3xxx_l4_per__timer8,
3691 &omap3xxx_l4_per__timer9,
3692 &omap3xxx_l4_core__timer10,
3693 &omap3xxx_l4_core__timer11,
3694 &omap3xxx_l4_wkup__wd_timer2,
3695 &omap3xxx_l4_wkup__gpio1,
3696 &omap3xxx_l4_per__gpio2,
3697 &omap3xxx_l4_per__gpio3,
3698 &omap3xxx_l4_per__gpio4,
3699 &omap3xxx_l4_per__gpio5,
3700 &omap3xxx_l4_per__gpio6,
3701 &omap3xxx_dma_system__l3,
3702 &omap3xxx_l4_core__dma_system,
3703 &omap3xxx_l4_core__mcbsp1,
3704 &omap3xxx_l4_per__mcbsp2,
3705 &omap3xxx_l4_per__mcbsp3,
3706 &omap3xxx_l4_per__mcbsp4,
3707 &omap3xxx_l4_core__mcbsp5,
3708 &omap3xxx_l4_per__mcbsp2_sidetone,
3709 &omap3xxx_l4_per__mcbsp3_sidetone,
3710 &omap34xx_l4_core__mcspi1,
3711 &omap34xx_l4_core__mcspi2,
3712 &omap34xx_l4_core__mcspi3,
3713 &omap34xx_l4_core__mcspi4,
3714 &omap3xxx_l4_wkup__counter_32k,
3715 &omap3xxx_l3_main__gpmc,
3716 NULL,
3717 };
3718
3719 /* GP-only hwmod links */
3720 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3721 &omap3xxx_l4_sec__timer12,
3722 NULL
3723 };
3724
3725 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3726 &omap3xxx_l4_sec__timer12,
3727 NULL
3728 };
3729
3730 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3731 &omap3xxx_l4_sec__timer12,
3732 NULL
3733 };
3734
3735 /* crypto hwmod links */
3736 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
3737 &omap3xxx_l4_core__sham,
3738 NULL
3739 };
3740
3741 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
3742 &omap3xxx_l4_core__aes,
3743 NULL
3744 };
3745
3746 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
3747 &omap3xxx_l4_core__sham,
3748 NULL
3749 };
3750
3751 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
3752 &omap3xxx_l4_core__aes,
3753 NULL
3754 };
3755
3756 /*
3757 * Apparently the SHA/MD5 and AES accelerator IP blocks are
3758 * only present on some AM35xx chips, and no one knows which
3759 * ones. See
3760 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3761 * if you need these IP blocks on an AM35xx, try uncommenting
3762 * the following lines.
3763 */
3764 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3765 /* &omap3xxx_l4_core__sham, */
3766 NULL
3767 };
3768
3769 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3770 /* &omap3xxx_l4_core__aes, */
3771 NULL
3772 };
3773
3774 /* 3430ES1-only hwmod links */
3775 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3776 &omap3430es1_dss__l3,
3777 &omap3430es1_l4_core__dss,
3778 NULL
3779 };
3780
3781 /* 3430ES2+-only hwmod links */
3782 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3783 &omap3xxx_dss__l3,
3784 &omap3xxx_l4_core__dss,
3785 &omap3xxx_usbhsotg__l3,
3786 &omap3xxx_l4_core__usbhsotg,
3787 &omap3xxx_usb_host_hs__l3_main_2,
3788 &omap3xxx_l4_core__usb_host_hs,
3789 &omap3xxx_l4_core__usb_tll_hs,
3790 NULL
3791 };
3792
3793 /* <= 3430ES3-only hwmod links */
3794 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3795 &omap3xxx_l4_core__pre_es3_mmc1,
3796 &omap3xxx_l4_core__pre_es3_mmc2,
3797 NULL
3798 };
3799
3800 /* 3430ES3+-only hwmod links */
3801 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3802 &omap3xxx_l4_core__es3plus_mmc1,
3803 &omap3xxx_l4_core__es3plus_mmc2,
3804 NULL
3805 };
3806
3807 /* 34xx-only hwmod links (all ES revisions) */
3808 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3809 &omap3xxx_l3__iva,
3810 &omap34xx_l4_core__sr1,
3811 &omap34xx_l4_core__sr2,
3812 &omap3xxx_l4_core__mailbox,
3813 &omap3xxx_l4_core__hdq1w,
3814 &omap3xxx_sad2d__l3,
3815 &omap3xxx_l4_core__mmu_isp,
3816 &omap3xxx_l3_main__mmu_iva,
3817 &omap34xx_l4_core__ssi,
3818 NULL
3819 };
3820
3821 /* 36xx-only hwmod links (all ES revisions) */
3822 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3823 &omap3xxx_l3__iva,
3824 &omap36xx_l4_per__uart4,
3825 &omap3xxx_dss__l3,
3826 &omap3xxx_l4_core__dss,
3827 &omap36xx_l4_core__sr1,
3828 &omap36xx_l4_core__sr2,
3829 &omap3xxx_usbhsotg__l3,
3830 &omap3xxx_l4_core__usbhsotg,
3831 &omap3xxx_l4_core__mailbox,
3832 &omap3xxx_usb_host_hs__l3_main_2,
3833 &omap3xxx_l4_core__usb_host_hs,
3834 &omap3xxx_l4_core__usb_tll_hs,
3835 &omap3xxx_l4_core__es3plus_mmc1,
3836 &omap3xxx_l4_core__es3plus_mmc2,
3837 &omap3xxx_l4_core__hdq1w,
3838 &omap3xxx_sad2d__l3,
3839 &omap3xxx_l4_core__mmu_isp,
3840 &omap3xxx_l3_main__mmu_iva,
3841 NULL
3842 };
3843
3844 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3845 &omap3xxx_dss__l3,
3846 &omap3xxx_l4_core__dss,
3847 &am35xx_usbhsotg__l3,
3848 &am35xx_l4_core__usbhsotg,
3849 &am35xx_l4_core__uart4,
3850 &omap3xxx_usb_host_hs__l3_main_2,
3851 &omap3xxx_l4_core__usb_host_hs,
3852 &omap3xxx_l4_core__usb_tll_hs,
3853 &omap3xxx_l4_core__es3plus_mmc1,
3854 &omap3xxx_l4_core__es3plus_mmc2,
3855 &omap3xxx_l4_core__hdq1w,
3856 &am35xx_mdio__l3,
3857 &am35xx_l4_core__mdio,
3858 &am35xx_emac__l3,
3859 &am35xx_l4_core__emac,
3860 NULL
3861 };
3862
3863 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3864 &omap3xxx_l4_core__dss_dispc,
3865 &omap3xxx_l4_core__dss_dsi1,
3866 &omap3xxx_l4_core__dss_rfbi,
3867 &omap3xxx_l4_core__dss_venc,
3868 NULL
3869 };
3870
3871 /**
3872 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
3873 * @bus: struct device_node * for the top-level OMAP DT data
3874 * @dev_name: device name used in the DT file
3875 *
3876 * Determine whether a "secure" IP block @dev_name is usable by Linux.
3877 * There doesn't appear to be a 100% reliable way to determine this,
3878 * so we rely on heuristics. If @bus is null, meaning there's no DT
3879 * data, then we only assume the IP block is accessible if the OMAP is
3880 * fused as a 'general-purpose' SoC. If however DT data is present,
3881 * test to see if the IP block is described in the DT data and set to
3882 * 'status = "okay"'. If so then we assume the ODM has configured the
3883 * OMAP firewalls to allow access to the IP block.
3884 *
3885 * Return: 0 if device named @dev_name is not likely to be accessible,
3886 * or 1 if it is likely to be accessible.
3887 */
omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node * bus,const char * dev_name)3888 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
3889 const char *dev_name)
3890 {
3891 struct device_node *node;
3892 bool available;
3893
3894 if (!bus)
3895 return omap_type() == OMAP2_DEVICE_TYPE_GP;
3896
3897 node = of_get_child_by_name(bus, dev_name);
3898 available = of_device_is_available(node);
3899 of_node_put(node);
3900
3901 return available;
3902 }
3903
omap3xxx_hwmod_init(void)3904 int __init omap3xxx_hwmod_init(void)
3905 {
3906 int r;
3907 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
3908 struct omap_hwmod_ocp_if **h_aes = NULL;
3909 struct device_node *bus = NULL;
3910 unsigned int rev;
3911
3912 omap_hwmod_init();
3913
3914 /* Register hwmod links common to all OMAP3 */
3915 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3916 if (r < 0)
3917 return r;
3918
3919 rev = omap_rev();
3920
3921 /*
3922 * Register hwmod links common to individual OMAP3 families, all
3923 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3924 * All possible revisions should be included in this conditional.
3925 */
3926 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3927 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3928 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3929 h = omap34xx_hwmod_ocp_ifs;
3930 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3931 h_sham = omap34xx_sham_hwmod_ocp_ifs;
3932 h_aes = omap34xx_aes_hwmod_ocp_ifs;
3933 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3934 h = am35xx_hwmod_ocp_ifs;
3935 h_gp = am35xx_gp_hwmod_ocp_ifs;
3936 h_sham = am35xx_sham_hwmod_ocp_ifs;
3937 h_aes = am35xx_aes_hwmod_ocp_ifs;
3938 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3939 rev == OMAP3630_REV_ES1_2) {
3940 h = omap36xx_hwmod_ocp_ifs;
3941 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3942 h_sham = omap36xx_sham_hwmod_ocp_ifs;
3943 h_aes = omap36xx_aes_hwmod_ocp_ifs;
3944 } else {
3945 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3946 return -EINVAL;
3947 }
3948
3949 r = omap_hwmod_register_links(h);
3950 if (r < 0)
3951 return r;
3952
3953 /* Register GP-only hwmod links. */
3954 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3955 r = omap_hwmod_register_links(h_gp);
3956 if (r < 0)
3957 return r;
3958 }
3959
3960 /*
3961 * Register crypto hwmod links only if they are not disabled in DT.
3962 * If DT information is missing, enable them only for GP devices.
3963 */
3964
3965 if (of_have_populated_dt())
3966 bus = of_find_node_by_name(NULL, "ocp");
3967
3968 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
3969 r = omap_hwmod_register_links(h_sham);
3970 if (r < 0) {
3971 of_node_put(bus);
3972 return r;
3973 }
3974 }
3975
3976 if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
3977 r = omap_hwmod_register_links(h_aes);
3978 if (r < 0) {
3979 of_node_put(bus);
3980 return r;
3981 }
3982 }
3983 of_node_put(bus);
3984
3985 /*
3986 * Register hwmod links specific to certain ES levels of a
3987 * particular family of silicon (e.g., 34xx ES1.0)
3988 */
3989 h = NULL;
3990 if (rev == OMAP3430_REV_ES1_0) {
3991 h = omap3430es1_hwmod_ocp_ifs;
3992 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3993 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3994 rev == OMAP3430_REV_ES3_1_2) {
3995 h = omap3430es2plus_hwmod_ocp_ifs;
3996 }
3997
3998 if (h) {
3999 r = omap_hwmod_register_links(h);
4000 if (r < 0)
4001 return r;
4002 }
4003
4004 h = NULL;
4005 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
4006 rev == OMAP3430_REV_ES2_1) {
4007 h = omap3430_pre_es3_hwmod_ocp_ifs;
4008 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
4009 rev == OMAP3430_REV_ES3_1_2) {
4010 h = omap3430_es3plus_hwmod_ocp_ifs;
4011 }
4012
4013 if (h)
4014 r = omap_hwmod_register_links(h);
4015 if (r < 0)
4016 return r;
4017
4018 /*
4019 * DSS code presumes that dss_core hwmod is handled first,
4020 * _before_ any other DSS related hwmods so register common
4021 * DSS hwmod links last to ensure that dss_core is already
4022 * registered. Otherwise some change things may happen, for
4023 * ex. if dispc is handled before dss_core and DSS is enabled
4024 * in bootloader DISPC will be reset with outputs enabled
4025 * which sometimes leads to unrecoverable L3 error. XXX The
4026 * long-term fix to this is to ensure hwmods are set up in
4027 * dependency order in the hwmod core code.
4028 */
4029 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
4030
4031 return r;
4032 }
4033