1 /* 2 * arch/arm/mach-sa1100/include/mach/irqs.h 3 * 4 * Copyright (C) 1996 Russell King 5 * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). 6 * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) 7 * 8 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. 9 */ 10 11 #define IRQ_GPIO0_SC 1 12 #define IRQ_GPIO1_SC 2 13 #define IRQ_GPIO2_SC 3 14 #define IRQ_GPIO3_SC 4 15 #define IRQ_GPIO4_SC 5 16 #define IRQ_GPIO5_SC 6 17 #define IRQ_GPIO6_SC 7 18 #define IRQ_GPIO7_SC 8 19 #define IRQ_GPIO8_SC 9 20 #define IRQ_GPIO9_SC 10 21 #define IRQ_GPIO10_SC 11 22 #define IRQ_GPIO11_27 12 23 #define IRQ_LCD 13 /* LCD controller */ 24 #define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */ 25 #define IRQ_Ser1SDLC 15 /* Ser. port 1 SDLC */ 26 #define IRQ_Ser1UART 16 /* Ser. port 1 UART */ 27 #define IRQ_Ser2ICP 17 /* Ser. port 2 ICP */ 28 #define IRQ_Ser3UART 18 /* Ser. port 3 UART */ 29 #define IRQ_Ser4MCP 19 /* Ser. port 4 MCP */ 30 #define IRQ_Ser4SSP 20 /* Ser. port 4 SSP */ 31 #define IRQ_DMA0 21 /* DMA controller channel 0 */ 32 #define IRQ_DMA1 22 /* DMA controller channel 1 */ 33 #define IRQ_DMA2 23 /* DMA controller channel 2 */ 34 #define IRQ_DMA3 24 /* DMA controller channel 3 */ 35 #define IRQ_DMA4 25 /* DMA controller channel 4 */ 36 #define IRQ_DMA5 26 /* DMA controller channel 5 */ 37 #define IRQ_OST0 27 /* OS Timer match 0 */ 38 #define IRQ_OST1 28 /* OS Timer match 1 */ 39 #define IRQ_OST2 29 /* OS Timer match 2 */ 40 #define IRQ_OST3 30 /* OS Timer match 3 */ 41 #define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */ 42 #define IRQ_RTCAlrm 32 /* RTC Alarm */ 43 44 #define IRQ_GPIO0 33 45 #define IRQ_GPIO1 34 46 #define IRQ_GPIO2 35 47 #define IRQ_GPIO3 36 48 #define IRQ_GPIO4 37 49 #define IRQ_GPIO5 38 50 #define IRQ_GPIO6 39 51 #define IRQ_GPIO7 40 52 #define IRQ_GPIO8 41 53 #define IRQ_GPIO9 42 54 #define IRQ_GPIO10 43 55 #define IRQ_GPIO11 44 56 #define IRQ_GPIO12 45 57 #define IRQ_GPIO13 46 58 #define IRQ_GPIO14 47 59 #define IRQ_GPIO15 48 60 #define IRQ_GPIO16 49 61 #define IRQ_GPIO17 50 62 #define IRQ_GPIO18 51 63 #define IRQ_GPIO19 52 64 #define IRQ_GPIO20 53 65 #define IRQ_GPIO21 54 66 #define IRQ_GPIO22 55 67 #define IRQ_GPIO23 56 68 #define IRQ_GPIO24 57 69 #define IRQ_GPIO25 58 70 #define IRQ_GPIO26 59 71 #define IRQ_GPIO27 60 72 73 /* 74 * The next 16 interrupts are for board specific purposes. Since 75 * the kernel can only run on one machine at a time, we can re-use 76 * these. If you need more, increase IRQ_BOARD_END, but keep it 77 * within sensible limits. IRQs 61 to 76 are available. 78 */ 79 #define IRQ_BOARD_START 61 80 #define IRQ_BOARD_END 77 81 82 /* 83 * Figure out the MAX IRQ number. 84 * 85 * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically 86 * allocate their IRQs above NR_IRQS. 87 * 88 * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has 89 * to be included in the NR_IRQS calculation. 90 */ 91 #ifdef CONFIG_SHARP_LOCOMO 92 #define NR_IRQS_LOCOMO 4 93 #else 94 #define NR_IRQS_LOCOMO 0 95 #endif 96 97 #ifndef NR_IRQS 98 #define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 99 #endif 100 #define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 101