1/* 2 * ARM Ltd. 3 * 4 * ARMv8 Foundation model DTS 5 */ 6 7/dts-v1/; 8 9/memreserve/ 0x80000000 0x00010000; 10 11/ { 12 model = "Foundation-v8A"; 13 compatible = "arm,foundation-aarch64", "arm,vexpress"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 aliases { 21 serial0 = &v2m_serial0; 22 serial1 = &v2m_serial1; 23 serial2 = &v2m_serial2; 24 serial3 = &v2m_serial3; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,armv8"; 34 reg = <0x0 0x0>; 35 enable-method = "spin-table"; 36 cpu-release-addr = <0x0 0x8000fff8>; 37 next-level-cache = <&L2_0>; 38 }; 39 cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,armv8"; 42 reg = <0x0 0x1>; 43 enable-method = "spin-table"; 44 cpu-release-addr = <0x0 0x8000fff8>; 45 next-level-cache = <&L2_0>; 46 }; 47 cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,armv8"; 50 reg = <0x0 0x2>; 51 enable-method = "spin-table"; 52 cpu-release-addr = <0x0 0x8000fff8>; 53 next-level-cache = <&L2_0>; 54 }; 55 cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,armv8"; 58 reg = <0x0 0x3>; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0x8000fff8>; 61 next-level-cache = <&L2_0>; 62 }; 63 64 L2_0: l2-cache0 { 65 compatible = "cache"; 66 }; 67 }; 68 69 memory@80000000 { 70 device_type = "memory"; 71 reg = <0x00000000 0x80000000 0 0x80000000>, 72 <0x00000008 0x80000000 0 0x80000000>; 73 }; 74 75 gic: interrupt-controller@2c001000 { 76 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 77 #interrupt-cells = <3>; 78 #address-cells = <0>; 79 interrupt-controller; 80 reg = <0x0 0x2c001000 0 0x1000>, 81 <0x0 0x2c002000 0 0x1000>, 82 <0x0 0x2c004000 0 0x2000>, 83 <0x0 0x2c006000 0 0x2000>; 84 interrupts = <1 9 0xf04>; 85 }; 86 87 timer { 88 compatible = "arm,armv8-timer"; 89 interrupts = <1 13 0xf08>, 90 <1 14 0xf08>, 91 <1 11 0xf08>, 92 <1 10 0xf08>; 93 clock-frequency = <100000000>; 94 }; 95 96 pmu { 97 compatible = "arm,armv8-pmuv3"; 98 interrupts = <0 60 4>, 99 <0 61 4>, 100 <0 62 4>, 101 <0 63 4>; 102 }; 103 104 smb { 105 compatible = "arm,vexpress,v2m-p1", "simple-bus"; 106 arm,v2m-memory-map = "rs1"; 107 #address-cells = <2>; /* SMB chipselect number and offset */ 108 #size-cells = <1>; 109 110 ranges = <0 0 0 0x08000000 0x04000000>, 111 <1 0 0 0x14000000 0x04000000>, 112 <2 0 0 0x18000000 0x04000000>, 113 <3 0 0 0x1c000000 0x04000000>, 114 <4 0 0 0x0c000000 0x04000000>, 115 <5 0 0 0x10000000 0x04000000>; 116 117 #interrupt-cells = <1>; 118 interrupt-map-mask = <0 0 63>; 119 interrupt-map = <0 0 0 &gic 0 0 4>, 120 <0 0 1 &gic 0 1 4>, 121 <0 0 2 &gic 0 2 4>, 122 <0 0 3 &gic 0 3 4>, 123 <0 0 4 &gic 0 4 4>, 124 <0 0 5 &gic 0 5 4>, 125 <0 0 6 &gic 0 6 4>, 126 <0 0 7 &gic 0 7 4>, 127 <0 0 8 &gic 0 8 4>, 128 <0 0 9 &gic 0 9 4>, 129 <0 0 10 &gic 0 10 4>, 130 <0 0 11 &gic 0 11 4>, 131 <0 0 12 &gic 0 12 4>, 132 <0 0 13 &gic 0 13 4>, 133 <0 0 14 &gic 0 14 4>, 134 <0 0 15 &gic 0 15 4>, 135 <0 0 16 &gic 0 16 4>, 136 <0 0 17 &gic 0 17 4>, 137 <0 0 18 &gic 0 18 4>, 138 <0 0 19 &gic 0 19 4>, 139 <0 0 20 &gic 0 20 4>, 140 <0 0 21 &gic 0 21 4>, 141 <0 0 22 &gic 0 22 4>, 142 <0 0 23 &gic 0 23 4>, 143 <0 0 24 &gic 0 24 4>, 144 <0 0 25 &gic 0 25 4>, 145 <0 0 26 &gic 0 26 4>, 146 <0 0 27 &gic 0 27 4>, 147 <0 0 28 &gic 0 28 4>, 148 <0 0 29 &gic 0 29 4>, 149 <0 0 30 &gic 0 30 4>, 150 <0 0 31 &gic 0 31 4>, 151 <0 0 32 &gic 0 32 4>, 152 <0 0 33 &gic 0 33 4>, 153 <0 0 34 &gic 0 34 4>, 154 <0 0 35 &gic 0 35 4>, 155 <0 0 36 &gic 0 36 4>, 156 <0 0 37 &gic 0 37 4>, 157 <0 0 38 &gic 0 38 4>, 158 <0 0 39 &gic 0 39 4>, 159 <0 0 40 &gic 0 40 4>, 160 <0 0 41 &gic 0 41 4>, 161 <0 0 42 &gic 0 42 4>; 162 163 ethernet@2,02000000 { 164 compatible = "smsc,lan91c111"; 165 reg = <2 0x02000000 0x10000>; 166 interrupts = <15>; 167 }; 168 169 v2m_clk24mhz: clk24mhz { 170 compatible = "fixed-clock"; 171 #clock-cells = <0>; 172 clock-frequency = <24000000>; 173 clock-output-names = "v2m:clk24mhz"; 174 }; 175 176 v2m_refclk1mhz: refclk1mhz { 177 compatible = "fixed-clock"; 178 #clock-cells = <0>; 179 clock-frequency = <1000000>; 180 clock-output-names = "v2m:refclk1mhz"; 181 }; 182 183 v2m_refclk32khz: refclk32khz { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-frequency = <32768>; 187 clock-output-names = "v2m:refclk32khz"; 188 }; 189 190 iofpga@3,00000000 { 191 compatible = "arm,amba-bus", "simple-bus"; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 ranges = <0 3 0 0x200000>; 195 196 v2m_sysreg: sysreg@010000 { 197 compatible = "arm,vexpress-sysreg"; 198 reg = <0x010000 0x1000>; 199 }; 200 201 v2m_serial0: uart@090000 { 202 compatible = "arm,pl011", "arm,primecell"; 203 reg = <0x090000 0x1000>; 204 interrupts = <5>; 205 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 206 clock-names = "uartclk", "apb_pclk"; 207 }; 208 209 v2m_serial1: uart@0a0000 { 210 compatible = "arm,pl011", "arm,primecell"; 211 reg = <0x0a0000 0x1000>; 212 interrupts = <6>; 213 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 214 clock-names = "uartclk", "apb_pclk"; 215 }; 216 217 v2m_serial2: uart@0b0000 { 218 compatible = "arm,pl011", "arm,primecell"; 219 reg = <0x0b0000 0x1000>; 220 interrupts = <7>; 221 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 222 clock-names = "uartclk", "apb_pclk"; 223 }; 224 225 v2m_serial3: uart@0c0000 { 226 compatible = "arm,pl011", "arm,primecell"; 227 reg = <0x0c0000 0x1000>; 228 interrupts = <8>; 229 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; 230 clock-names = "uartclk", "apb_pclk"; 231 }; 232 233 virtio_block@0130000 { 234 compatible = "virtio,mmio"; 235 reg = <0x130000 0x200>; 236 interrupts = <42>; 237 }; 238 }; 239 }; 240}; 241