1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/memreserve/ 0x81000000 0x00200000; 34 35#include <dt-bindings/interrupt-controller/arm-gic.h> 36 37/memreserve/ 0x84b00000 0x00000008; 38 39/ { 40 compatible = "brcm,ns2"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a57", "arm,armv8"; 52 reg = <0 0>; 53 enable-method = "spin-table"; 54 cpu-release-addr = <0 0x84b00000>; 55 }; 56 57 cpu@1 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a57", "arm,armv8"; 60 reg = <0 1>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0 0x84b00000>; 63 }; 64 65 cpu@2 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a57", "arm,armv8"; 68 reg = <0 2>; 69 enable-method = "spin-table"; 70 cpu-release-addr = <0 0x84b00000>; 71 }; 72 73 cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a57", "arm,armv8"; 76 reg = <0 3>; 77 enable-method = "spin-table"; 78 cpu-release-addr = <0 0x84b00000>; 79 }; 80 }; 81 82 timer { 83 compatible = "arm,armv8-timer"; 84 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | 85 IRQ_TYPE_EDGE_RISING)>, 86 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | 87 IRQ_TYPE_EDGE_RISING)>, 88 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | 89 IRQ_TYPE_EDGE_RISING)>, 90 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | 91 IRQ_TYPE_EDGE_RISING)>; 92 }; 93 94 soc: soc { 95 compatible = "simple-bus"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges = <0 0 0 0xffffffff>; 99 100 gic: interrupt-controller@65210000 { 101 compatible = "arm,gic-400"; 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 reg = <0x65210000 0x1000>, 105 <0x65220000 0x1000>, 106 <0x65240000 0x2000>, 107 <0x65260000 0x1000>; 108 }; 109 110 uart3: serial@66130000 { 111 compatible = "snps,dw-apb-uart"; 112 reg = <0x66130000 0x100>; 113 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 114 reg-shift = <2>; 115 reg-io-width = <4>; 116 clock-frequency = <23961600>; 117 status = "disabled"; 118 }; 119 }; 120}; 121