1/* 2 * Copyright (C) 2015 Marvell Technology Group Ltd. 3 * 4 * Author: Jisheng Zhang <jszhang@marvell.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPLv2 or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46 47/ { 48 compatible = "marvell,berlin4ct", "marvell,berlin"; 49 interrupt-parent = <&gic>; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 53 aliases { 54 serial0 = &uart0; 55 }; 56 57 psci { 58 compatible = "arm,psci-0.2"; 59 method = "smc"; 60 }; 61 62 cpus { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 cpu0: cpu@0 { 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 device_type = "cpu"; 69 reg = <0x0>; 70 enable-method = "psci"; 71 }; 72 73 cpu1: cpu@1 { 74 compatible = "arm,cortex-a53", "arm,armv8"; 75 device_type = "cpu"; 76 reg = <0x1>; 77 enable-method = "psci"; 78 }; 79 80 cpu2: cpu@2 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <0x2>; 84 enable-method = "psci"; 85 }; 86 87 cpu3: cpu@3 { 88 compatible = "arm,cortex-a53", "arm,armv8"; 89 device_type = "cpu"; 90 reg = <0x3>; 91 enable-method = "psci"; 92 }; 93 }; 94 95 osc: osc { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <25000000>; 99 }; 100 101 pmu { 102 compatible = "arm,armv8-pmuv3"; 103 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 107 interrupt-affinity = <&cpu0>, 108 <&cpu1>, 109 <&cpu2>, 110 <&cpu3>; 111 }; 112 113 timer { 114 compatible = "arm,armv8-timer"; 115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 119 }; 120 121 soc { 122 compatible = "simple-bus"; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0 0 0xf7000000 0x1000000>; 126 127 gic: interrupt-controller@901000 { 128 compatible = "arm,gic-400"; 129 #interrupt-cells = <3>; 130 interrupt-controller; 131 reg = <0x901000 0x1000>, 132 <0x902000 0x2000>, 133 <0x904000 0x2000>, 134 <0x906000 0x2000>; 135 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 136 }; 137 138 apb@e80000 { 139 compatible = "simple-bus"; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 143 ranges = <0 0xe80000 0x10000>; 144 interrupt-parent = <&aic>; 145 146 gpio0: gpio@0400 { 147 compatible = "snps,dw-apb-gpio"; 148 reg = <0x0400 0x400>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 152 porta: gpio-port@0 { 153 compatible = "snps,dw-apb-gpio-port"; 154 gpio-controller; 155 #gpio-cells = <2>; 156 snps,nr-gpios = <32>; 157 reg = <0>; 158 interrupt-controller; 159 #interrupt-cells = <2>; 160 interrupts = <0>; 161 }; 162 }; 163 164 gpio1: gpio@0800 { 165 compatible = "snps,dw-apb-gpio"; 166 reg = <0x0800 0x400>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 portb: gpio-port@1 { 171 compatible = "snps,dw-apb-gpio-port"; 172 gpio-controller; 173 #gpio-cells = <2>; 174 snps,nr-gpios = <32>; 175 reg = <0>; 176 interrupt-controller; 177 #interrupt-cells = <2>; 178 interrupts = <1>; 179 }; 180 }; 181 182 gpio2: gpio@0c00 { 183 compatible = "snps,dw-apb-gpio"; 184 reg = <0x0c00 0x400>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 portc: gpio-port@2 { 189 compatible = "snps,dw-apb-gpio-port"; 190 gpio-controller; 191 #gpio-cells = <2>; 192 snps,nr-gpios = <32>; 193 reg = <0>; 194 interrupt-controller; 195 #interrupt-cells = <2>; 196 interrupts = <2>; 197 }; 198 }; 199 200 gpio3: gpio@1000 { 201 compatible = "snps,dw-apb-gpio"; 202 reg = <0x1000 0x400>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 206 portd: gpio-port@3 { 207 compatible = "snps,dw-apb-gpio-port"; 208 gpio-controller; 209 #gpio-cells = <2>; 210 snps,nr-gpios = <32>; 211 reg = <0>; 212 interrupt-controller; 213 #interrupt-cells = <2>; 214 interrupts = <3>; 215 }; 216 }; 217 218 aic: interrupt-controller@3800 { 219 compatible = "snps,dw-apb-ictl"; 220 reg = <0x3800 0x30>; 221 interrupt-controller; 222 #interrupt-cells = <1>; 223 interrupt-parent = <&gic>; 224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 225 }; 226 }; 227 228 apb@fc0000 { 229 compatible = "simple-bus"; 230 #address-cells = <1>; 231 #size-cells = <1>; 232 ranges = <0 0xfc0000 0x10000>; 233 interrupt-parent = <&sic>; 234 235 sic: interrupt-controller@1000 { 236 compatible = "snps,dw-apb-ictl"; 237 reg = <0x1000 0x30>; 238 interrupt-controller; 239 #interrupt-cells = <1>; 240 interrupt-parent = <&gic>; 241 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 242 }; 243 244 sm_gpio0: gpio@8000 { 245 compatible = "snps,dw-apb-gpio"; 246 reg = <0x8000 0x400>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 250 porte: gpio-port@4 { 251 compatible = "snps,dw-apb-gpio-port"; 252 gpio-controller; 253 #gpio-cells = <2>; 254 snps,nr-gpios = <32>; 255 reg = <0>; 256 }; 257 }; 258 259 sm_gpio1: gpio@9000 { 260 compatible = "snps,dw-apb-gpio"; 261 reg = <0x9000 0x400>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 portf: gpio-port@5 { 266 compatible = "snps,dw-apb-gpio-port"; 267 gpio-controller; 268 #gpio-cells = <2>; 269 snps,nr-gpios = <32>; 270 reg = <0>; 271 }; 272 }; 273 274 uart0: uart@d000 { 275 compatible = "snps,dw-apb-uart"; 276 reg = <0xd000 0x100>; 277 interrupts = <8>; 278 clocks = <&osc>; 279 reg-shift = <2>; 280 status = "disabled"; 281 }; 282 }; 283 }; 284}; 285