1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3368-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48 49/ { 50 compatible = "rockchip,rk3368"; 51 interrupt-parent = <&gic>; 52 #address-cells = <2>; 53 #size-cells = <2>; 54 55 aliases { 56 i2c0 = &i2c0; 57 i2c1 = &i2c1; 58 i2c2 = &i2c2; 59 i2c3 = &i2c3; 60 i2c4 = &i2c4; 61 i2c5 = &i2c5; 62 serial0 = &uart0; 63 serial1 = &uart1; 64 serial2 = &uart2; 65 serial3 = &uart3; 66 serial4 = &uart4; 67 spi0 = &spi0; 68 spi1 = &spi1; 69 spi2 = &spi2; 70 }; 71 72 cpus { 73 #address-cells = <0x2>; 74 #size-cells = <0x0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu_b0>; 80 }; 81 core1 { 82 cpu = <&cpu_b1>; 83 }; 84 core2 { 85 cpu = <&cpu_b2>; 86 }; 87 core3 { 88 cpu = <&cpu_b3>; 89 }; 90 }; 91 92 cluster1 { 93 core0 { 94 cpu = <&cpu_l0>; 95 }; 96 core1 { 97 cpu = <&cpu_l1>; 98 }; 99 core2 { 100 cpu = <&cpu_l2>; 101 }; 102 core3 { 103 cpu = <&cpu_l3>; 104 }; 105 }; 106 }; 107 108 idle-states { 109 entry-method = "psci"; 110 111 cpu_sleep: cpu-sleep-0 { 112 compatible = "arm,idle-state"; 113 arm,psci-suspend-param = <0x1010000>; 114 entry-latency-us = <0x3fffffff>; 115 exit-latency-us = <0x40000000>; 116 min-residency-us = <0xffffffff>; 117 }; 118 }; 119 120 cpu_l0: cpu@0 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53", "arm,armv8"; 123 reg = <0x0 0x0>; 124 cpu-idle-states = <&cpu_sleep>; 125 enable-method = "psci"; 126 }; 127 128 cpu_l1: cpu@1 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a53", "arm,armv8"; 131 reg = <0x0 0x1>; 132 cpu-idle-states = <&cpu_sleep>; 133 enable-method = "psci"; 134 }; 135 136 cpu_l2: cpu@2 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a53", "arm,armv8"; 139 reg = <0x0 0x2>; 140 cpu-idle-states = <&cpu_sleep>; 141 enable-method = "psci"; 142 }; 143 144 cpu_l3: cpu@3 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a53", "arm,armv8"; 147 reg = <0x0 0x3>; 148 cpu-idle-states = <&cpu_sleep>; 149 enable-method = "psci"; 150 }; 151 152 cpu_b0: cpu@100 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a53", "arm,armv8"; 155 reg = <0x0 0x100>; 156 cpu-idle-states = <&cpu_sleep>; 157 enable-method = "psci"; 158 }; 159 160 cpu_b1: cpu@101 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a53", "arm,armv8"; 163 reg = <0x0 0x101>; 164 cpu-idle-states = <&cpu_sleep>; 165 enable-method = "psci"; 166 }; 167 168 cpu_b2: cpu@102 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a53", "arm,armv8"; 171 reg = <0x0 0x102>; 172 cpu-idle-states = <&cpu_sleep>; 173 enable-method = "psci"; 174 }; 175 176 cpu_b3: cpu@103 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-a53", "arm,armv8"; 179 reg = <0x0 0x103>; 180 cpu-idle-states = <&cpu_sleep>; 181 enable-method = "psci"; 182 }; 183 }; 184 185 arm-pmu { 186 compatible = "arm,armv8-pmuv3"; 187 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 195 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 196 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 197 <&cpu_b2>, <&cpu_b3>; 198 }; 199 200 psci { 201 compatible = "arm,psci-0.2"; 202 method = "smc"; 203 }; 204 205 timer { 206 compatible = "arm,armv8-timer"; 207 interrupts = <GIC_PPI 13 208 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 209 <GIC_PPI 14 210 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 211 <GIC_PPI 11 212 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 213 <GIC_PPI 10 214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 215 }; 216 217 xin24m: oscillator { 218 compatible = "fixed-clock"; 219 clock-frequency = <24000000>; 220 clock-output-names = "xin24m"; 221 #clock-cells = <0>; 222 }; 223 224 sdmmc: dwmmc@ff0c0000 { 225 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 226 reg = <0x0 0xff0c0000 0x0 0x4000>; 227 clock-freq-min-max = <400000 150000000>; 228 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 229 clock-names = "biu", "ciu"; 230 fifo-depth = <0x100>; 231 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 232 status = "disabled"; 233 }; 234 235 sdio0: dwmmc@ff0d0000 { 236 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 237 reg = <0x0 0xff0d0000 0x0 0x4000>; 238 clock-freq-min-max = <400000 150000000>; 239 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 240 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 241 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 242 fifo-depth = <0x100>; 243 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 244 status = "disabled"; 245 }; 246 247 emmc: dwmmc@ff0f0000 { 248 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 249 reg = <0x0 0xff0f0000 0x0 0x4000>; 250 clock-freq-min-max = <400000 150000000>; 251 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 252 clock-names = "biu", "ciu"; 253 fifo-depth = <0x100>; 254 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 255 status = "disabled"; 256 }; 257 258 saradc: saradc@ff100000 { 259 compatible = "rockchip,saradc"; 260 reg = <0x0 0xff100000 0x0 0x100>; 261 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 262 #io-channel-cells = <1>; 263 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 264 clock-names = "saradc", "apb_pclk"; 265 resets = <&cru SRST_SARADC>; 266 reset-names = "saradc-apb"; 267 status = "disabled"; 268 }; 269 270 spi0: spi@ff110000 { 271 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 272 reg = <0x0 0xff110000 0x0 0x1000>; 273 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 274 clock-names = "spiclk", "apb_pclk"; 275 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 status = "disabled"; 281 }; 282 283 spi1: spi@ff120000 { 284 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 285 reg = <0x0 0xff120000 0x0 0x1000>; 286 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 287 clock-names = "spiclk", "apb_pclk"; 288 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 status = "disabled"; 294 }; 295 296 spi2: spi@ff130000 { 297 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 298 reg = <0x0 0xff130000 0x0 0x1000>; 299 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 300 clock-names = "spiclk", "apb_pclk"; 301 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 i2c1: i2c@ff140000 { 310 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 311 reg = <0x0 0xff140000 0x0 0x1000>; 312 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 clock-names = "i2c"; 316 clocks = <&cru PCLK_I2C1>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&i2c1_xfer>; 319 status = "disabled"; 320 }; 321 322 i2c3: i2c@ff150000 { 323 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 324 reg = <0x0 0xff150000 0x0 0x1000>; 325 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clock-names = "i2c"; 329 clocks = <&cru PCLK_I2C3>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&i2c3_xfer>; 332 status = "disabled"; 333 }; 334 335 i2c4: i2c@ff160000 { 336 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 337 reg = <0x0 0xff160000 0x0 0x1000>; 338 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 clock-names = "i2c"; 342 clocks = <&cru PCLK_I2C4>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&i2c4_xfer>; 345 status = "disabled"; 346 }; 347 348 i2c5: i2c@ff170000 { 349 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 350 reg = <0x0 0xff170000 0x0 0x1000>; 351 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 clock-names = "i2c"; 355 clocks = <&cru PCLK_I2C5>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&i2c5_xfer>; 358 status = "disabled"; 359 }; 360 361 uart0: serial@ff180000 { 362 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 363 reg = <0x0 0xff180000 0x0 0x100>; 364 clock-frequency = <24000000>; 365 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 366 clock-names = "baudclk", "apb_pclk"; 367 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 368 reg-shift = <2>; 369 reg-io-width = <4>; 370 status = "disabled"; 371 }; 372 373 uart1: serial@ff190000 { 374 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 375 reg = <0x0 0xff190000 0x0 0x100>; 376 clock-frequency = <24000000>; 377 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 378 clock-names = "baudclk", "apb_pclk"; 379 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 380 reg-shift = <2>; 381 reg-io-width = <4>; 382 status = "disabled"; 383 }; 384 385 uart3: serial@ff1b0000 { 386 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 387 reg = <0x0 0xff1b0000 0x0 0x100>; 388 clock-frequency = <24000000>; 389 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 390 clock-names = "baudclk", "apb_pclk"; 391 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 392 reg-shift = <2>; 393 reg-io-width = <4>; 394 status = "disabled"; 395 }; 396 397 uart4: serial@ff1c0000 { 398 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 399 reg = <0x0 0xff1c0000 0x0 0x100>; 400 clock-frequency = <24000000>; 401 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 402 clock-names = "baudclk", "apb_pclk"; 403 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 404 reg-shift = <2>; 405 reg-io-width = <4>; 406 status = "disabled"; 407 }; 408 409 gmac: ethernet@ff290000 { 410 compatible = "rockchip,rk3368-gmac"; 411 reg = <0x0 0xff290000 0x0 0x10000>; 412 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "macirq"; 414 rockchip,grf = <&grf>; 415 clocks = <&cru SCLK_MAC>, 416 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 417 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 418 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 419 clock-names = "stmmaceth", 420 "mac_clk_rx", "mac_clk_tx", 421 "clk_mac_ref", "clk_mac_refout", 422 "aclk_mac", "pclk_mac"; 423 status = "disabled"; 424 }; 425 426 usb_host0_ehci: usb@ff500000 { 427 compatible = "generic-ehci"; 428 reg = <0x0 0xff500000 0x0 0x100>; 429 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cru HCLK_HOST0>; 431 clock-names = "usbhost"; 432 status = "disabled"; 433 }; 434 435 usb_otg: usb@ff580000 { 436 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 437 "snps,dwc2"; 438 reg = <0x0 0xff580000 0x0 0x40000>; 439 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cru HCLK_OTG0>; 441 clock-names = "otg"; 442 dr_mode = "otg"; 443 g-np-tx-fifo-size = <16>; 444 g-rx-fifo-size = <275>; 445 g-tx-fifo-size = <256 128 128 64 64 32>; 446 g-use-dma; 447 status = "disabled"; 448 }; 449 450 i2c0: i2c@ff650000 { 451 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 452 reg = <0x0 0xff650000 0x0 0x1000>; 453 clocks = <&cru PCLK_I2C0>; 454 clock-names = "i2c"; 455 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&i2c0_xfer>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 status = "disabled"; 461 }; 462 463 i2c2: i2c@ff660000 { 464 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 465 reg = <0x0 0xff660000 0x0 0x1000>; 466 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 clock-names = "i2c"; 470 clocks = <&cru PCLK_I2C2>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&i2c2_xfer>; 473 status = "disabled"; 474 }; 475 476 uart2: serial@ff690000 { 477 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 478 reg = <0x0 0xff690000 0x0 0x100>; 479 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 480 clock-names = "baudclk", "apb_pclk"; 481 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&uart2_xfer>; 484 reg-shift = <2>; 485 reg-io-width = <4>; 486 status = "disabled"; 487 }; 488 489 pmugrf: syscon@ff738000 { 490 compatible = "rockchip,rk3368-pmugrf", "syscon"; 491 reg = <0x0 0xff738000 0x0 0x1000>; 492 }; 493 494 cru: clock-controller@ff760000 { 495 compatible = "rockchip,rk3368-cru"; 496 reg = <0x0 0xff760000 0x0 0x1000>; 497 rockchip,grf = <&grf>; 498 #clock-cells = <1>; 499 #reset-cells = <1>; 500 }; 501 502 grf: syscon@ff770000 { 503 compatible = "rockchip,rk3368-grf", "syscon"; 504 reg = <0x0 0xff770000 0x0 0x1000>; 505 }; 506 507 wdt: watchdog@ff800000 { 508 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 509 reg = <0x0 0xff800000 0x0 0x100>; 510 clocks = <&cru PCLK_WDT>; 511 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 512 status = "disabled"; 513 }; 514 515 gic: interrupt-controller@ffb71000 { 516 compatible = "arm,gic-400"; 517 interrupt-controller; 518 #interrupt-cells = <3>; 519 #address-cells = <0>; 520 521 reg = <0x0 0xffb71000 0x0 0x1000>, 522 <0x0 0xffb72000 0x0 0x2000>, 523 <0x0 0xffb74000 0x0 0x2000>, 524 <0x0 0xffb76000 0x0 0x2000>; 525 interrupts = <GIC_PPI 9 526 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 527 }; 528 529 pinctrl: pinctrl { 530 compatible = "rockchip,rk3368-pinctrl"; 531 rockchip,grf = <&grf>; 532 rockchip,pmu = <&pmugrf>; 533 #address-cells = <0x2>; 534 #size-cells = <0x2>; 535 ranges; 536 537 gpio0: gpio0@ff750000 { 538 compatible = "rockchip,gpio-bank"; 539 reg = <0x0 0xff750000 0x0 0x100>; 540 clocks = <&cru PCLK_GPIO0>; 541 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 542 543 gpio-controller; 544 #gpio-cells = <0x2>; 545 546 interrupt-controller; 547 #interrupt-cells = <0x2>; 548 }; 549 550 gpio1: gpio1@ff780000 { 551 compatible = "rockchip,gpio-bank"; 552 reg = <0x0 0xff780000 0x0 0x100>; 553 clocks = <&cru PCLK_GPIO1>; 554 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 555 556 gpio-controller; 557 #gpio-cells = <0x2>; 558 559 interrupt-controller; 560 #interrupt-cells = <0x2>; 561 }; 562 563 gpio2: gpio2@ff790000 { 564 compatible = "rockchip,gpio-bank"; 565 reg = <0x0 0xff790000 0x0 0x100>; 566 clocks = <&cru PCLK_GPIO2>; 567 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 568 569 gpio-controller; 570 #gpio-cells = <0x2>; 571 572 interrupt-controller; 573 #interrupt-cells = <0x2>; 574 }; 575 576 gpio3: gpio3@ff7a0000 { 577 compatible = "rockchip,gpio-bank"; 578 reg = <0x0 0xff7a0000 0x0 0x100>; 579 clocks = <&cru PCLK_GPIO3>; 580 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 581 582 gpio-controller; 583 #gpio-cells = <0x2>; 584 585 interrupt-controller; 586 #interrupt-cells = <0x2>; 587 }; 588 589 pcfg_pull_up: pcfg-pull-up { 590 bias-pull-up; 591 }; 592 593 pcfg_pull_down: pcfg-pull-down { 594 bias-pull-down; 595 }; 596 597 pcfg_pull_none: pcfg-pull-none { 598 bias-disable; 599 }; 600 601 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 602 bias-disable; 603 drive-strength = <12>; 604 }; 605 606 emmc { 607 emmc_clk: emmc-clk { 608 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 609 }; 610 611 emmc_cmd: emmc-cmd { 612 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; 613 }; 614 615 emmc_pwr: emmc-pwr { 616 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; 617 }; 618 619 emmc_bus1: emmc-bus1 { 620 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; 621 }; 622 623 emmc_bus4: emmc-bus4 { 624 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 625 <1 19 RK_FUNC_2 &pcfg_pull_up>, 626 <1 20 RK_FUNC_2 &pcfg_pull_up>, 627 <1 21 RK_FUNC_2 &pcfg_pull_up>; 628 }; 629 630 emmc_bus8: emmc-bus8 { 631 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 632 <1 19 RK_FUNC_2 &pcfg_pull_up>, 633 <1 20 RK_FUNC_2 &pcfg_pull_up>, 634 <1 21 RK_FUNC_2 &pcfg_pull_up>, 635 <1 22 RK_FUNC_2 &pcfg_pull_up>, 636 <1 23 RK_FUNC_2 &pcfg_pull_up>, 637 <1 24 RK_FUNC_2 &pcfg_pull_up>, 638 <1 25 RK_FUNC_2 &pcfg_pull_up>; 639 }; 640 }; 641 642 gmac { 643 rgmii_pins: rgmii-pins { 644 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 645 <3 24 RK_FUNC_1 &pcfg_pull_none>, 646 <3 19 RK_FUNC_1 &pcfg_pull_none>, 647 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 648 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 649 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, 650 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, 651 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, 652 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 653 <3 15 RK_FUNC_1 &pcfg_pull_none>, 654 <3 16 RK_FUNC_1 &pcfg_pull_none>, 655 <3 17 RK_FUNC_1 &pcfg_pull_none>, 656 <3 18 RK_FUNC_1 &pcfg_pull_none>, 657 <3 25 RK_FUNC_1 &pcfg_pull_none>, 658 <3 20 RK_FUNC_1 &pcfg_pull_none>; 659 }; 660 661 rmii_pins: rmii-pins { 662 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 663 <3 24 RK_FUNC_1 &pcfg_pull_none>, 664 <3 19 RK_FUNC_1 &pcfg_pull_none>, 665 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 666 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 667 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 668 <3 15 RK_FUNC_1 &pcfg_pull_none>, 669 <3 16 RK_FUNC_1 &pcfg_pull_none>, 670 <3 20 RK_FUNC_1 &pcfg_pull_none>, 671 <3 21 RK_FUNC_1 &pcfg_pull_none>; 672 }; 673 }; 674 675 i2c0 { 676 i2c0_xfer: i2c0-xfer { 677 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 678 <0 7 RK_FUNC_1 &pcfg_pull_none>; 679 }; 680 }; 681 682 i2c1 { 683 i2c1_xfer: i2c1-xfer { 684 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, 685 <2 22 RK_FUNC_1 &pcfg_pull_none>; 686 }; 687 }; 688 689 i2c2 { 690 i2c2_xfer: i2c2-xfer { 691 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, 692 <3 31 RK_FUNC_2 &pcfg_pull_none>; 693 }; 694 }; 695 696 i2c3 { 697 i2c3_xfer: i2c3-xfer { 698 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, 699 <1 17 RK_FUNC_1 &pcfg_pull_none>; 700 }; 701 }; 702 703 i2c4 { 704 i2c4_xfer: i2c4-xfer { 705 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, 706 <3 25 RK_FUNC_2 &pcfg_pull_none>; 707 }; 708 }; 709 710 i2c5 { 711 i2c5_xfer: i2c5-xfer { 712 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, 713 <3 27 RK_FUNC_2 &pcfg_pull_none>; 714 }; 715 }; 716 717 sdio0 { 718 sdio0_bus1: sdio0-bus1 { 719 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; 720 }; 721 722 sdio0_bus4: sdio0-bus4 { 723 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, 724 <2 29 RK_FUNC_1 &pcfg_pull_up>, 725 <2 30 RK_FUNC_1 &pcfg_pull_up>, 726 <2 31 RK_FUNC_1 &pcfg_pull_up>; 727 }; 728 729 sdio0_cmd: sdio0-cmd { 730 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; 731 }; 732 733 sdio0_clk: sdio0-clk { 734 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; 735 }; 736 737 sdio0_cd: sdio0-cd { 738 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; 739 }; 740 741 sdio0_wp: sdio0-wp { 742 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; 743 }; 744 745 sdio0_pwr: sdio0-pwr { 746 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; 747 }; 748 749 sdio0_bkpwr: sdio0-bkpwr { 750 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; 751 }; 752 753 sdio0_int: sdio0-int { 754 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; 755 }; 756 }; 757 758 sdmmc { 759 sdmmc_clk: sdmmc-clk { 760 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; 761 }; 762 763 sdmmc_cmd: sdmmc-cmd { 764 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; 765 }; 766 767 sdmmc_cd: sdmcc-cd { 768 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; 769 }; 770 771 sdmmc_bus1: sdmmc-bus1 { 772 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; 773 }; 774 775 sdmmc_bus4: sdmmc-bus4 { 776 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, 777 <2 6 RK_FUNC_1 &pcfg_pull_up>, 778 <2 7 RK_FUNC_1 &pcfg_pull_up>, 779 <2 8 RK_FUNC_1 &pcfg_pull_up>; 780 }; 781 }; 782 783 spi0 { 784 spi0_clk: spi0-clk { 785 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; 786 }; 787 spi0_cs0: spi0-cs0 { 788 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; 789 }; 790 spi0_cs1: spi0-cs1 { 791 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; 792 }; 793 spi0_tx: spi0-tx { 794 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; 795 }; 796 spi0_rx: spi0-rx { 797 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; 798 }; 799 }; 800 801 spi1 { 802 spi1_clk: spi1-clk { 803 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; 804 }; 805 spi1_cs0: spi1-cs0 { 806 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; 807 }; 808 spi1_cs1: spi1-cs1 { 809 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; 810 }; 811 spi1_rx: spi1-rx { 812 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; 813 }; 814 spi1_tx: spi1-tx { 815 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; 816 }; 817 }; 818 819 spi2 { 820 spi2_clk: spi2-clk { 821 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; 822 }; 823 spi2_cs0: spi2-cs0 { 824 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 825 }; 826 spi2_rx: spi2-rx { 827 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; 828 }; 829 spi2_tx: spi2-tx { 830 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 831 }; 832 }; 833 834 uart0 { 835 uart0_xfer: uart0-xfer { 836 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, 837 <2 25 RK_FUNC_1 &pcfg_pull_none>; 838 }; 839 840 uart0_cts: uart0-cts { 841 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; 842 }; 843 844 uart0_rts: uart0-rts { 845 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; 846 }; 847 }; 848 849 uart1 { 850 uart1_xfer: uart1-xfer { 851 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, 852 <0 21 RK_FUNC_3 &pcfg_pull_none>; 853 }; 854 855 uart1_cts: uart1-cts { 856 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; 857 }; 858 859 uart1_rts: uart1-rts { 860 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; 861 }; 862 }; 863 864 uart2 { 865 uart2_xfer: uart2-xfer { 866 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, 867 <2 5 RK_FUNC_2 &pcfg_pull_none>; 868 }; 869 /* no rts / cts for uart2 */ 870 }; 871 872 uart3 { 873 uart3_xfer: uart3-xfer { 874 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, 875 <3 30 RK_FUNC_3 &pcfg_pull_none>; 876 }; 877 878 uart3_cts: uart3-cts { 879 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; 880 }; 881 882 uart3_rts: uart3-rts { 883 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; 884 }; 885 }; 886 887 uart4 { 888 uart4_xfer: uart4-xfer { 889 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, 890 <0 26 RK_FUNC_3 &pcfg_pull_none>; 891 }; 892 893 uart4_cts: uart4-cts { 894 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; 895 }; 896 897 uart4_rts: uart4-rts { 898 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; 899 }; 900 }; 901 }; 902}; 903