1 /* 2 * BF533 memory map 3 * 4 * Copyright 2004-2009 Analog Devices Inc. 5 * Licensed under the GPL-2 or later. 6 */ 7 8 #ifndef __BFIN_MACH_MEM_MAP_H__ 9 #define __BFIN_MACH_MEM_MAP_H__ 10 11 #ifndef __BFIN_MEM_MAP_H__ 12 # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" 13 #endif 14 15 /* Async Memory Banks */ 16 #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ 17 #define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ 18 #define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ 19 #define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ 20 #define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ 21 #define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ 22 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ 23 #define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ 24 25 /* Boot ROM Memory */ 26 27 #define BOOT_ROM_START 0xEF000000 28 #define BOOT_ROM_LENGTH 0x400 29 30 /* Level 1 Memory */ 31 32 #ifdef CONFIG_BFIN_ICACHE 33 #define BFIN_ICACHESIZE (16*1024) 34 #else 35 #define BFIN_ICACHESIZE (0*1024) 36 #endif 37 38 /* Memory Map for ADSP-BF533 processors */ 39 40 #ifdef CONFIG_BF533 41 #define L1_CODE_START 0xFFA00000 42 #define L1_DATA_A_START 0xFF800000 43 #define L1_DATA_B_START 0xFF900000 44 45 #ifdef CONFIG_BFIN_ICACHE 46 #define L1_CODE_LENGTH (0x14000 - 0x4000) 47 #else 48 #define L1_CODE_LENGTH 0x14000 49 #endif 50 51 #ifdef CONFIG_BFIN_DCACHE 52 53 #ifdef CONFIG_BFIN_DCACHE_BANKA 54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 55 #define L1_DATA_A_LENGTH (0x8000 - 0x4000) 56 #define L1_DATA_B_LENGTH 0x8000 57 #define BFIN_DCACHESIZE (16*1024) 58 #define BFIN_DSUPBANKS 1 59 #else 60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 61 #define L1_DATA_A_LENGTH (0x8000 - 0x4000) 62 #define L1_DATA_B_LENGTH (0x8000 - 0x4000) 63 #define BFIN_DCACHESIZE (32*1024) 64 #define BFIN_DSUPBANKS 2 65 #endif 66 67 #else 68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 69 #define L1_DATA_A_LENGTH 0x8000 70 #define L1_DATA_B_LENGTH 0x8000 71 #define BFIN_DCACHESIZE (0*1024) 72 #define BFIN_DSUPBANKS 0 73 #endif /*CONFIG_BFIN_DCACHE*/ 74 #endif 75 76 /* Memory Map for ADSP-BF532 processors */ 77 78 #ifdef CONFIG_BF532 79 #define L1_CODE_START 0xFFA08000 80 #define L1_DATA_A_START 0xFF804000 81 #define L1_DATA_B_START 0xFF904000 82 83 #ifdef CONFIG_BFIN_ICACHE 84 #define L1_CODE_LENGTH (0xC000 - 0x4000) 85 #else 86 #define L1_CODE_LENGTH 0xC000 87 #endif 88 89 #ifdef CONFIG_BFIN_DCACHE 90 91 #ifdef CONFIG_BFIN_DCACHE_BANKA 92 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 93 #define L1_DATA_A_LENGTH (0x4000 - 0x4000) 94 #define L1_DATA_B_LENGTH 0x4000 95 #define BFIN_DCACHESIZE (16*1024) 96 #define BFIN_DSUPBANKS 1 97 98 #else 99 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 100 #define L1_DATA_A_LENGTH (0x4000 - 0x4000) 101 #define L1_DATA_B_LENGTH (0x4000 - 0x4000) 102 #define BFIN_DCACHESIZE (32*1024) 103 #define BFIN_DSUPBANKS 2 104 #endif 105 106 #else 107 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 108 #define L1_DATA_A_LENGTH 0x4000 109 #define L1_DATA_B_LENGTH 0x4000 110 #define BFIN_DCACHESIZE (0*1024) 111 #define BFIN_DSUPBANKS 0 112 #endif /*CONFIG_BFIN_DCACHE*/ 113 #endif 114 115 /* Memory Map for ADSP-BF531 processors */ 116 117 #ifdef CONFIG_BF531 118 #define L1_CODE_START 0xFFA08000 119 #define L1_DATA_A_START 0xFF804000 120 #define L1_DATA_B_START 0xFF904000 121 #define L1_CODE_LENGTH 0x4000 122 #define L1_DATA_B_LENGTH 0x0000 123 124 125 #ifdef CONFIG_BFIN_DCACHE 126 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 127 #define L1_DATA_A_LENGTH (0x4000 - 0x4000) 128 #define BFIN_DCACHESIZE (16*1024) 129 #define BFIN_DSUPBANKS 1 130 #else 131 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 132 #define L1_DATA_A_LENGTH 0x4000 133 #define BFIN_DCACHESIZE (0*1024) 134 #define BFIN_DSUPBANKS 0 135 #endif 136 137 #endif 138 139 #endif 140