1 /* 2 * BF60x memory map 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * Licensed under the GPL-2 or later. 6 */ 7 8 #ifndef __BFIN_MACH_MEM_MAP_H__ 9 #define __BFIN_MACH_MEM_MAP_H__ 10 11 #ifndef __BFIN_MEM_MAP_H__ 12 # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" 13 #endif 14 15 /* Async Memory Banks */ 16 #define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */ 17 #define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ 18 #define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */ 19 #define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ 20 #define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */ 21 #define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ 22 #define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */ 23 #define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ 24 25 /* Boot ROM Memory */ 26 27 #define BOOT_ROM_START 0xC8000000 28 #define BOOT_ROM_LENGTH 0x8000 29 30 /* Level 1 Memory */ 31 32 /* Memory Map for ADSP-BF60x processors */ 33 #ifdef CONFIG_BFIN_ICACHE 34 #define BFIN_ICACHESIZE (16*1024) 35 #define L1_CODE_LENGTH 0x10000 36 #else 37 #define BFIN_ICACHESIZE (0*1024) 38 #define L1_CODE_LENGTH 0x14000 39 #endif 40 41 #define L1_CODE_START 0xFFA00000 42 #define L1_DATA_A_START 0xFF800000 43 #define L1_DATA_B_START 0xFF900000 44 45 46 #define COREA_L1_SCRATCH_START 0xFFB00000 47 #define COREB_L1_SCRATCH_START 0xFF700000 48 49 #define COREB_L1_CODE_START 0xFF600000 50 #define COREB_L1_DATA_A_START 0xFF400000 51 #define COREB_L1_DATA_B_START 0xFF500000 52 53 #define COREB_L1_CODE_LENGTH 0x14000 54 #define COREB_L1_DATA_A_LENGTH 0x8000 55 #define COREB_L1_DATA_B_LENGTH 0x8000 56 57 58 #ifdef CONFIG_BFIN_DCACHE 59 60 #ifdef CONFIG_BFIN_DCACHE_BANKA 61 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 62 #define L1_DATA_A_LENGTH (0x8000 - 0x4000) 63 #define L1_DATA_B_LENGTH 0x8000 64 #define BFIN_DCACHESIZE (16*1024) 65 #define BFIN_DSUPBANKS 1 66 #else 67 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 68 #define L1_DATA_A_LENGTH (0x8000 - 0x4000) 69 #define L1_DATA_B_LENGTH (0x8000 - 0x4000) 70 #define BFIN_DCACHESIZE (32*1024) 71 #define BFIN_DSUPBANKS 2 72 #endif 73 74 #else 75 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 76 #define L1_DATA_A_LENGTH 0x8000 77 #define L1_DATA_B_LENGTH 0x8000 78 #define BFIN_DCACHESIZE (0*1024) 79 #define BFIN_DSUPBANKS 0 80 #endif /*CONFIG_BFIN_DCACHE*/ 81 82 /* Level 2 Memory */ 83 #define L2_START 0xC8080000 84 #define L2_LENGTH 0x40000 85 86 #endif 87