1 /*
2 * arch/cris/arch-v32/kernel/kgdb.c
3 *
4 * CRIS v32 version by Orjan Friberg, Axis Communications AB.
5 *
6 * S390 version
7 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
8 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 *
10 * Originally written by Glenn Engel, Lake Stevens Instrument Division
11 *
12 * Contributed by HP Systems
13 *
14 * Modified for SPARC by Stu Grossman, Cygnus Support.
15 *
16 * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
17 * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
18 *
19 * Copyright (C) 1995 Andreas Busse
20 */
21
22 /* FIXME: Check the documentation. */
23
24 /*
25 * kgdb usage notes:
26 * -----------------
27 *
28 * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be
29 * built with different gcc flags: "-g" is added to get debug infos, and
30 * "-fomit-frame-pointer" is omitted to make debugging easier. Since the
31 * resulting kernel will be quite big (approx. > 7 MB), it will be stripped
32 * before compresion. Such a kernel will behave just as usually, except if
33 * given a "debug=<device>" command line option. (Only serial devices are
34 * allowed for <device>, i.e. no printers or the like; possible values are
35 * machine depedend and are the same as for the usual debug device, the one
36 * for logging kernel messages.) If that option is given and the device can be
37 * initialized, the kernel will connect to the remote gdb in trap_init(). The
38 * serial parameters are fixed to 8N1 and 115200 bps, for easyness of
39 * implementation.
40 *
41 * To start a debugging session, start that gdb with the debugging kernel
42 * image (the one with the symbols, vmlinux.debug) named on the command line.
43 * This file will be used by gdb to get symbol and debugging infos about the
44 * kernel. Next, select remote debug mode by
45 * target remote <device>
46 * where <device> is the name of the serial device over which the debugged
47 * machine is connected. Maybe you have to adjust the baud rate by
48 * set remotebaud <rate>
49 * or also other parameters with stty:
50 * shell stty ... </dev/...
51 * If the kernel to debug has already booted, it waited for gdb and now
52 * connects, and you'll see a breakpoint being reported. If the kernel isn't
53 * running yet, start it now. The order of gdb and the kernel doesn't matter.
54 * Another thing worth knowing about in the getting-started phase is how to
55 * debug the remote protocol itself. This is activated with
56 * set remotedebug 1
57 * gdb will then print out each packet sent or received. You'll also get some
58 * messages about the gdb stub on the console of the debugged machine.
59 *
60 * If all that works, you can use lots of the usual debugging techniques on
61 * the kernel, e.g. inspecting and changing variables/memory, setting
62 * breakpoints, single stepping and so on. It's also possible to interrupt the
63 * debugged kernel by pressing C-c in gdb. Have fun! :-)
64 *
65 * The gdb stub is entered (and thus the remote gdb gets control) in the
66 * following situations:
67 *
68 * - If breakpoint() is called. This is just after kgdb initialization, or if
69 * a breakpoint() call has been put somewhere into the kernel source.
70 * (Breakpoints can of course also be set the usual way in gdb.)
71 * In eLinux, we call breakpoint() in init/main.c after IRQ initialization.
72 *
73 * - If there is a kernel exception, i.e. bad_super_trap() or die_if_kernel()
74 * are entered. All the CPU exceptions are mapped to (more or less..., see
75 * the hard_trap_info array below) appropriate signal, which are reported
76 * to gdb. die_if_kernel() is usually called after some kind of access
77 * error and thus is reported as SIGSEGV.
78 *
79 * - When panic() is called. This is reported as SIGABRT.
80 *
81 * - If C-c is received over the serial line, which is treated as
82 * SIGINT.
83 *
84 * Of course, all these signals are just faked for gdb, since there is no
85 * signal concept as such for the kernel. It also isn't possible --obviously--
86 * to set signal handlers from inside gdb, or restart the kernel with a
87 * signal.
88 *
89 * Current limitations:
90 *
91 * - While the kernel is stopped, interrupts are disabled for safety reasons
92 * (i.e., variables not changing magically or the like). But this also
93 * means that the clock isn't running anymore, and that interrupts from the
94 * hardware may get lost/not be served in time. This can cause some device
95 * errors...
96 *
97 * - When single-stepping, only one instruction of the current thread is
98 * executed, but interrupts are allowed for that time and will be serviced
99 * if pending. Be prepared for that.
100 *
101 * - All debugging happens in kernel virtual address space. There's no way to
102 * access physical memory not mapped in kernel space, or to access user
103 * space. A way to work around this is using get_user_long & Co. in gdb
104 * expressions, but only for the current process.
105 *
106 * - Interrupting the kernel only works if interrupts are currently allowed,
107 * and the interrupt of the serial line isn't blocked by some other means
108 * (IPL too high, disabled, ...)
109 *
110 * - The gdb stub is currently not reentrant, i.e. errors that happen therein
111 * (e.g. accessing invalid memory) may not be caught correctly. This could
112 * be removed in future by introducing a stack of struct registers.
113 *
114 */
115
116 /*
117 * To enable debugger support, two things need to happen. One, a
118 * call to kgdb_init() is necessary in order to allow any breakpoints
119 * or error conditions to be properly intercepted and reported to gdb.
120 * Two, a breakpoint needs to be generated to begin communication. This
121 * is most easily accomplished by a call to breakpoint().
122 *
123 * The following gdb commands are supported:
124 *
125 * command function Return value
126 *
127 * g return the value of the CPU registers hex data or ENN
128 * G set the value of the CPU registers OK or ENN
129 *
130 * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
131 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
132 *
133 * c Resume at current address SNN ( signal NN)
134 * cAA..AA Continue at address AA..AA SNN
135 *
136 * s Step one instruction SNN
137 * sAA..AA Step one instruction from AA..AA SNN
138 *
139 * k kill
140 *
141 * ? What was the last sigval ? SNN (signal NN)
142 *
143 * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
144 * baud rate
145 *
146 * All commands and responses are sent with a packet which includes a
147 * checksum. A packet consists of
148 *
149 * $<packet info>#<checksum>.
150 *
151 * where
152 * <packet info> :: <characters representing the command or response>
153 * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
154 *
155 * When a packet is received, it is first acknowledged with either '+' or '-'.
156 * '+' indicates a successful transfer. '-' indicates a failed transfer.
157 *
158 * Example:
159 *
160 * Host: Reply:
161 * $m0,10#2a +$00010203040506070809101112131415#42
162 *
163 */
164
165
166 #include <linux/string.h>
167 #include <linux/signal.h>
168 #include <linux/kernel.h>
169 #include <linux/delay.h>
170 #include <linux/linkage.h>
171 #include <linux/reboot.h>
172
173 #include <asm/setup.h>
174 #include <asm/ptrace.h>
175
176 #include <asm/irq.h>
177 #include <hwregs/reg_map.h>
178 #include <hwregs/reg_rdwr.h>
179 #include <hwregs/intr_vect_defs.h>
180 #include <hwregs/ser_defs.h>
181
182 /* From entry.S. */
183 extern void gdb_handle_exception(void);
184 /* From kgdb_asm.S. */
185 extern void kgdb_handle_exception(void);
186
187 static int kgdb_started = 0;
188
189 /********************************* Register image ****************************/
190
191 typedef
192 struct register_image
193 {
194 /* Offset */
195 unsigned int r0; /* 0x00 */
196 unsigned int r1; /* 0x04 */
197 unsigned int r2; /* 0x08 */
198 unsigned int r3; /* 0x0C */
199 unsigned int r4; /* 0x10 */
200 unsigned int r5; /* 0x14 */
201 unsigned int r6; /* 0x18 */
202 unsigned int r7; /* 0x1C */
203 unsigned int r8; /* 0x20; Frame pointer (if any) */
204 unsigned int r9; /* 0x24 */
205 unsigned int r10; /* 0x28 */
206 unsigned int r11; /* 0x2C */
207 unsigned int r12; /* 0x30 */
208 unsigned int r13; /* 0x34 */
209 unsigned int sp; /* 0x38; R14, Stack pointer */
210 unsigned int acr; /* 0x3C; R15, Address calculation register. */
211
212 unsigned char bz; /* 0x40; P0, 8-bit zero register */
213 unsigned char vr; /* 0x41; P1, Version register (8-bit) */
214 unsigned int pid; /* 0x42; P2, Process ID */
215 unsigned char srs; /* 0x46; P3, Support register select (8-bit) */
216 unsigned short wz; /* 0x47; P4, 16-bit zero register */
217 unsigned int exs; /* 0x49; P5, Exception status */
218 unsigned int eda; /* 0x4D; P6, Exception data address */
219 unsigned int mof; /* 0x51; P7, Multiply overflow register */
220 unsigned int dz; /* 0x55; P8, 32-bit zero register */
221 unsigned int ebp; /* 0x59; P9, Exception base pointer */
222 unsigned int erp; /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */
223 unsigned int srp; /* 0x61; P11, Subroutine return pointer */
224 unsigned int nrp; /* 0x65; P12, NMI return pointer */
225 unsigned int ccs; /* 0x69; P13, Condition code stack */
226 unsigned int usp; /* 0x6D; P14, User mode stack pointer */
227 unsigned int spc; /* 0x71; P15, Single step PC */
228 unsigned int pc; /* 0x75; Pseudo register (for the most part set to ERP). */
229
230 } registers;
231
232 typedef
233 struct bp_register_image
234 {
235 /* Support register bank 0. */
236 unsigned int s0_0;
237 unsigned int s1_0;
238 unsigned int s2_0;
239 unsigned int s3_0;
240 unsigned int s4_0;
241 unsigned int s5_0;
242 unsigned int s6_0;
243 unsigned int s7_0;
244 unsigned int s8_0;
245 unsigned int s9_0;
246 unsigned int s10_0;
247 unsigned int s11_0;
248 unsigned int s12_0;
249 unsigned int s13_0;
250 unsigned int s14_0;
251 unsigned int s15_0;
252
253 /* Support register bank 1. */
254 unsigned int s0_1;
255 unsigned int s1_1;
256 unsigned int s2_1;
257 unsigned int s3_1;
258 unsigned int s4_1;
259 unsigned int s5_1;
260 unsigned int s6_1;
261 unsigned int s7_1;
262 unsigned int s8_1;
263 unsigned int s9_1;
264 unsigned int s10_1;
265 unsigned int s11_1;
266 unsigned int s12_1;
267 unsigned int s13_1;
268 unsigned int s14_1;
269 unsigned int s15_1;
270
271 /* Support register bank 2. */
272 unsigned int s0_2;
273 unsigned int s1_2;
274 unsigned int s2_2;
275 unsigned int s3_2;
276 unsigned int s4_2;
277 unsigned int s5_2;
278 unsigned int s6_2;
279 unsigned int s7_2;
280 unsigned int s8_2;
281 unsigned int s9_2;
282 unsigned int s10_2;
283 unsigned int s11_2;
284 unsigned int s12_2;
285 unsigned int s13_2;
286 unsigned int s14_2;
287 unsigned int s15_2;
288
289 /* Support register bank 3. */
290 unsigned int s0_3; /* BP_CTRL */
291 unsigned int s1_3; /* BP_I0_START */
292 unsigned int s2_3; /* BP_I0_END */
293 unsigned int s3_3; /* BP_D0_START */
294 unsigned int s4_3; /* BP_D0_END */
295 unsigned int s5_3; /* BP_D1_START */
296 unsigned int s6_3; /* BP_D1_END */
297 unsigned int s7_3; /* BP_D2_START */
298 unsigned int s8_3; /* BP_D2_END */
299 unsigned int s9_3; /* BP_D3_START */
300 unsigned int s10_3; /* BP_D3_END */
301 unsigned int s11_3; /* BP_D4_START */
302 unsigned int s12_3; /* BP_D4_END */
303 unsigned int s13_3; /* BP_D5_START */
304 unsigned int s14_3; /* BP_D5_END */
305 unsigned int s15_3; /* BP_RESERVED */
306
307 } support_registers;
308
309 enum register_name
310 {
311 R0, R1, R2, R3,
312 R4, R5, R6, R7,
313 R8, R9, R10, R11,
314 R12, R13, SP, ACR,
315
316 BZ, VR, PID, SRS,
317 WZ, EXS, EDA, MOF,
318 DZ, EBP, ERP, SRP,
319 NRP, CCS, USP, SPC,
320 PC,
321
322 S0, S1, S2, S3,
323 S4, S5, S6, S7,
324 S8, S9, S10, S11,
325 S12, S13, S14, S15
326
327 };
328
329 /* The register sizes of the registers in register_name. An unimplemented register
330 is designated by size 0 in this array. */
331 static int register_size[] =
332 {
333 4, 4, 4, 4,
334 4, 4, 4, 4,
335 4, 4, 4, 4,
336 4, 4, 4, 4,
337
338 1, 1, 4, 1,
339 2, 4, 4, 4,
340 4, 4, 4, 4,
341 4, 4, 4, 4,
342
343 4,
344
345 4, 4, 4, 4,
346 4, 4, 4, 4,
347 4, 4, 4, 4,
348 4, 4, 4
349
350 };
351
352 /* Contains the register image of the kernel.
353 (Global so that they can be reached from assembler code.) */
354 registers reg;
355 support_registers sreg;
356
357 /************** Prototypes for local library functions ***********************/
358
359 /* Copy of strcpy from libc. */
360 static char *gdb_cris_strcpy(char *s1, const char *s2);
361
362 /* Copy of strlen from libc. */
363 static int gdb_cris_strlen(const char *s);
364
365 /* Copy of memchr from libc. */
366 static void *gdb_cris_memchr(const void *s, int c, int n);
367
368 /* Copy of strtol from libc. Does only support base 16. */
369 static int gdb_cris_strtol(const char *s, char **endptr, int base);
370
371 /********************** Prototypes for local functions. **********************/
372
373 /* Write a value to a specified register regno in the register image
374 of the current thread. */
375 static int write_register(int regno, char *val);
376
377 /* Read a value from a specified register in the register image. Returns the
378 status of the read operation. The register value is returned in valptr. */
379 static int read_register(char regno, unsigned int *valptr);
380
381 /* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
382 int getDebugChar(void);
383
384 /* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
385 void putDebugChar(int val);
386
387 /* Convert the memory, pointed to by mem into hexadecimal representation.
388 Put the result in buf, and return a pointer to the last character
389 in buf (null). */
390 static char *mem2hex(char *buf, unsigned char *mem, int count);
391
392 /* Put the content of the array, in binary representation, pointed to by buf
393 into memory pointed to by mem, and return a pointer to
394 the character after the last byte written. */
395 static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count);
396
397 /* Await the sequence $<data>#<checksum> and store <data> in the array buffer
398 returned. */
399 static void getpacket(char *buffer);
400
401 /* Send $<data>#<checksum> from the <data> in the array buffer. */
402 static void putpacket(char *buffer);
403
404 /* Build and send a response packet in order to inform the host the
405 stub is stopped. */
406 static void stub_is_stopped(int sigval);
407
408 /* All expected commands are sent from remote.c. Send a response according
409 to the description in remote.c. Not static since it needs to be reached
410 from assembler code. */
411 void handle_exception(int sigval);
412
413 /* Performs a complete re-start from scratch. ETRAX specific. */
414 static void kill_restart(void);
415
416 /******************** Prototypes for global functions. ***********************/
417
418 /* The string str is prepended with the GDB printout token and sent. */
419 void putDebugString(const unsigned char *str, int len);
420
421 /* A static breakpoint to be used at startup. */
422 void breakpoint(void);
423
424 /* Avoid warning as the internal_stack is not used in the C-code. */
425 #define USEDVAR(name) { if (name) { ; } }
426 #define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) }
427
428 /********************************** Packet I/O ******************************/
429 /* BUFMAX defines the maximum number of characters in
430 inbound/outbound buffers */
431 /* FIXME: How do we know it's enough? */
432 #define BUFMAX 512
433
434 /* Run-length encoding maximum length. Send 64 at most. */
435 #define RUNLENMAX 64
436
437 /* The inbound/outbound buffers used in packet I/O */
438 static char input_buffer[BUFMAX];
439 static char output_buffer[BUFMAX];
440
441 /* Error and warning messages. */
442 enum error_type
443 {
444 SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
445 };
446
447 static char *error_message[] =
448 {
449 "",
450 "E01 Set current or general thread - H[c,g] - internal error.",
451 "E02 Change register content - P - cannot change read-only register.",
452 "E03 Thread is not alive.", /* T, not used. */
453 "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
454 "E05 Change register content - P - the register is not implemented..",
455 "E06 Change memory content - M - internal error.",
456 "E07 Change register content - P - the register is not stored on the stack",
457 "E08 Invalid parameter"
458 };
459
460 /********************************** Breakpoint *******************************/
461 /* Use an internal stack in the breakpoint and interrupt response routines.
462 FIXME: How do we know the size of this stack is enough?
463 Global so it can be reached from assembler code. */
464 #define INTERNAL_STACK_SIZE 1024
465 char internal_stack[INTERNAL_STACK_SIZE];
466
467 /* Due to the breakpoint return pointer, a state variable is needed to keep
468 track of whether it is a static (compiled) or dynamic (gdb-invoked)
469 breakpoint to be handled. A static breakpoint uses the content of register
470 ERP as it is whereas a dynamic breakpoint requires subtraction with 2
471 in order to execute the instruction. The first breakpoint is static; all
472 following are assumed to be dynamic. */
473 static int dynamic_bp = 0;
474
475 /********************************* String library ****************************/
476 /* Single-step over library functions creates trap loops. */
477
478 /* Copy char s2[] to s1[]. */
479 static char*
gdb_cris_strcpy(char * s1,const char * s2)480 gdb_cris_strcpy(char *s1, const char *s2)
481 {
482 char *s = s1;
483
484 for (s = s1; (*s++ = *s2++) != '\0'; )
485 ;
486 return s1;
487 }
488
489 /* Find length of s[]. */
490 static int
gdb_cris_strlen(const char * s)491 gdb_cris_strlen(const char *s)
492 {
493 const char *sc;
494
495 for (sc = s; *sc != '\0'; sc++)
496 ;
497 return (sc - s);
498 }
499
500 /* Find first occurrence of c in s[n]. */
501 static void*
gdb_cris_memchr(const void * s,int c,int n)502 gdb_cris_memchr(const void *s, int c, int n)
503 {
504 const unsigned char uc = c;
505 const unsigned char *su;
506
507 for (su = s; 0 < n; ++su, --n)
508 if (*su == uc)
509 return (void *)su;
510 return NULL;
511 }
512 /******************************* Standard library ****************************/
513 /* Single-step over library functions creates trap loops. */
514 /* Convert string to long. */
515 static int
gdb_cris_strtol(const char * s,char ** endptr,int base)516 gdb_cris_strtol(const char *s, char **endptr, int base)
517 {
518 char *s1;
519 char *sd;
520 int x = 0;
521
522 for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1)
523 x = x * base + (sd - hex_asc);
524
525 if (endptr) {
526 /* Unconverted suffix is stored in endptr unless endptr is NULL. */
527 *endptr = s1;
528 }
529
530 return x;
531 }
532
533 /********************************* Register image ****************************/
534
535 /* Write a value to a specified register in the register image of the current
536 thread. Returns status code SUCCESS, E02, E05 or E08. */
537 static int
write_register(int regno,char * val)538 write_register(int regno, char *val)
539 {
540 int status = SUCCESS;
541
542 if (regno >= R0 && regno <= ACR) {
543 /* Consecutive 32-bit registers. */
544 if (hex2bin((unsigned char *)®.r0 + (regno - R0) * sizeof(unsigned int),
545 val, sizeof(unsigned int)))
546 status = E08;
547
548 } else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
549 /* Read-only registers. */
550 status = E02;
551
552 } else if (regno == PID) {
553 /* 32-bit register. (Even though we already checked SRS and WZ, we cannot
554 combine this with the EXS - SPC write since SRS and WZ have different size.) */
555 if (hex2bin((unsigned char *)®.pid, val, sizeof(unsigned int)))
556 status = E08;
557
558 } else if (regno == SRS) {
559 /* 8-bit register. */
560 if (hex2bin((unsigned char *)®.srs, val, sizeof(unsigned char)))
561 status = E08;
562
563 } else if (regno >= EXS && regno <= SPC) {
564 /* Consecutive 32-bit registers. */
565 if (hex2bin((unsigned char *)®.exs + (regno - EXS) * sizeof(unsigned int),
566 val, sizeof(unsigned int)))
567 status = E08;
568
569 } else if (regno == PC) {
570 /* Pseudo-register. Treat as read-only. */
571 status = E02;
572
573 } else if (regno >= S0 && regno <= S15) {
574 /* 32-bit registers. */
575 if (hex2bin((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int),
576 val, sizeof(unsigned int)))
577 status = E08;
578 } else {
579 /* Non-existing register. */
580 status = E05;
581 }
582 return status;
583 }
584
585 /* Read a value from a specified register in the register image. Returns the
586 value in the register or -1 for non-implemented registers. */
587 static int
read_register(char regno,unsigned int * valptr)588 read_register(char regno, unsigned int *valptr)
589 {
590 int status = SUCCESS;
591
592 /* We read the zero registers from the register struct (instead of just returning 0)
593 to catch errors. */
594
595 if (regno >= R0 && regno <= ACR) {
596 /* Consecutive 32-bit registers. */
597 *valptr = *(unsigned int *)((char *)®.r0 + (regno - R0) * sizeof(unsigned int));
598
599 } else if (regno == BZ || regno == VR) {
600 /* Consecutive 8-bit registers. */
601 *valptr = (unsigned int)(*(unsigned char *)
602 ((char *)®.bz + (regno - BZ) * sizeof(char)));
603
604 } else if (regno == PID) {
605 /* 32-bit register. */
606 *valptr = *(unsigned int *)((char *)®.pid);
607
608 } else if (regno == SRS) {
609 /* 8-bit register. */
610 *valptr = (unsigned int)(*(unsigned char *)((char *)®.srs));
611
612 } else if (regno == WZ) {
613 /* 16-bit register. */
614 *valptr = (unsigned int)(*(unsigned short *)(char *)®.wz);
615
616 } else if (regno >= EXS && regno <= PC) {
617 /* Consecutive 32-bit registers. */
618 *valptr = *(unsigned int *)((char *)®.exs + (regno - EXS) * sizeof(unsigned int));
619
620 } else if (regno >= S0 && regno <= S15) {
621 /* Consecutive 32-bit registers, located elsewhere. */
622 *valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int));
623
624 } else {
625 /* Non-existing register. */
626 status = E05;
627 }
628 return status;
629
630 }
631
632 /********************************** Packet I/O ******************************/
633 /* Convert the memory, pointed to by mem into hexadecimal representation.
634 Put the result in buf, and return a pointer to the last character
635 in buf (null). */
636
637 static char *
mem2hex(char * buf,unsigned char * mem,int count)638 mem2hex(char *buf, unsigned char *mem, int count)
639 {
640 int i;
641 int ch;
642
643 if (mem == NULL) {
644 /* Invalid address, caught by 'm' packet handler. */
645 for (i = 0; i < count; i++) {
646 *buf++ = '0';
647 *buf++ = '0';
648 }
649 } else {
650 /* Valid mem address. */
651 for (i = 0; i < count; i++) {
652 ch = *mem++;
653 buf = hex_byte_pack(buf, ch);
654 }
655 }
656 /* Terminate properly. */
657 *buf = '\0';
658 return buf;
659 }
660
661 /* Same as mem2hex, but puts it in network byte order. */
662 static char *
mem2hex_nbo(char * buf,unsigned char * mem,int count)663 mem2hex_nbo(char *buf, unsigned char *mem, int count)
664 {
665 int i;
666 int ch;
667
668 mem += count - 1;
669 for (i = 0; i < count; i++) {
670 ch = *mem--;
671 buf = hex_byte_pack(buf, ch);
672 }
673
674 /* Terminate properly. */
675 *buf = '\0';
676 return buf;
677 }
678
679 /* Put the content of the array, in binary representation, pointed to by buf
680 into memory pointed to by mem, and return a pointer to the character after
681 the last byte written.
682 Gdb will escape $, #, and the escape char (0x7d). */
683 static unsigned char*
bin2mem(unsigned char * mem,unsigned char * buf,int count)684 bin2mem(unsigned char *mem, unsigned char *buf, int count)
685 {
686 int i;
687 unsigned char *next;
688 for (i = 0; i < count; i++) {
689 /* Check for any escaped characters. Be paranoid and
690 only unescape chars that should be escaped. */
691 if (*buf == 0x7d) {
692 next = buf + 1;
693 if (*next == 0x3 || *next == 0x4 || *next == 0x5D) {
694 /* #, $, ESC */
695 buf++;
696 *buf += 0x20;
697 }
698 }
699 *mem++ = *buf++;
700 }
701 return mem;
702 }
703
704 /* Await the sequence $<data>#<checksum> and store <data> in the array buffer
705 returned. */
706 static void
getpacket(char * buffer)707 getpacket(char *buffer)
708 {
709 unsigned char checksum;
710 unsigned char xmitcsum;
711 int i;
712 int count;
713 char ch;
714
715 do {
716 while((ch = getDebugChar ()) != '$')
717 /* Wait for the start character $ and ignore all other characters */;
718 checksum = 0;
719 xmitcsum = -1;
720 count = 0;
721 /* Read until a # or the end of the buffer is reached */
722 while (count < BUFMAX) {
723 ch = getDebugChar();
724 if (ch == '#')
725 break;
726 checksum = checksum + ch;
727 buffer[count] = ch;
728 count = count + 1;
729 }
730
731 if (count >= BUFMAX)
732 continue;
733
734 buffer[count] = 0;
735
736 if (ch == '#') {
737 xmitcsum = hex_to_bin(getDebugChar()) << 4;
738 xmitcsum += hex_to_bin(getDebugChar());
739 if (checksum != xmitcsum) {
740 /* Wrong checksum */
741 putDebugChar('-');
742 } else {
743 /* Correct checksum */
744 putDebugChar('+');
745 /* If sequence characters are received, reply with them */
746 if (buffer[2] == ':') {
747 putDebugChar(buffer[0]);
748 putDebugChar(buffer[1]);
749 /* Remove the sequence characters from the buffer */
750 count = gdb_cris_strlen(buffer);
751 for (i = 3; i <= count; i++)
752 buffer[i - 3] = buffer[i];
753 }
754 }
755 }
756 } while (checksum != xmitcsum);
757 }
758
759 /* Send $<data>#<checksum> from the <data> in the array buffer. */
760
761 static void
putpacket(char * buffer)762 putpacket(char *buffer)
763 {
764 int checksum;
765 int runlen;
766 int encode;
767
768 do {
769 char *src = buffer;
770 putDebugChar('$');
771 checksum = 0;
772 while (*src) {
773 /* Do run length encoding */
774 putDebugChar(*src);
775 checksum += *src;
776 runlen = 0;
777 while (runlen < RUNLENMAX && *src == src[runlen]) {
778 runlen++;
779 }
780 if (runlen > 3) {
781 /* Got a useful amount */
782 putDebugChar ('*');
783 checksum += '*';
784 encode = runlen + ' ' - 4;
785 putDebugChar(encode);
786 checksum += encode;
787 src += runlen;
788 } else {
789 src++;
790 }
791 }
792 putDebugChar('#');
793 putDebugChar(hex_asc_hi(checksum));
794 putDebugChar(hex_asc_lo(checksum));
795 } while(kgdb_started && (getDebugChar() != '+'));
796 }
797
798 /* The string str is prepended with the GDB printout token and sent. Required
799 in traditional implementations. */
800 void
putDebugString(const unsigned char * str,int len)801 putDebugString(const unsigned char *str, int len)
802 {
803 /* Move SPC forward if we are single-stepping. */
804 asm("spchere:");
805 asm("move $spc, $r10");
806 asm("cmp.d spchere, $r10");
807 asm("bne nosstep");
808 asm("nop");
809 asm("move.d spccont, $r10");
810 asm("move $r10, $spc");
811 asm("nosstep:");
812
813 output_buffer[0] = 'O';
814 mem2hex(&output_buffer[1], (unsigned char *)str, len);
815 putpacket(output_buffer);
816
817 asm("spccont:");
818 }
819
820 /********************************** Handle exceptions ************************/
821 /* Build and send a response packet in order to inform the host the
822 stub is stopped. TAAn...:r...;n...:r...;n...:r...;
823 AA = signal number
824 n... = register number (hex)
825 r... = register contents
826 n... = `thread'
827 r... = thread process ID. This is a hex integer.
828 n... = other string not starting with valid hex digit.
829 gdb should ignore this n,r pair and go on to the next.
830 This way we can extend the protocol. */
831 static void
stub_is_stopped(int sigval)832 stub_is_stopped(int sigval)
833 {
834 char *ptr = output_buffer;
835 unsigned int reg_cont;
836
837 /* Send trap type (converted to signal) */
838
839 *ptr++ = 'T';
840 ptr = hex_byte_pack(ptr, sigval);
841
842 if (((reg.exs & 0xff00) >> 8) == 0xc) {
843
844 /* Some kind of hardware watchpoint triggered. Find which one
845 and determine its type (read/write/access). */
846 int S, bp, trig_bits = 0, rw_bits = 0;
847 int trig_mask = 0;
848 unsigned int *bp_d_regs = &sreg.s3_3;
849 /* In a lot of cases, the stopped data address will simply be EDA.
850 In some cases, we adjust it to match the watched data range.
851 (We don't want to change the actual EDA though). */
852 unsigned int stopped_data_address;
853 /* The S field of EXS. */
854 S = (reg.exs & 0xffff0000) >> 16;
855
856 if (S & 1) {
857 /* Instruction watchpoint. */
858 /* FIXME: Check against, and possibly adjust reported EDA. */
859 } else {
860 /* Data watchpoint. Find the one that triggered. */
861 for (bp = 0; bp < 6; bp++) {
862
863 /* Dx_RD, Dx_WR in the S field of EXS for this BP. */
864 int bitpos_trig = 1 + bp * 2;
865 /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
866 int bitpos_config = 2 + bp * 4;
867
868 /* Get read/write trig bits for this BP. */
869 trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig;
870
871 /* Read/write config bits for this BP. */
872 rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
873 if (trig_bits) {
874 /* Sanity check: the BP shouldn't trigger for accesses
875 that it isn't configured for. */
876 if ((rw_bits == 0x1 && trig_bits != 0x1) ||
877 (rw_bits == 0x2 && trig_bits != 0x2))
878 panic("Invalid r/w trigging for this BP");
879
880 /* Mark this BP as trigged for future reference. */
881 trig_mask |= (1 << bp);
882
883 if (reg.eda >= bp_d_regs[bp * 2] &&
884 reg.eda <= bp_d_regs[bp * 2 + 1]) {
885 /* EDA within range for this BP; it must be the one
886 we're looking for. */
887 stopped_data_address = reg.eda;
888 break;
889 }
890 }
891 }
892 if (bp < 6) {
893 /* Found a trigged BP with EDA within its configured data range. */
894 } else if (trig_mask) {
895 /* Something triggered, but EDA doesn't match any BP's range. */
896 for (bp = 0; bp < 6; bp++) {
897 /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
898 int bitpos_config = 2 + bp * 4;
899
900 /* Read/write config bits for this BP (needed later). */
901 rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
902
903 if (trig_mask & (1 << bp)) {
904 /* EDA within 31 bytes of the configured start address? */
905 if (reg.eda + 31 >= bp_d_regs[bp * 2]) {
906 /* Changing the reported address to match
907 the start address of the first applicable BP. */
908 stopped_data_address = bp_d_regs[bp * 2];
909 break;
910 } else {
911 /* We continue since we might find another useful BP. */
912 printk("EDA doesn't match trigged BP's range");
913 }
914 }
915 }
916 }
917
918 /* No match yet? */
919 BUG_ON(bp >= 6);
920 /* Note that we report the type according to what the BP is configured
921 for (otherwise we'd never report an 'awatch'), not according to how
922 it trigged. We did check that the trigged bits match what the BP is
923 configured for though. */
924 if (rw_bits == 0x1) {
925 /* read */
926 strncpy(ptr, "rwatch", 6);
927 ptr += 6;
928 } else if (rw_bits == 0x2) {
929 /* write */
930 strncpy(ptr, "watch", 5);
931 ptr += 5;
932 } else if (rw_bits == 0x3) {
933 /* access */
934 strncpy(ptr, "awatch", 6);
935 ptr += 6;
936 } else {
937 panic("Invalid r/w bits for this BP.");
938 }
939
940 *ptr++ = ':';
941 /* Note that we don't read_register(EDA, ...) */
942 ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]);
943 *ptr++ = ';';
944 }
945 }
946 /* Only send PC, frame and stack pointer. */
947 read_register(PC, ®_cont);
948 ptr = hex_byte_pack(ptr, PC);
949 *ptr++ = ':';
950 ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[PC]);
951 *ptr++ = ';';
952
953 read_register(R8, ®_cont);
954 ptr = hex_byte_pack(ptr, R8);
955 *ptr++ = ':';
956 ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[R8]);
957 *ptr++ = ';';
958
959 read_register(SP, ®_cont);
960 ptr = hex_byte_pack(ptr, SP);
961 *ptr++ = ':';
962 ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[SP]);
963 *ptr++ = ';';
964
965 /* Send ERP as well; this will save us an entire register fetch in some cases. */
966 read_register(ERP, ®_cont);
967 ptr = hex_byte_pack(ptr, ERP);
968 *ptr++ = ':';
969 ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[ERP]);
970 *ptr++ = ';';
971
972 /* null-terminate and send it off */
973 *ptr = 0;
974 putpacket(output_buffer);
975 }
976
977 /* Returns the size of an instruction that has a delay slot. */
978
insn_size(unsigned long pc)979 int insn_size(unsigned long pc)
980 {
981 unsigned short opcode = *(unsigned short *)pc;
982 int size = 0;
983
984 switch ((opcode & 0x0f00) >> 8) {
985 case 0x0:
986 case 0x9:
987 case 0xb:
988 size = 2;
989 break;
990 case 0xe:
991 case 0xf:
992 size = 6;
993 break;
994 case 0xd:
995 /* Could be 4 or 6; check more bits. */
996 if ((opcode & 0xff) == 0xff)
997 size = 4;
998 else
999 size = 6;
1000 break;
1001 default:
1002 panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc);
1003 }
1004
1005 return size;
1006 }
1007
register_fixup(int sigval)1008 void register_fixup(int sigval)
1009 {
1010 /* Compensate for ACR push at the beginning of exception handler. */
1011 reg.sp += 4;
1012
1013 /* Standard case. */
1014 reg.pc = reg.erp;
1015 if (reg.erp & 0x1) {
1016 /* Delay slot bit set. Report as stopped on proper instruction. */
1017 if (reg.spc) {
1018 /* Rely on SPC if set. */
1019 reg.pc = reg.spc;
1020 } else {
1021 /* Calculate the PC from the size of the instruction
1022 that the delay slot we're in belongs to. */
1023 reg.pc += insn_size(reg.erp & ~1) - 1 ;
1024 }
1025 }
1026
1027 if ((reg.exs & 0x3) == 0x0) {
1028 /* Bits 1 - 0 indicate the type of memory operation performed
1029 by the interrupted instruction. 0 means no memory operation,
1030 and EDA is undefined in that case. We zero it to avoid confusion. */
1031 reg.eda = 0;
1032 }
1033
1034 if (sigval == SIGTRAP) {
1035 /* Break 8, single step or hardware breakpoint exception. */
1036
1037 /* Check IDX field of EXS. */
1038 if (((reg.exs & 0xff00) >> 8) == 0x18) {
1039
1040 /* Break 8. */
1041
1042 /* Static (compiled) breakpoints must return to the next instruction
1043 in order to avoid infinite loops (default value of ERP). Dynamic
1044 (gdb-invoked) must subtract the size of the break instruction from
1045 the ERP so that the instruction that was originally in the break
1046 instruction's place will be run when we return from the exception. */
1047 if (!dynamic_bp) {
1048 /* Assuming that all breakpoints are dynamic from now on. */
1049 dynamic_bp = 1;
1050 } else {
1051
1052 /* Only if not in a delay slot. */
1053 if (!(reg.erp & 0x1)) {
1054 reg.erp -= 2;
1055 reg.pc -= 2;
1056 }
1057 }
1058
1059 } else if (((reg.exs & 0xff00) >> 8) == 0x3) {
1060 /* Single step. */
1061 /* Don't fiddle with S1. */
1062
1063 } else if (((reg.exs & 0xff00) >> 8) == 0xc) {
1064
1065 /* Hardware watchpoint exception. */
1066
1067 /* SPC has been updated so that we will get a single step exception
1068 when we return, but we don't want that. */
1069 reg.spc = 0;
1070
1071 /* Don't fiddle with S1. */
1072 }
1073
1074 } else if (sigval == SIGINT) {
1075 /* Nothing special. */
1076 }
1077 }
1078
insert_watchpoint(char type,int addr,int len)1079 static void insert_watchpoint(char type, int addr, int len)
1080 {
1081 /* Breakpoint/watchpoint types (GDB terminology):
1082 0 = memory breakpoint for instructions
1083 (not supported; done via memory write instead)
1084 1 = hardware breakpoint for instructions (supported)
1085 2 = write watchpoint (supported)
1086 3 = read watchpoint (supported)
1087 4 = access watchpoint (supported) */
1088
1089 if (type < '1' || type > '4') {
1090 output_buffer[0] = 0;
1091 return;
1092 }
1093
1094 /* Read watchpoints are set as access watchpoints, because of GDB's
1095 inability to deal with pure read watchpoints. */
1096 if (type == '3')
1097 type = '4';
1098
1099 if (type == '1') {
1100 /* Hardware (instruction) breakpoint. */
1101 /* Bit 0 in BP_CTRL holds the configuration for I0. */
1102 if (sreg.s0_3 & 0x1) {
1103 /* Already in use. */
1104 gdb_cris_strcpy(output_buffer, error_message[E04]);
1105 return;
1106 }
1107 /* Configure. */
1108 sreg.s1_3 = addr;
1109 sreg.s2_3 = (addr + len - 1);
1110 sreg.s0_3 |= 1;
1111 } else {
1112 int bp;
1113 unsigned int *bp_d_regs = &sreg.s3_3;
1114
1115 /* The watchpoint allocation scheme is the simplest possible.
1116 For example, if a region is watched for read and
1117 a write watch is requested, a new watchpoint will
1118 be used. Also, if a watch for a region that is already
1119 covered by one or more existing watchpoints, a new
1120 watchpoint will be used. */
1121
1122 /* First, find a free data watchpoint. */
1123 for (bp = 0; bp < 6; bp++) {
1124 /* Each data watchpoint's control registers occupy 2 bits
1125 (hence the 3), starting at bit 2 for D0 (hence the 2)
1126 with 4 bits between for each watchpoint (yes, the 4). */
1127 if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) {
1128 break;
1129 }
1130 }
1131
1132 if (bp > 5) {
1133 /* We're out of watchpoints. */
1134 gdb_cris_strcpy(output_buffer, error_message[E04]);
1135 return;
1136 }
1137
1138 /* Configure the control register first. */
1139 if (type == '3' || type == '4') {
1140 /* Trigger on read. */
1141 sreg.s0_3 |= (1 << (2 + bp * 4));
1142 }
1143 if (type == '2' || type == '4') {
1144 /* Trigger on write. */
1145 sreg.s0_3 |= (2 << (2 + bp * 4));
1146 }
1147
1148 /* Ugly pointer arithmetics to configure the watched range. */
1149 bp_d_regs[bp * 2] = addr;
1150 bp_d_regs[bp * 2 + 1] = (addr + len - 1);
1151 }
1152
1153 /* Set the S1 flag to enable watchpoints. */
1154 reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
1155 gdb_cris_strcpy(output_buffer, "OK");
1156 }
1157
remove_watchpoint(char type,int addr,int len)1158 static void remove_watchpoint(char type, int addr, int len)
1159 {
1160 /* Breakpoint/watchpoint types:
1161 0 = memory breakpoint for instructions
1162 (not supported; done via memory write instead)
1163 1 = hardware breakpoint for instructions (supported)
1164 2 = write watchpoint (supported)
1165 3 = read watchpoint (supported)
1166 4 = access watchpoint (supported) */
1167 if (type < '1' || type > '4') {
1168 output_buffer[0] = 0;
1169 return;
1170 }
1171
1172 /* Read watchpoints are set as access watchpoints, because of GDB's
1173 inability to deal with pure read watchpoints. */
1174 if (type == '3')
1175 type = '4';
1176
1177 if (type == '1') {
1178 /* Hardware breakpoint. */
1179 /* Bit 0 in BP_CTRL holds the configuration for I0. */
1180 if (!(sreg.s0_3 & 0x1)) {
1181 /* Not in use. */
1182 gdb_cris_strcpy(output_buffer, error_message[E04]);
1183 return;
1184 }
1185 /* Deconfigure. */
1186 sreg.s1_3 = 0;
1187 sreg.s2_3 = 0;
1188 sreg.s0_3 &= ~1;
1189 } else {
1190 int bp;
1191 unsigned int *bp_d_regs = &sreg.s3_3;
1192 /* Try to find a watchpoint that is configured for the
1193 specified range, then check that read/write also matches. */
1194
1195 /* Ugly pointer arithmetic, since I cannot rely on a
1196 single switch (addr) as there may be several watchpoints with
1197 the same start address for example. */
1198
1199 for (bp = 0; bp < 6; bp++) {
1200 if (bp_d_regs[bp * 2] == addr &&
1201 bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
1202 /* Matching range. */
1203 int bitpos = 2 + bp * 4;
1204 int rw_bits;
1205
1206 /* Read/write bits for this BP. */
1207 rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos;
1208
1209 if ((type == '3' && rw_bits == 0x1) ||
1210 (type == '2' && rw_bits == 0x2) ||
1211 (type == '4' && rw_bits == 0x3)) {
1212 /* Read/write matched. */
1213 break;
1214 }
1215 }
1216 }
1217
1218 if (bp > 5) {
1219 /* No watchpoint matched. */
1220 gdb_cris_strcpy(output_buffer, error_message[E04]);
1221 return;
1222 }
1223
1224 /* Found a matching watchpoint. Now, deconfigure it by
1225 both disabling read/write in bp_ctrl and zeroing its
1226 start/end addresses. */
1227 sreg.s0_3 &= ~(3 << (2 + (bp * 4)));
1228 bp_d_regs[bp * 2] = 0;
1229 bp_d_regs[bp * 2 + 1] = 0;
1230 }
1231
1232 /* Note that we don't clear the S1 flag here. It's done when continuing. */
1233 gdb_cris_strcpy(output_buffer, "OK");
1234 }
1235
1236
1237
1238 /* All expected commands are sent from remote.c. Send a response according
1239 to the description in remote.c. */
1240 void
handle_exception(int sigval)1241 handle_exception(int sigval)
1242 {
1243 /* Avoid warning of not used. */
1244
1245 USEDFUN(handle_exception);
1246 USEDVAR(internal_stack[0]);
1247
1248 register_fixup(sigval);
1249
1250 /* Send response. */
1251 stub_is_stopped(sigval);
1252
1253 for (;;) {
1254 output_buffer[0] = '\0';
1255 getpacket(input_buffer);
1256 switch (input_buffer[0]) {
1257 case 'g':
1258 /* Read registers: g
1259 Success: Each byte of register data is described by two hex digits.
1260 Registers are in the internal order for GDB, and the bytes
1261 in a register are in the same order the machine uses.
1262 Failure: void. */
1263 {
1264 char *buf;
1265 /* General and special registers. */
1266 buf = mem2hex(output_buffer, (char *)®, sizeof(registers));
1267 /* Support registers. */
1268 /* -1 because of the null termination that mem2hex adds. */
1269 mem2hex(buf,
1270 (char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
1271 16 * sizeof(unsigned int));
1272 break;
1273 }
1274 case 'G':
1275 /* Write registers. GXX..XX
1276 Each byte of register data is described by two hex digits.
1277 Success: OK
1278 Failure: E08. */
1279 /* General and special registers. */
1280 if (hex2bin((char *)®, &input_buffer[1], sizeof(registers)))
1281 gdb_cris_strcpy(output_buffer, error_message[E08]);
1282 /* Support registers. */
1283 else if (hex2bin((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
1284 &input_buffer[1] + sizeof(registers),
1285 16 * sizeof(unsigned int)))
1286 gdb_cris_strcpy(output_buffer, error_message[E08]);
1287 else
1288 gdb_cris_strcpy(output_buffer, "OK");
1289 break;
1290
1291 case 'P':
1292 /* Write register. Pn...=r...
1293 Write register n..., hex value without 0x, with value r...,
1294 which contains a hex value without 0x and two hex digits
1295 for each byte in the register (target byte order). P1f=11223344 means
1296 set register 31 to 44332211.
1297 Success: OK
1298 Failure: E02, E05 */
1299 {
1300 char *suffix;
1301 int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16);
1302 int status;
1303
1304 status = write_register(regno, suffix+1);
1305
1306 switch (status) {
1307 case E02:
1308 /* Do not support read-only registers. */
1309 gdb_cris_strcpy(output_buffer, error_message[E02]);
1310 break;
1311 case E05:
1312 /* Do not support non-existing registers. */
1313 gdb_cris_strcpy(output_buffer, error_message[E05]);
1314 break;
1315 case E08:
1316 /* Invalid parameter. */
1317 gdb_cris_strcpy(output_buffer, error_message[E08]);
1318 break;
1319 default:
1320 /* Valid register number. */
1321 gdb_cris_strcpy(output_buffer, "OK");
1322 break;
1323 }
1324 }
1325 break;
1326
1327 case 'm':
1328 /* Read from memory. mAA..AA,LLLL
1329 AA..AA is the address and LLLL is the length.
1330 Success: XX..XX is the memory content. Can be fewer bytes than
1331 requested if only part of the data may be read. m6000120a,6c means
1332 retrieve 108 byte from base address 6000120a.
1333 Failure: void. */
1334 {
1335 char *suffix;
1336 unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
1337 &suffix, 16);
1338 int len = gdb_cris_strtol(suffix+1, 0, 16);
1339
1340 /* Bogus read (i.e. outside the kernel's
1341 segment)? . */
1342 if (!((unsigned int)addr >= 0xc0000000 &&
1343 (unsigned int)addr < 0xd0000000))
1344 addr = NULL;
1345
1346 mem2hex(output_buffer, addr, len);
1347 }
1348 break;
1349
1350 case 'X':
1351 /* Write to memory. XAA..AA,LLLL:XX..XX
1352 AA..AA is the start address, LLLL is the number of bytes, and
1353 XX..XX is the binary data.
1354 Success: OK
1355 Failure: void. */
1356 case 'M':
1357 /* Write to memory. MAA..AA,LLLL:XX..XX
1358 AA..AA is the start address, LLLL is the number of bytes, and
1359 XX..XX is the hexadecimal data.
1360 Success: OK
1361 Failure: E08. */
1362 {
1363 char *lenptr;
1364 char *dataptr;
1365 unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
1366 &lenptr, 16);
1367 int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
1368 if (*lenptr == ',' && *dataptr == ':') {
1369 if (input_buffer[0] == 'M') {
1370 if (hex2bin(addr, dataptr + 1, len))
1371 gdb_cris_strcpy(output_buffer, error_message[E08]);
1372 else
1373 gdb_cris_strcpy(output_buffer, "OK");
1374 } else /* X */ {
1375 bin2mem(addr, dataptr + 1, len);
1376 gdb_cris_strcpy(output_buffer, "OK");
1377 }
1378 } else {
1379 gdb_cris_strcpy(output_buffer, error_message[E06]);
1380 }
1381 }
1382 break;
1383
1384 case 'c':
1385 /* Continue execution. cAA..AA
1386 AA..AA is the address where execution is resumed. If AA..AA is
1387 omitted, resume at the present address.
1388 Success: return to the executing thread.
1389 Failure: will never know. */
1390
1391 if (input_buffer[1] != '\0') {
1392 /* FIXME: Doesn't handle address argument. */
1393 gdb_cris_strcpy(output_buffer, error_message[E04]);
1394 break;
1395 }
1396
1397 /* Before continuing, make sure everything is set up correctly. */
1398
1399 /* Set the SPC to some unlikely value. */
1400 reg.spc = 0;
1401 /* Set the S1 flag to 0 unless some watchpoint is enabled (since setting
1402 S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL
1403 are reserved, so don't check against those). */
1404 if ((sreg.s0_3 & 0x3fff) == 0) {
1405 reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
1406 }
1407
1408 return;
1409
1410 case 's':
1411 /* Step. sAA..AA
1412 AA..AA is the address where execution is resumed. If AA..AA is
1413 omitted, resume at the present address. Success: return to the
1414 executing thread. Failure: will never know. */
1415
1416 if (input_buffer[1] != '\0') {
1417 /* FIXME: Doesn't handle address argument. */
1418 gdb_cris_strcpy(output_buffer, error_message[E04]);
1419 break;
1420 }
1421
1422 /* Set the SPC to PC, which is where we'll return
1423 (deduced previously). */
1424 reg.spc = reg.pc;
1425
1426 /* Set the S1 (first stacked, not current) flag, which will
1427 kick into action when we rfe. */
1428 reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
1429 return;
1430
1431 case 'Z':
1432
1433 /* Insert breakpoint or watchpoint, Ztype,addr,length.
1434 Remote protocol says: A remote target shall return an empty string
1435 for an unrecognized breakpoint or watchpoint packet type. */
1436 {
1437 char *lenptr;
1438 char *dataptr;
1439 int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
1440 int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
1441 char type = input_buffer[1];
1442
1443 insert_watchpoint(type, addr, len);
1444 break;
1445 }
1446
1447 case 'z':
1448 /* Remove breakpoint or watchpoint, Ztype,addr,length.
1449 Remote protocol says: A remote target shall return an empty string
1450 for an unrecognized breakpoint or watchpoint packet type. */
1451 {
1452 char *lenptr;
1453 char *dataptr;
1454 int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
1455 int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
1456 char type = input_buffer[1];
1457
1458 remove_watchpoint(type, addr, len);
1459 break;
1460 }
1461
1462
1463 case '?':
1464 /* The last signal which caused a stop. ?
1465 Success: SAA, where AA is the signal number.
1466 Failure: void. */
1467 output_buffer[0] = 'S';
1468 output_buffer[1] = hex_asc_hi(sigval);
1469 output_buffer[2] = hex_asc_lo(sigval);
1470 output_buffer[3] = 0;
1471 break;
1472
1473 case 'D':
1474 /* Detach from host. D
1475 Success: OK, and return to the executing thread.
1476 Failure: will never know */
1477 putpacket("OK");
1478 return;
1479
1480 case 'k':
1481 case 'r':
1482 /* kill request or reset request.
1483 Success: restart of target.
1484 Failure: will never know. */
1485 kill_restart();
1486 break;
1487
1488 case 'C':
1489 case 'S':
1490 case '!':
1491 case 'R':
1492 case 'd':
1493 /* Continue with signal sig. Csig;AA..AA
1494 Step with signal sig. Ssig;AA..AA
1495 Use the extended remote protocol. !
1496 Restart the target system. R0
1497 Toggle debug flag. d
1498 Search backwards. tAA:PP,MM
1499 Not supported: E04 */
1500
1501 /* FIXME: What's the difference between not supported
1502 and ignored (below)? */
1503 gdb_cris_strcpy(output_buffer, error_message[E04]);
1504 break;
1505
1506 default:
1507 /* The stub should ignore other request and send an empty
1508 response ($#<checksum>). This way we can extend the protocol and GDB
1509 can tell whether the stub it is talking to uses the old or the new. */
1510 output_buffer[0] = 0;
1511 break;
1512 }
1513 putpacket(output_buffer);
1514 }
1515 }
1516
1517 void
kgdb_init(void)1518 kgdb_init(void)
1519 {
1520 reg_intr_vect_rw_mask intr_mask;
1521 reg_ser_rw_intr_mask ser_intr_mask;
1522
1523 /* Configure the kgdb serial port. */
1524 #if defined(CONFIG_ETRAX_KGDB_PORT0)
1525 /* Note: no shortcut registered (not handled by multiple_interrupt).
1526 See entry.S. */
1527 set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception);
1528 /* Enable the ser irq in the global config. */
1529 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1530 intr_mask.ser0 = 1;
1531 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1532
1533 ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask);
1534 ser_intr_mask.dav = regk_ser_yes;
1535 REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask);
1536 #elif defined(CONFIG_ETRAX_KGDB_PORT1)
1537 /* Note: no shortcut registered (not handled by multiple_interrupt).
1538 See entry.S. */
1539 set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception);
1540 /* Enable the ser irq in the global config. */
1541 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1542 intr_mask.ser1 = 1;
1543 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1544
1545 ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask);
1546 ser_intr_mask.dav = regk_ser_yes;
1547 REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask);
1548 #elif defined(CONFIG_ETRAX_KGDB_PORT2)
1549 /* Note: no shortcut registered (not handled by multiple_interrupt).
1550 See entry.S. */
1551 set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception);
1552 /* Enable the ser irq in the global config. */
1553 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1554 intr_mask.ser2 = 1;
1555 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1556
1557 ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask);
1558 ser_intr_mask.dav = regk_ser_yes;
1559 REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask);
1560 #elif defined(CONFIG_ETRAX_KGDB_PORT3)
1561 /* Note: no shortcut registered (not handled by multiple_interrupt).
1562 See entry.S. */
1563 set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception);
1564 /* Enable the ser irq in the global config. */
1565 intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1566 intr_mask.ser3 = 1;
1567 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1568
1569 ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask);
1570 ser_intr_mask.dav = regk_ser_yes;
1571 REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask);
1572 #endif
1573
1574 }
1575 /* Performs a complete re-start from scratch. */
1576 static void
kill_restart(void)1577 kill_restart(void)
1578 {
1579 machine_restart("");
1580 }
1581
1582 /* Use this static breakpoint in the start-up only. */
1583
1584 void
breakpoint(void)1585 breakpoint(void)
1586 {
1587 kgdb_started = 1;
1588 dynamic_bp = 0; /* This is a static, not a dynamic breakpoint. */
1589 __asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */
1590 }
1591
1592 /****************************** End of file **********************************/
1593