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1 #ifndef __iop_dmc_out_defs_h
2 #define __iop_dmc_out_defs_h
3 
4 /*
5  * This file is autogenerated from
6  *   file:           ../../inst/io_proc/rtl/iop_dmc_out.r
7  *     id:           iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
8  *     last modfied: Mon Apr 11 16:08:45 2005
9  *
10  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
11  *      id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
12  * Any changes here will be lost.
13  *
14  * -*- buffer-read-only: t -*-
15  */
16 /* Main access macros */
17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \
19   REG_READ( reg_##scope##_##reg, \
20             (inst) + REG_RD_ADDR_##scope##_##reg )
21 #endif
22 
23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \
25   REG_WRITE( reg_##scope##_##reg, \
26              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #endif
28 
29 #ifndef REG_RD_VECT
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31   REG_READ( reg_##scope##_##reg, \
32             (inst) + REG_RD_ADDR_##scope##_##reg + \
33 	    (index) * STRIDE_##scope##_##reg )
34 #endif
35 
36 #ifndef REG_WR_VECT
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38   REG_WRITE( reg_##scope##_##reg, \
39              (inst) + REG_WR_ADDR_##scope##_##reg + \
40 	     (index) * STRIDE_##scope##_##reg, (val) )
41 #endif
42 
43 #ifndef REG_RD_INT
44 #define REG_RD_INT( scope, inst, reg ) \
45   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #endif
47 
48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \
50   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #endif
52 
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 	    (index) * STRIDE_##scope##_##reg )
57 #endif
58 
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 	     (index) * STRIDE_##scope##_##reg, (val) )
63 #endif
64 
65 #ifndef REG_TYPE_CONV
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68 #endif
69 
70 #ifndef reg_page_size
71 #define reg_page_size 8192
72 #endif
73 
74 #ifndef REG_ADDR
75 #define REG_ADDR( scope, inst, reg ) \
76   ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #endif
78 
79 #ifndef REG_ADDR_VECT
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82     (index) * STRIDE_##scope##_##reg )
83 #endif
84 
85 /* C-code for register scope iop_dmc_out */
86 
87 /* Register rw_cfg, scope iop_dmc_out, type rw */
88 typedef struct {
89   unsigned int trf_lim         : 16;
90   unsigned int last_at_trf_lim : 1;
91   unsigned int dth_intr        : 3;
92   unsigned int dummy1          : 12;
93 } reg_iop_dmc_out_rw_cfg;
94 #define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
95 #define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
96 
97 /* Register rw_ctrl, scope iop_dmc_out, type rw */
98 typedef struct {
99   unsigned int dif_en  : 1;
100   unsigned int dif_dis : 1;
101   unsigned int dummy1  : 30;
102 } reg_iop_dmc_out_rw_ctrl;
103 #define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
104 #define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
105 
106 /* Register r_stat, scope iop_dmc_out, type r */
107 typedef struct {
108   unsigned int dif_en : 1;
109   unsigned int dummy1 : 31;
110 } reg_iop_dmc_out_r_stat;
111 #define REG_RD_ADDR_iop_dmc_out_r_stat 8
112 
113 /* Register rw_stream_cmd, scope iop_dmc_out, type rw */
114 typedef struct {
115   unsigned int cmd : 10;
116   unsigned int dummy1 : 6;
117   unsigned int n   : 8;
118   unsigned int dummy2 : 8;
119 } reg_iop_dmc_out_rw_stream_cmd;
120 #define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
121 #define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
122 
123 /* Register rs_stream_data, scope iop_dmc_out, type rs */
124 typedef unsigned int reg_iop_dmc_out_rs_stream_data;
125 #define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
126 
127 /* Register r_stream_data, scope iop_dmc_out, type r */
128 typedef unsigned int reg_iop_dmc_out_r_stream_data;
129 #define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
130 
131 /* Register r_stream_stat, scope iop_dmc_out, type r */
132 typedef struct {
133   unsigned int dth            : 7;
134   unsigned int dummy1         : 9;
135   unsigned int dv             : 1;
136   unsigned int all_avail      : 1;
137   unsigned int last           : 1;
138   unsigned int size           : 3;
139   unsigned int data_md_valid  : 1;
140   unsigned int ctxt_md_valid  : 1;
141   unsigned int group_md_valid : 1;
142   unsigned int stream_busy    : 1;
143   unsigned int cmd_rdy        : 1;
144   unsigned int cmd_rq         : 1;
145   unsigned int dummy2         : 4;
146 } reg_iop_dmc_out_r_stream_stat;
147 #define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
148 
149 /* Register r_data_descr, scope iop_dmc_out, type r */
150 typedef struct {
151   unsigned int ctrl : 8;
152   unsigned int stat : 8;
153   unsigned int md   : 16;
154 } reg_iop_dmc_out_r_data_descr;
155 #define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
156 
157 /* Register r_ctxt_descr, scope iop_dmc_out, type r */
158 typedef struct {
159   unsigned int ctrl : 8;
160   unsigned int stat : 8;
161   unsigned int md0  : 16;
162 } reg_iop_dmc_out_r_ctxt_descr;
163 #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
164 
165 /* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
166 typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
167 #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
168 
169 /* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
170 typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
171 #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
172 
173 /* Register r_group_descr, scope iop_dmc_out, type r */
174 typedef struct {
175   unsigned int ctrl : 8;
176   unsigned int stat : 8;
177   unsigned int md   : 16;
178 } reg_iop_dmc_out_r_group_descr;
179 #define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
180 
181 /* Register rw_data_descr, scope iop_dmc_out, type rw */
182 typedef struct {
183   unsigned int dummy1 : 16;
184   unsigned int md : 16;
185 } reg_iop_dmc_out_rw_data_descr;
186 #define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
187 #define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
188 
189 /* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
190 typedef struct {
191   unsigned int dummy1 : 16;
192   unsigned int md0 : 16;
193 } reg_iop_dmc_out_rw_ctxt_descr;
194 #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
195 #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
196 
197 /* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
198 typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
199 #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
200 #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
201 
202 /* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
203 typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
204 #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
205 #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
206 
207 /* Register rw_group_descr, scope iop_dmc_out, type rw */
208 typedef struct {
209   unsigned int dummy1 : 16;
210   unsigned int md : 16;
211 } reg_iop_dmc_out_rw_group_descr;
212 #define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
213 #define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
214 
215 /* Register rw_intr_mask, scope iop_dmc_out, type rw */
216 typedef struct {
217   unsigned int data_md   : 1;
218   unsigned int ctxt_md   : 1;
219   unsigned int group_md  : 1;
220   unsigned int cmd_rdy   : 1;
221   unsigned int dth       : 1;
222   unsigned int dv        : 1;
223   unsigned int last_data : 1;
224   unsigned int trf_lim   : 1;
225   unsigned int cmd_rq    : 1;
226   unsigned int dummy1    : 23;
227 } reg_iop_dmc_out_rw_intr_mask;
228 #define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
229 #define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
230 
231 /* Register rw_ack_intr, scope iop_dmc_out, type rw */
232 typedef struct {
233   unsigned int data_md   : 1;
234   unsigned int ctxt_md   : 1;
235   unsigned int group_md  : 1;
236   unsigned int cmd_rdy   : 1;
237   unsigned int dth       : 1;
238   unsigned int dv        : 1;
239   unsigned int last_data : 1;
240   unsigned int trf_lim   : 1;
241   unsigned int cmd_rq    : 1;
242   unsigned int dummy1    : 23;
243 } reg_iop_dmc_out_rw_ack_intr;
244 #define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
245 #define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
246 
247 /* Register r_intr, scope iop_dmc_out, type r */
248 typedef struct {
249   unsigned int data_md   : 1;
250   unsigned int ctxt_md   : 1;
251   unsigned int group_md  : 1;
252   unsigned int cmd_rdy   : 1;
253   unsigned int dth       : 1;
254   unsigned int dv        : 1;
255   unsigned int last_data : 1;
256   unsigned int trf_lim   : 1;
257   unsigned int cmd_rq    : 1;
258   unsigned int dummy1    : 23;
259 } reg_iop_dmc_out_r_intr;
260 #define REG_RD_ADDR_iop_dmc_out_r_intr 92
261 
262 /* Register r_masked_intr, scope iop_dmc_out, type r */
263 typedef struct {
264   unsigned int data_md   : 1;
265   unsigned int ctxt_md   : 1;
266   unsigned int group_md  : 1;
267   unsigned int cmd_rdy   : 1;
268   unsigned int dth       : 1;
269   unsigned int dv        : 1;
270   unsigned int last_data : 1;
271   unsigned int trf_lim   : 1;
272   unsigned int cmd_rq    : 1;
273   unsigned int dummy1    : 23;
274 } reg_iop_dmc_out_r_masked_intr;
275 #define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
276 
277 
278 /* Constants */
279 enum {
280   regk_iop_dmc_out_ack_pkt                 = 0x00000100,
281   regk_iop_dmc_out_array                   = 0x00000008,
282   regk_iop_dmc_out_burst                   = 0x00000020,
283   regk_iop_dmc_out_copy_next               = 0x00000010,
284   regk_iop_dmc_out_copy_up                 = 0x00000020,
285   regk_iop_dmc_out_dis_c                   = 0x00000010,
286   regk_iop_dmc_out_dis_g                   = 0x00000020,
287   regk_iop_dmc_out_lim1                    = 0x00000000,
288   regk_iop_dmc_out_lim16                   = 0x00000004,
289   regk_iop_dmc_out_lim2                    = 0x00000001,
290   regk_iop_dmc_out_lim32                   = 0x00000005,
291   regk_iop_dmc_out_lim4                    = 0x00000002,
292   regk_iop_dmc_out_lim64                   = 0x00000006,
293   regk_iop_dmc_out_lim8                    = 0x00000003,
294   regk_iop_dmc_out_load_c                  = 0x00000200,
295   regk_iop_dmc_out_load_c_n                = 0x00000280,
296   regk_iop_dmc_out_load_c_next             = 0x00000240,
297   regk_iop_dmc_out_load_d                  = 0x00000140,
298   regk_iop_dmc_out_load_g                  = 0x00000300,
299   regk_iop_dmc_out_load_g_down             = 0x000003c0,
300   regk_iop_dmc_out_load_g_next             = 0x00000340,
301   regk_iop_dmc_out_load_g_up               = 0x00000380,
302   regk_iop_dmc_out_next_en                 = 0x00000010,
303   regk_iop_dmc_out_next_pkt                = 0x00000010,
304   regk_iop_dmc_out_no                      = 0x00000000,
305   regk_iop_dmc_out_restore                 = 0x00000020,
306   regk_iop_dmc_out_rw_cfg_default          = 0x00000000,
307   regk_iop_dmc_out_rw_ctxt_descr_default   = 0x00000000,
308   regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
309   regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
310   regk_iop_dmc_out_rw_data_descr_default   = 0x00000000,
311   regk_iop_dmc_out_rw_group_descr_default  = 0x00000000,
312   regk_iop_dmc_out_rw_intr_mask_default    = 0x00000000,
313   regk_iop_dmc_out_save_down               = 0x00000020,
314   regk_iop_dmc_out_save_up                 = 0x00000020,
315   regk_iop_dmc_out_set_reg                 = 0x00000050,
316   regk_iop_dmc_out_set_w_size1             = 0x00000190,
317   regk_iop_dmc_out_set_w_size2             = 0x000001a0,
318   regk_iop_dmc_out_set_w_size4             = 0x000001c0,
319   regk_iop_dmc_out_store_c                 = 0x00000002,
320   regk_iop_dmc_out_store_descr             = 0x00000000,
321   regk_iop_dmc_out_store_g                 = 0x00000004,
322   regk_iop_dmc_out_store_md                = 0x00000001,
323   regk_iop_dmc_out_update_down             = 0x00000020,
324   regk_iop_dmc_out_yes                     = 0x00000001
325 };
326 #endif /* __iop_dmc_out_defs_h */
327