1 /***************************************************************************/
2
3 /*
4 * m5272.c -- platform support for ColdFire 5272 based boards
5 *
6 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
7 * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
8 */
9
10 /***************************************************************************/
11
12 #include <linux/kernel.h>
13 #include <linux/param.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <asm/machdep.h>
19 #include <asm/coldfire.h>
20 #include <asm/mcfsim.h>
21 #include <asm/mcfuart.h>
22 #include <asm/mcfclk.h>
23
24 /***************************************************************************/
25
26 /*
27 * Some platforms need software versions of the GPIO data registers.
28 */
29 unsigned short ppdata;
30 unsigned char ledbank = 0xff;
31
32 /***************************************************************************/
33
34 DEFINE_CLK(pll, "pll.0", MCF_CLK);
35 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
36 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
37 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
38 DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
39 DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
40 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
41 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
42 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
43 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
44
45 struct clk *mcf_clks[] = {
46 &clk_pll,
47 &clk_sys,
48 &clk_mcftmr0,
49 &clk_mcftmr1,
50 &clk_mcftmr2,
51 &clk_mcftmr3,
52 &clk_mcfuart0,
53 &clk_mcfuart1,
54 &clk_mcfqspi0,
55 &clk_fec0,
56 NULL
57 };
58
59 /***************************************************************************/
60
m5272_uarts_init(void)61 static void __init m5272_uarts_init(void)
62 {
63 u32 v;
64
65 /* Enable the output lines for the serial ports */
66 v = readl(MCFSIM_PBCNT);
67 v = (v & ~0x000000ff) | 0x00000055;
68 writel(v, MCFSIM_PBCNT);
69
70 v = readl(MCFSIM_PDCNT);
71 v = (v & ~0x000003fc) | 0x000002a8;
72 writel(v, MCFSIM_PDCNT);
73 }
74
75 /***************************************************************************/
76
m5272_cpu_reset(void)77 static void m5272_cpu_reset(void)
78 {
79 local_irq_disable();
80 /* Set watchdog to reset, and enabled */
81 __raw_writew(0, MCFSIM_WIRR);
82 __raw_writew(1, MCFSIM_WRRR);
83 __raw_writew(0, MCFSIM_WCR);
84 for (;;)
85 /* wait for watchdog to timeout */;
86 }
87
88 /***************************************************************************/
89
config_BSP(char * commandp,int size)90 void __init config_BSP(char *commandp, int size)
91 {
92 #if defined (CONFIG_MOD5272)
93 /* Set base of device vectors to be 64 */
94 writeb(0x40, MCFSIM_PIVR);
95 #endif
96
97 #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
98 /* Copy command line from FLASH to local buffer... */
99 memcpy(commandp, (char *) 0xf0004000, size);
100 commandp[size-1] = 0;
101 #elif defined(CONFIG_CANCam)
102 /* Copy command line from FLASH to local buffer... */
103 memcpy(commandp, (char *) 0xf0010000, size);
104 commandp[size-1] = 0;
105 #endif
106
107 mach_reset = m5272_cpu_reset;
108 mach_sched_init = hw_timer_init;
109 }
110
111 /***************************************************************************/
112
113 /*
114 * Some 5272 based boards have the FEC ethernet diectly connected to
115 * an ethernet switch. In this case we need to use the fixed phy type,
116 * and we need to declare it early in boot.
117 */
118 static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
119 .link = 1,
120 .speed = 100,
121 .duplex = 0,
122 };
123
124 /***************************************************************************/
125
init_BSP(void)126 static int __init init_BSP(void)
127 {
128 m5272_uarts_init();
129 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status, -1);
130 return 0;
131 }
132
133 arch_initcall(init_BSP);
134
135 /***************************************************************************/
136