1/ { 2 compatible = "qca,ar9132"; 3 4 #address-cells = <1>; 5 #size-cells = <1>; 6 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 11 cpu@0 { 12 device_type = "cpu"; 13 compatible = "mips,mips24Kc"; 14 reg = <0>; 15 }; 16 }; 17 18 cpuintc: interrupt-controller { 19 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 20 21 interrupt-controller; 22 #interrupt-cells = <1>; 23 24 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; 25 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, 26 <&ddr_ctrl 0>, <&ddr_ctrl 1>; 27 }; 28 29 ahb { 30 compatible = "simple-bus"; 31 ranges; 32 33 #address-cells = <1>; 34 #size-cells = <1>; 35 36 interrupt-parent = <&cpuintc>; 37 38 apb { 39 compatible = "simple-bus"; 40 ranges; 41 42 #address-cells = <1>; 43 #size-cells = <1>; 44 45 interrupt-parent = <&miscintc>; 46 47 ddr_ctrl: memory-controller@18000000 { 48 compatible = "qca,ar9132-ddr-controller", 49 "qca,ar7240-ddr-controller"; 50 reg = <0x18000000 0x100>; 51 52 #qca,ddr-wb-channel-cells = <1>; 53 }; 54 55 uart@18020000 { 56 compatible = "ns8250"; 57 reg = <0x18020000 0x20>; 58 interrupts = <3>; 59 60 clocks = <&pll 2>; 61 clock-names = "uart"; 62 63 reg-io-width = <4>; 64 reg-shift = <2>; 65 no-loopback-test; 66 67 status = "disabled"; 68 }; 69 70 gpio: gpio@18040000 { 71 compatible = "qca,ar9132-gpio", 72 "qca,ar7100-gpio"; 73 reg = <0x18040000 0x30>; 74 interrupts = <2>; 75 76 ngpios = <22>; 77 78 gpio-controller; 79 #gpio-cells = <2>; 80 81 interrupt-controller; 82 #interrupt-cells = <2>; 83 }; 84 85 pll: pll-controller@18050000 { 86 compatible = "qca,ar9132-ppl", 87 "qca,ar9130-pll"; 88 reg = <0x18050000 0x20>; 89 90 clock-names = "ref"; 91 /* The board must provides the ref clock */ 92 93 #clock-cells = <1>; 94 clock-output-names = "cpu", "ddr", "ahb"; 95 }; 96 97 wdt@18060008 { 98 compatible = "qca,ar7130-wdt"; 99 reg = <0x18060008 0x8>; 100 101 interrupts = <4>; 102 103 clocks = <&pll 2>; 104 clock-names = "wdt"; 105 }; 106 107 miscintc: interrupt-controller@18060010 { 108 compatible = "qca,ar9132-misc-intc", 109 "qca,ar7100-misc-intc"; 110 reg = <0x18060010 0x8>; 111 112 interrupt-parent = <&cpuintc>; 113 interrupts = <6>; 114 115 interrupt-controller; 116 #interrupt-cells = <1>; 117 }; 118 119 rst: reset-controller@1806001c { 120 compatible = "qca,ar9132-reset", 121 "qca,ar7100-reset"; 122 reg = <0x1806001c 0x4>; 123 124 #reset-cells = <1>; 125 }; 126 }; 127 128 spi@1f000000 { 129 compatible = "qca,ar9132-spi", "qca,ar7100-spi"; 130 reg = <0x1f000000 0x10>; 131 132 clocks = <&pll 2>; 133 clock-names = "ahb"; 134 135 status = "disabled"; 136 137 #address-cells = <1>; 138 #size-cells = <0>; 139 }; 140 }; 141}; 142