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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_PCSXX_DEFS_H__
29 #define __CVMX_PCSXX_DEFS_H__
30 
CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)31 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
32 {
33 	switch (cvmx_get_octeon_family()) {
34 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
35 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
36 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
37 		return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
38 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
39 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40 		return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
41 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
42 		return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
43 	}
44 	return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
45 }
46 
CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)47 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
48 {
49 	switch (cvmx_get_octeon_family()) {
50 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
51 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
52 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
53 		return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
54 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
55 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
56 		return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
57 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
58 		return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
59 	}
60 	return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
61 }
62 
CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)63 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
64 {
65 	switch (cvmx_get_octeon_family()) {
66 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
67 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
68 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
69 		return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
70 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
71 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
72 		return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
73 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
74 		return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
75 	}
76 	return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
77 }
78 
CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)79 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
80 {
81 	switch (cvmx_get_octeon_family()) {
82 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
83 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
84 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
85 		return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
86 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
87 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
88 		return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
89 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
90 		return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
91 	}
92 	return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
93 }
94 
CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)95 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
96 {
97 	switch (cvmx_get_octeon_family()) {
98 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
99 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
100 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
101 		return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
102 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
103 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
104 		return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
105 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
106 		return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
107 	}
108 	return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
109 }
110 
CVMX_PCSXX_INT_EN_REG(unsigned long block_id)111 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
112 {
113 	switch (cvmx_get_octeon_family()) {
114 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
115 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
116 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
117 		return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
118 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
119 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
120 		return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
121 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
122 		return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
123 	}
124 	return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
125 }
126 
CVMX_PCSXX_INT_REG(unsigned long block_id)127 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
128 {
129 	switch (cvmx_get_octeon_family()) {
130 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
131 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
132 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
133 		return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
134 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
135 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
136 		return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
137 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
138 		return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
139 	}
140 	return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
141 }
142 
CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)143 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
144 {
145 	switch (cvmx_get_octeon_family()) {
146 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
147 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
148 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
149 		return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
150 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
151 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
152 		return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
153 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
154 		return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
155 	}
156 	return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
157 }
158 
CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)159 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
160 {
161 	switch (cvmx_get_octeon_family()) {
162 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
163 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
164 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
165 		return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
166 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
167 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
168 		return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
169 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
170 		return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
171 	}
172 	return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
173 }
174 
CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)175 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
176 {
177 	switch (cvmx_get_octeon_family()) {
178 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
179 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
180 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
181 		return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
182 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
183 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
184 		return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
185 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
186 		return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
187 	}
188 	return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
189 }
190 
CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)191 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
192 {
193 	switch (cvmx_get_octeon_family()) {
194 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
195 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
196 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
197 		return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
198 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
199 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
200 		return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
201 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
202 		return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
203 	}
204 	return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
205 }
206 
CVMX_PCSXX_STATUS1_REG(unsigned long block_id)207 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
208 {
209 	switch (cvmx_get_octeon_family()) {
210 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
211 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
212 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
213 		return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
214 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
215 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
216 		return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
217 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
218 		return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
219 	}
220 	return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
221 }
222 
CVMX_PCSXX_STATUS2_REG(unsigned long block_id)223 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
224 {
225 	switch (cvmx_get_octeon_family()) {
226 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
227 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
228 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
229 		return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
230 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
231 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
232 		return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
233 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
234 		return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
235 	}
236 	return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
237 }
238 
CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)239 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
240 {
241 	switch (cvmx_get_octeon_family()) {
242 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
243 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
244 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
245 		return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
246 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
247 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
248 		return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
249 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
250 		return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
251 	}
252 	return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
253 }
254 
CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)255 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
256 {
257 	switch (cvmx_get_octeon_family()) {
258 	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
259 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
260 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
261 		return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
262 	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
263 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
264 		return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
265 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
266 		return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
267 	}
268 	return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
269 }
270 
271 union cvmx_pcsxx_10gbx_status_reg {
272 	uint64_t u64;
273 	struct cvmx_pcsxx_10gbx_status_reg_s {
274 #ifdef __BIG_ENDIAN_BITFIELD
275 		uint64_t reserved_13_63:51;
276 		uint64_t alignd:1;
277 		uint64_t pattst:1;
278 		uint64_t reserved_4_10:7;
279 		uint64_t l3sync:1;
280 		uint64_t l2sync:1;
281 		uint64_t l1sync:1;
282 		uint64_t l0sync:1;
283 #else
284 		uint64_t l0sync:1;
285 		uint64_t l1sync:1;
286 		uint64_t l2sync:1;
287 		uint64_t l3sync:1;
288 		uint64_t reserved_4_10:7;
289 		uint64_t pattst:1;
290 		uint64_t alignd:1;
291 		uint64_t reserved_13_63:51;
292 #endif
293 	} s;
294 	struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
295 	struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
296 	struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
297 	struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
298 	struct cvmx_pcsxx_10gbx_status_reg_s cn61xx;
299 	struct cvmx_pcsxx_10gbx_status_reg_s cn63xx;
300 	struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1;
301 	struct cvmx_pcsxx_10gbx_status_reg_s cn66xx;
302 	struct cvmx_pcsxx_10gbx_status_reg_s cn68xx;
303 	struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1;
304 };
305 
306 union cvmx_pcsxx_bist_status_reg {
307 	uint64_t u64;
308 	struct cvmx_pcsxx_bist_status_reg_s {
309 #ifdef __BIG_ENDIAN_BITFIELD
310 		uint64_t reserved_1_63:63;
311 		uint64_t bist_status:1;
312 #else
313 		uint64_t bist_status:1;
314 		uint64_t reserved_1_63:63;
315 #endif
316 	} s;
317 	struct cvmx_pcsxx_bist_status_reg_s cn52xx;
318 	struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
319 	struct cvmx_pcsxx_bist_status_reg_s cn56xx;
320 	struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
321 	struct cvmx_pcsxx_bist_status_reg_s cn61xx;
322 	struct cvmx_pcsxx_bist_status_reg_s cn63xx;
323 	struct cvmx_pcsxx_bist_status_reg_s cn63xxp1;
324 	struct cvmx_pcsxx_bist_status_reg_s cn66xx;
325 	struct cvmx_pcsxx_bist_status_reg_s cn68xx;
326 	struct cvmx_pcsxx_bist_status_reg_s cn68xxp1;
327 };
328 
329 union cvmx_pcsxx_bit_lock_status_reg {
330 	uint64_t u64;
331 	struct cvmx_pcsxx_bit_lock_status_reg_s {
332 #ifdef __BIG_ENDIAN_BITFIELD
333 		uint64_t reserved_4_63:60;
334 		uint64_t bitlck3:1;
335 		uint64_t bitlck2:1;
336 		uint64_t bitlck1:1;
337 		uint64_t bitlck0:1;
338 #else
339 		uint64_t bitlck0:1;
340 		uint64_t bitlck1:1;
341 		uint64_t bitlck2:1;
342 		uint64_t bitlck3:1;
343 		uint64_t reserved_4_63:60;
344 #endif
345 	} s;
346 	struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
347 	struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
348 	struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
349 	struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
350 	struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
351 	struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
352 	struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
353 	struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
354 	struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
355 	struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
356 };
357 
358 union cvmx_pcsxx_control1_reg {
359 	uint64_t u64;
360 	struct cvmx_pcsxx_control1_reg_s {
361 #ifdef __BIG_ENDIAN_BITFIELD
362 		uint64_t reserved_16_63:48;
363 		uint64_t reset:1;
364 		uint64_t loopbck1:1;
365 		uint64_t spdsel1:1;
366 		uint64_t reserved_12_12:1;
367 		uint64_t lo_pwr:1;
368 		uint64_t reserved_7_10:4;
369 		uint64_t spdsel0:1;
370 		uint64_t spd:4;
371 		uint64_t reserved_0_1:2;
372 #else
373 		uint64_t reserved_0_1:2;
374 		uint64_t spd:4;
375 		uint64_t spdsel0:1;
376 		uint64_t reserved_7_10:4;
377 		uint64_t lo_pwr:1;
378 		uint64_t reserved_12_12:1;
379 		uint64_t spdsel1:1;
380 		uint64_t loopbck1:1;
381 		uint64_t reset:1;
382 		uint64_t reserved_16_63:48;
383 #endif
384 	} s;
385 	struct cvmx_pcsxx_control1_reg_s cn52xx;
386 	struct cvmx_pcsxx_control1_reg_s cn52xxp1;
387 	struct cvmx_pcsxx_control1_reg_s cn56xx;
388 	struct cvmx_pcsxx_control1_reg_s cn56xxp1;
389 	struct cvmx_pcsxx_control1_reg_s cn61xx;
390 	struct cvmx_pcsxx_control1_reg_s cn63xx;
391 	struct cvmx_pcsxx_control1_reg_s cn63xxp1;
392 	struct cvmx_pcsxx_control1_reg_s cn66xx;
393 	struct cvmx_pcsxx_control1_reg_s cn68xx;
394 	struct cvmx_pcsxx_control1_reg_s cn68xxp1;
395 };
396 
397 union cvmx_pcsxx_control2_reg {
398 	uint64_t u64;
399 	struct cvmx_pcsxx_control2_reg_s {
400 #ifdef __BIG_ENDIAN_BITFIELD
401 		uint64_t reserved_2_63:62;
402 		uint64_t type:2;
403 #else
404 		uint64_t type:2;
405 		uint64_t reserved_2_63:62;
406 #endif
407 	} s;
408 	struct cvmx_pcsxx_control2_reg_s cn52xx;
409 	struct cvmx_pcsxx_control2_reg_s cn52xxp1;
410 	struct cvmx_pcsxx_control2_reg_s cn56xx;
411 	struct cvmx_pcsxx_control2_reg_s cn56xxp1;
412 	struct cvmx_pcsxx_control2_reg_s cn61xx;
413 	struct cvmx_pcsxx_control2_reg_s cn63xx;
414 	struct cvmx_pcsxx_control2_reg_s cn63xxp1;
415 	struct cvmx_pcsxx_control2_reg_s cn66xx;
416 	struct cvmx_pcsxx_control2_reg_s cn68xx;
417 	struct cvmx_pcsxx_control2_reg_s cn68xxp1;
418 };
419 
420 union cvmx_pcsxx_int_en_reg {
421 	uint64_t u64;
422 	struct cvmx_pcsxx_int_en_reg_s {
423 #ifdef __BIG_ENDIAN_BITFIELD
424 		uint64_t reserved_7_63:57;
425 		uint64_t dbg_sync_en:1;
426 		uint64_t algnlos_en:1;
427 		uint64_t synlos_en:1;
428 		uint64_t bitlckls_en:1;
429 		uint64_t rxsynbad_en:1;
430 		uint64_t rxbad_en:1;
431 		uint64_t txflt_en:1;
432 #else
433 		uint64_t txflt_en:1;
434 		uint64_t rxbad_en:1;
435 		uint64_t rxsynbad_en:1;
436 		uint64_t bitlckls_en:1;
437 		uint64_t synlos_en:1;
438 		uint64_t algnlos_en:1;
439 		uint64_t dbg_sync_en:1;
440 		uint64_t reserved_7_63:57;
441 #endif
442 	} s;
443 	struct cvmx_pcsxx_int_en_reg_cn52xx {
444 #ifdef __BIG_ENDIAN_BITFIELD
445 		uint64_t reserved_6_63:58;
446 		uint64_t algnlos_en:1;
447 		uint64_t synlos_en:1;
448 		uint64_t bitlckls_en:1;
449 		uint64_t rxsynbad_en:1;
450 		uint64_t rxbad_en:1;
451 		uint64_t txflt_en:1;
452 #else
453 		uint64_t txflt_en:1;
454 		uint64_t rxbad_en:1;
455 		uint64_t rxsynbad_en:1;
456 		uint64_t bitlckls_en:1;
457 		uint64_t synlos_en:1;
458 		uint64_t algnlos_en:1;
459 		uint64_t reserved_6_63:58;
460 #endif
461 	} cn52xx;
462 	struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1;
463 	struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx;
464 	struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1;
465 	struct cvmx_pcsxx_int_en_reg_s cn61xx;
466 	struct cvmx_pcsxx_int_en_reg_s cn63xx;
467 	struct cvmx_pcsxx_int_en_reg_s cn63xxp1;
468 	struct cvmx_pcsxx_int_en_reg_s cn66xx;
469 	struct cvmx_pcsxx_int_en_reg_s cn68xx;
470 	struct cvmx_pcsxx_int_en_reg_s cn68xxp1;
471 };
472 
473 union cvmx_pcsxx_int_reg {
474 	uint64_t u64;
475 	struct cvmx_pcsxx_int_reg_s {
476 #ifdef __BIG_ENDIAN_BITFIELD
477 		uint64_t reserved_7_63:57;
478 		uint64_t dbg_sync:1;
479 		uint64_t algnlos:1;
480 		uint64_t synlos:1;
481 		uint64_t bitlckls:1;
482 		uint64_t rxsynbad:1;
483 		uint64_t rxbad:1;
484 		uint64_t txflt:1;
485 #else
486 		uint64_t txflt:1;
487 		uint64_t rxbad:1;
488 		uint64_t rxsynbad:1;
489 		uint64_t bitlckls:1;
490 		uint64_t synlos:1;
491 		uint64_t algnlos:1;
492 		uint64_t dbg_sync:1;
493 		uint64_t reserved_7_63:57;
494 #endif
495 	} s;
496 	struct cvmx_pcsxx_int_reg_cn52xx {
497 #ifdef __BIG_ENDIAN_BITFIELD
498 		uint64_t reserved_6_63:58;
499 		uint64_t algnlos:1;
500 		uint64_t synlos:1;
501 		uint64_t bitlckls:1;
502 		uint64_t rxsynbad:1;
503 		uint64_t rxbad:1;
504 		uint64_t txflt:1;
505 #else
506 		uint64_t txflt:1;
507 		uint64_t rxbad:1;
508 		uint64_t rxsynbad:1;
509 		uint64_t bitlckls:1;
510 		uint64_t synlos:1;
511 		uint64_t algnlos:1;
512 		uint64_t reserved_6_63:58;
513 #endif
514 	} cn52xx;
515 	struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1;
516 	struct cvmx_pcsxx_int_reg_cn52xx cn56xx;
517 	struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1;
518 	struct cvmx_pcsxx_int_reg_s cn61xx;
519 	struct cvmx_pcsxx_int_reg_s cn63xx;
520 	struct cvmx_pcsxx_int_reg_s cn63xxp1;
521 	struct cvmx_pcsxx_int_reg_s cn66xx;
522 	struct cvmx_pcsxx_int_reg_s cn68xx;
523 	struct cvmx_pcsxx_int_reg_s cn68xxp1;
524 };
525 
526 union cvmx_pcsxx_log_anl_reg {
527 	uint64_t u64;
528 	struct cvmx_pcsxx_log_anl_reg_s {
529 #ifdef __BIG_ENDIAN_BITFIELD
530 		uint64_t reserved_7_63:57;
531 		uint64_t enc_mode:1;
532 		uint64_t drop_ln:2;
533 		uint64_t lafifovfl:1;
534 		uint64_t la_en:1;
535 		uint64_t pkt_sz:2;
536 #else
537 		uint64_t pkt_sz:2;
538 		uint64_t la_en:1;
539 		uint64_t lafifovfl:1;
540 		uint64_t drop_ln:2;
541 		uint64_t enc_mode:1;
542 		uint64_t reserved_7_63:57;
543 #endif
544 	} s;
545 	struct cvmx_pcsxx_log_anl_reg_s cn52xx;
546 	struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
547 	struct cvmx_pcsxx_log_anl_reg_s cn56xx;
548 	struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
549 	struct cvmx_pcsxx_log_anl_reg_s cn61xx;
550 	struct cvmx_pcsxx_log_anl_reg_s cn63xx;
551 	struct cvmx_pcsxx_log_anl_reg_s cn63xxp1;
552 	struct cvmx_pcsxx_log_anl_reg_s cn66xx;
553 	struct cvmx_pcsxx_log_anl_reg_s cn68xx;
554 	struct cvmx_pcsxx_log_anl_reg_s cn68xxp1;
555 };
556 
557 union cvmx_pcsxx_misc_ctl_reg {
558 	uint64_t u64;
559 	struct cvmx_pcsxx_misc_ctl_reg_s {
560 #ifdef __BIG_ENDIAN_BITFIELD
561 		uint64_t reserved_4_63:60;
562 		uint64_t tx_swap:1;
563 		uint64_t rx_swap:1;
564 		uint64_t xaui:1;
565 		uint64_t gmxeno:1;
566 #else
567 		uint64_t gmxeno:1;
568 		uint64_t xaui:1;
569 		uint64_t rx_swap:1;
570 		uint64_t tx_swap:1;
571 		uint64_t reserved_4_63:60;
572 #endif
573 	} s;
574 	struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
575 	struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
576 	struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
577 	struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
578 	struct cvmx_pcsxx_misc_ctl_reg_s cn61xx;
579 	struct cvmx_pcsxx_misc_ctl_reg_s cn63xx;
580 	struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1;
581 	struct cvmx_pcsxx_misc_ctl_reg_s cn66xx;
582 	struct cvmx_pcsxx_misc_ctl_reg_s cn68xx;
583 	struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1;
584 };
585 
586 union cvmx_pcsxx_rx_sync_states_reg {
587 	uint64_t u64;
588 	struct cvmx_pcsxx_rx_sync_states_reg_s {
589 #ifdef __BIG_ENDIAN_BITFIELD
590 		uint64_t reserved_16_63:48;
591 		uint64_t sync3st:4;
592 		uint64_t sync2st:4;
593 		uint64_t sync1st:4;
594 		uint64_t sync0st:4;
595 #else
596 		uint64_t sync0st:4;
597 		uint64_t sync1st:4;
598 		uint64_t sync2st:4;
599 		uint64_t sync3st:4;
600 		uint64_t reserved_16_63:48;
601 #endif
602 	} s;
603 	struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
604 	struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
605 	struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
606 	struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
607 	struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
608 	struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
609 	struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
610 	struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
611 	struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
612 	struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
613 };
614 
615 union cvmx_pcsxx_spd_abil_reg {
616 	uint64_t u64;
617 	struct cvmx_pcsxx_spd_abil_reg_s {
618 #ifdef __BIG_ENDIAN_BITFIELD
619 		uint64_t reserved_2_63:62;
620 		uint64_t tenpasst:1;
621 		uint64_t tengb:1;
622 #else
623 		uint64_t tengb:1;
624 		uint64_t tenpasst:1;
625 		uint64_t reserved_2_63:62;
626 #endif
627 	} s;
628 	struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
629 	struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
630 	struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
631 	struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
632 	struct cvmx_pcsxx_spd_abil_reg_s cn61xx;
633 	struct cvmx_pcsxx_spd_abil_reg_s cn63xx;
634 	struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1;
635 	struct cvmx_pcsxx_spd_abil_reg_s cn66xx;
636 	struct cvmx_pcsxx_spd_abil_reg_s cn68xx;
637 	struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1;
638 };
639 
640 union cvmx_pcsxx_status1_reg {
641 	uint64_t u64;
642 	struct cvmx_pcsxx_status1_reg_s {
643 #ifdef __BIG_ENDIAN_BITFIELD
644 		uint64_t reserved_8_63:56;
645 		uint64_t flt:1;
646 		uint64_t reserved_3_6:4;
647 		uint64_t rcv_lnk:1;
648 		uint64_t lpable:1;
649 		uint64_t reserved_0_0:1;
650 #else
651 		uint64_t reserved_0_0:1;
652 		uint64_t lpable:1;
653 		uint64_t rcv_lnk:1;
654 		uint64_t reserved_3_6:4;
655 		uint64_t flt:1;
656 		uint64_t reserved_8_63:56;
657 #endif
658 	} s;
659 	struct cvmx_pcsxx_status1_reg_s cn52xx;
660 	struct cvmx_pcsxx_status1_reg_s cn52xxp1;
661 	struct cvmx_pcsxx_status1_reg_s cn56xx;
662 	struct cvmx_pcsxx_status1_reg_s cn56xxp1;
663 	struct cvmx_pcsxx_status1_reg_s cn61xx;
664 	struct cvmx_pcsxx_status1_reg_s cn63xx;
665 	struct cvmx_pcsxx_status1_reg_s cn63xxp1;
666 	struct cvmx_pcsxx_status1_reg_s cn66xx;
667 	struct cvmx_pcsxx_status1_reg_s cn68xx;
668 	struct cvmx_pcsxx_status1_reg_s cn68xxp1;
669 };
670 
671 union cvmx_pcsxx_status2_reg {
672 	uint64_t u64;
673 	struct cvmx_pcsxx_status2_reg_s {
674 #ifdef __BIG_ENDIAN_BITFIELD
675 		uint64_t reserved_16_63:48;
676 		uint64_t dev:2;
677 		uint64_t reserved_12_13:2;
678 		uint64_t xmtflt:1;
679 		uint64_t rcvflt:1;
680 		uint64_t reserved_3_9:7;
681 		uint64_t tengb_w:1;
682 		uint64_t tengb_x:1;
683 		uint64_t tengb_r:1;
684 #else
685 		uint64_t tengb_r:1;
686 		uint64_t tengb_x:1;
687 		uint64_t tengb_w:1;
688 		uint64_t reserved_3_9:7;
689 		uint64_t rcvflt:1;
690 		uint64_t xmtflt:1;
691 		uint64_t reserved_12_13:2;
692 		uint64_t dev:2;
693 		uint64_t reserved_16_63:48;
694 #endif
695 	} s;
696 	struct cvmx_pcsxx_status2_reg_s cn52xx;
697 	struct cvmx_pcsxx_status2_reg_s cn52xxp1;
698 	struct cvmx_pcsxx_status2_reg_s cn56xx;
699 	struct cvmx_pcsxx_status2_reg_s cn56xxp1;
700 	struct cvmx_pcsxx_status2_reg_s cn61xx;
701 	struct cvmx_pcsxx_status2_reg_s cn63xx;
702 	struct cvmx_pcsxx_status2_reg_s cn63xxp1;
703 	struct cvmx_pcsxx_status2_reg_s cn66xx;
704 	struct cvmx_pcsxx_status2_reg_s cn68xx;
705 	struct cvmx_pcsxx_status2_reg_s cn68xxp1;
706 };
707 
708 union cvmx_pcsxx_tx_rx_polarity_reg {
709 	uint64_t u64;
710 	struct cvmx_pcsxx_tx_rx_polarity_reg_s {
711 #ifdef __BIG_ENDIAN_BITFIELD
712 		uint64_t reserved_10_63:54;
713 		uint64_t xor_rxplrt:4;
714 		uint64_t xor_txplrt:4;
715 		uint64_t rxplrt:1;
716 		uint64_t txplrt:1;
717 #else
718 		uint64_t txplrt:1;
719 		uint64_t rxplrt:1;
720 		uint64_t xor_txplrt:4;
721 		uint64_t xor_rxplrt:4;
722 		uint64_t reserved_10_63:54;
723 #endif
724 	} s;
725 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
726 	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
727 #ifdef __BIG_ENDIAN_BITFIELD
728 		uint64_t reserved_2_63:62;
729 		uint64_t rxplrt:1;
730 		uint64_t txplrt:1;
731 #else
732 		uint64_t txplrt:1;
733 		uint64_t rxplrt:1;
734 		uint64_t reserved_2_63:62;
735 #endif
736 	} cn52xxp1;
737 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
738 	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
739 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
740 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
741 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
742 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
743 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
744 	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
745 };
746 
747 union cvmx_pcsxx_tx_rx_states_reg {
748 	uint64_t u64;
749 	struct cvmx_pcsxx_tx_rx_states_reg_s {
750 #ifdef __BIG_ENDIAN_BITFIELD
751 		uint64_t reserved_14_63:50;
752 		uint64_t term_err:1;
753 		uint64_t syn3bad:1;
754 		uint64_t syn2bad:1;
755 		uint64_t syn1bad:1;
756 		uint64_t syn0bad:1;
757 		uint64_t rxbad:1;
758 		uint64_t algn_st:3;
759 		uint64_t rx_st:2;
760 		uint64_t tx_st:3;
761 #else
762 		uint64_t tx_st:3;
763 		uint64_t rx_st:2;
764 		uint64_t algn_st:3;
765 		uint64_t rxbad:1;
766 		uint64_t syn0bad:1;
767 		uint64_t syn1bad:1;
768 		uint64_t syn2bad:1;
769 		uint64_t syn3bad:1;
770 		uint64_t term_err:1;
771 		uint64_t reserved_14_63:50;
772 #endif
773 	} s;
774 	struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
775 	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
776 #ifdef __BIG_ENDIAN_BITFIELD
777 		uint64_t reserved_13_63:51;
778 		uint64_t syn3bad:1;
779 		uint64_t syn2bad:1;
780 		uint64_t syn1bad:1;
781 		uint64_t syn0bad:1;
782 		uint64_t rxbad:1;
783 		uint64_t algn_st:3;
784 		uint64_t rx_st:2;
785 		uint64_t tx_st:3;
786 #else
787 		uint64_t tx_st:3;
788 		uint64_t rx_st:2;
789 		uint64_t algn_st:3;
790 		uint64_t rxbad:1;
791 		uint64_t syn0bad:1;
792 		uint64_t syn1bad:1;
793 		uint64_t syn2bad:1;
794 		uint64_t syn3bad:1;
795 		uint64_t reserved_13_63:51;
796 #endif
797 	} cn52xxp1;
798 	struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
799 	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
800 	struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx;
801 	struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx;
802 	struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1;
803 	struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx;
804 	struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx;
805 	struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1;
806 };
807 
808 #endif
809