1 /*
2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/irqchip/mips-gic.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16 #include <linux/smp.h>
17 #include <linux/types.h>
18
19 #include <asm/bcache.h>
20 #include <asm/mips-cm.h>
21 #include <asm/mips-cpc.h>
22 #include <asm/mips_mt.h>
23 #include <asm/mipsregs.h>
24 #include <asm/pm-cps.h>
25 #include <asm/r4kcache.h>
26 #include <asm/smp-cps.h>
27 #include <asm/time.h>
28 #include <asm/uasm.h>
29
30 static bool threads_disabled;
31 static DECLARE_BITMAP(core_power, NR_CPUS);
32
33 struct core_boot_config *mips_cps_core_bootcfg;
34
setup_nothreads(char * s)35 static int __init setup_nothreads(char *s)
36 {
37 threads_disabled = true;
38 return 0;
39 }
40 early_param("nothreads", setup_nothreads);
41
core_vpe_count(unsigned core)42 static unsigned core_vpe_count(unsigned core)
43 {
44 unsigned cfg;
45
46 if (threads_disabled)
47 return 1;
48
49 if ((!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
50 && (!config_enabled(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
51 return 1;
52
53 mips_cm_lock_other(core, 0);
54 cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
55 mips_cm_unlock_other();
56 return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
57 }
58
cps_smp_setup(void)59 static void __init cps_smp_setup(void)
60 {
61 unsigned int ncores, nvpes, core_vpes;
62 unsigned long core_entry;
63 int c, v;
64
65 /* Detect & record VPE topology */
66 ncores = mips_cm_numcores();
67 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
68 for (c = nvpes = 0; c < ncores; c++) {
69 core_vpes = core_vpe_count(c);
70 pr_cont("%c%u", c ? ',' : '{', core_vpes);
71
72 /* Use the number of VPEs in core 0 for smp_num_siblings */
73 if (!c)
74 smp_num_siblings = core_vpes;
75
76 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
77 cpu_data[nvpes + v].core = c;
78 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
79 cpu_data[nvpes + v].vpe_id = v;
80 #endif
81 }
82
83 nvpes += core_vpes;
84 }
85 pr_cont("} total %u\n", nvpes);
86
87 /* Indicate present CPUs (CPU being synonymous with VPE) */
88 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
89 set_cpu_possible(v, true);
90 set_cpu_present(v, true);
91 __cpu_number_map[v] = v;
92 __cpu_logical_map[v] = v;
93 }
94
95 /* Set a coherent default CCA (CWB) */
96 change_c0_config(CONF_CM_CMASK, 0x5);
97
98 /* Core 0 is powered up (we're running on it) */
99 bitmap_set(core_power, 0, 1);
100
101 /* Initialise core 0 */
102 mips_cps_core_init();
103
104 /* Make core 0 coherent with everything */
105 write_gcr_cl_coherence(0xff);
106
107 if (mips_cm_revision() >= CM_REV_CM3) {
108 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
109 write_gcr_bev_base(core_entry);
110 }
111
112 #ifdef CONFIG_MIPS_MT_FPAFF
113 /* If we have an FPU, enroll ourselves in the FPU-full mask */
114 if (cpu_has_fpu)
115 cpumask_set_cpu(0, &mt_fpu_cpumask);
116 #endif /* CONFIG_MIPS_MT_FPAFF */
117 }
118
cps_prepare_cpus(unsigned int max_cpus)119 static void __init cps_prepare_cpus(unsigned int max_cpus)
120 {
121 unsigned ncores, core_vpes, c, cca;
122 bool cca_unsuitable;
123 u32 *entry_code;
124
125 mips_mt_set_cpuoptions();
126
127 /* Detect whether the CCA is unsuited to multi-core SMP */
128 cca = read_c0_config() & CONF_CM_CMASK;
129 switch (cca) {
130 case 0x4: /* CWBE */
131 case 0x5: /* CWB */
132 /* The CCA is coherent, multi-core is fine */
133 cca_unsuitable = false;
134 break;
135
136 default:
137 /* CCA is not coherent, multi-core is not usable */
138 cca_unsuitable = true;
139 }
140
141 /* Warn the user if the CCA prevents multi-core */
142 ncores = mips_cm_numcores();
143 if ((cca_unsuitable || cpu_has_dc_aliases) && ncores > 1) {
144 pr_warn("Using only one core due to %s%s%s\n",
145 cca_unsuitable ? "unsuitable CCA" : "",
146 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
147 cpu_has_dc_aliases ? "dcache aliasing" : "");
148
149 for_each_present_cpu(c) {
150 if (cpu_data[c].core)
151 set_cpu_present(c, false);
152 }
153 }
154
155 /*
156 * Patch the start of mips_cps_core_entry to provide:
157 *
158 * s0 = kseg0 CCA
159 */
160 entry_code = (u32 *)&mips_cps_core_entry;
161 uasm_i_addiu(&entry_code, 16, 0, cca);
162 blast_dcache_range((unsigned long)&mips_cps_core_entry,
163 (unsigned long)entry_code);
164 bc_wback_inv((unsigned long)&mips_cps_core_entry,
165 (void *)entry_code - (void *)&mips_cps_core_entry);
166 __sync();
167
168 /* Allocate core boot configuration structs */
169 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
170 GFP_KERNEL);
171 if (!mips_cps_core_bootcfg) {
172 pr_err("Failed to allocate boot config for %u cores\n", ncores);
173 goto err_out;
174 }
175
176 /* Allocate VPE boot configuration structs */
177 for (c = 0; c < ncores; c++) {
178 core_vpes = core_vpe_count(c);
179 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
180 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
181 GFP_KERNEL);
182 if (!mips_cps_core_bootcfg[c].vpe_config) {
183 pr_err("Failed to allocate %u VPE boot configs\n",
184 core_vpes);
185 goto err_out;
186 }
187 }
188
189 /* Mark this CPU as booted */
190 atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
191 1 << cpu_vpe_id(¤t_cpu_data));
192
193 return;
194 err_out:
195 /* Clean up allocations */
196 if (mips_cps_core_bootcfg) {
197 for (c = 0; c < ncores; c++)
198 kfree(mips_cps_core_bootcfg[c].vpe_config);
199 kfree(mips_cps_core_bootcfg);
200 mips_cps_core_bootcfg = NULL;
201 }
202
203 /* Effectively disable SMP by declaring CPUs not present */
204 for_each_possible_cpu(c) {
205 if (c == 0)
206 continue;
207 set_cpu_present(c, false);
208 }
209 }
210
boot_core(unsigned core)211 static void boot_core(unsigned core)
212 {
213 u32 access, stat, seq_state;
214 unsigned timeout;
215
216 /* Select the appropriate core */
217 mips_cm_lock_other(core, 0);
218
219 /* Set its reset vector */
220 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
221
222 /* Ensure its coherency is disabled */
223 write_gcr_co_coherence(0);
224
225 /* Ensure the core can access the GCRs */
226 access = read_gcr_access();
227 access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
228 write_gcr_access(access);
229
230 if (mips_cpc_present()) {
231 /* Reset the core */
232 mips_cpc_lock_other(core);
233
234 if (mips_cm_revision() >= CM_REV_CM3) {
235 /* Run VP0 following the reset */
236 write_cpc_co_vp_run(0x1);
237
238 /*
239 * Ensure that the VP_RUN register is written before the
240 * core leaves reset.
241 */
242 wmb();
243 }
244
245 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
246
247 timeout = 100;
248 while (true) {
249 stat = read_cpc_co_stat_conf();
250 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
251
252 /* U6 == coherent execution, ie. the core is up */
253 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
254 break;
255
256 /* Delay a little while before we start warning */
257 if (timeout) {
258 timeout--;
259 mdelay(10);
260 continue;
261 }
262
263 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
264 core, stat);
265 mdelay(1000);
266 }
267
268 mips_cpc_unlock_other();
269 } else {
270 /* Take the core out of reset */
271 write_gcr_co_reset_release(0);
272 }
273
274 mips_cm_unlock_other();
275
276 /* The core is now powered up */
277 bitmap_set(core_power, core, 1);
278 }
279
remote_vpe_boot(void * dummy)280 static void remote_vpe_boot(void *dummy)
281 {
282 unsigned core = current_cpu_data.core;
283 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
284
285 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data));
286 }
287
cps_boot_secondary(int cpu,struct task_struct * idle)288 static void cps_boot_secondary(int cpu, struct task_struct *idle)
289 {
290 unsigned core = cpu_data[cpu].core;
291 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
292 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
293 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
294 unsigned long core_entry;
295 unsigned int remote;
296 int err;
297
298 vpe_cfg->pc = (unsigned long)&smp_bootstrap;
299 vpe_cfg->sp = __KSTK_TOS(idle);
300 vpe_cfg->gp = (unsigned long)task_thread_info(idle);
301
302 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
303
304 preempt_disable();
305
306 if (!test_bit(core, core_power)) {
307 /* Boot a VPE on a powered down core */
308 boot_core(core);
309 goto out;
310 }
311
312 if (cpu_has_vp) {
313 mips_cm_lock_other(core, vpe_id);
314 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
315 write_gcr_co_reset_base(core_entry);
316 mips_cm_unlock_other();
317 }
318
319 if (core != current_cpu_data.core) {
320 /* Boot a VPE on another powered up core */
321 for (remote = 0; remote < NR_CPUS; remote++) {
322 if (cpu_data[remote].core != core)
323 continue;
324 if (cpu_online(remote))
325 break;
326 }
327 BUG_ON(remote >= NR_CPUS);
328
329 err = smp_call_function_single(remote, remote_vpe_boot,
330 NULL, 1);
331 if (err)
332 panic("Failed to call remote CPU\n");
333 goto out;
334 }
335
336 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
337
338 /* Boot a VPE on this core */
339 mips_cps_boot_vpes(core_cfg, vpe_id);
340 out:
341 preempt_enable();
342 }
343
cps_init_secondary(void)344 static void cps_init_secondary(void)
345 {
346 /* Disable MT - we only want to run 1 TC per VPE */
347 if (cpu_has_mipsmt)
348 dmt();
349
350 if (mips_cm_revision() >= CM_REV_CM3) {
351 unsigned ident = gic_read_local_vp_id();
352
353 /*
354 * Ensure that our calculation of the VP ID matches up with
355 * what the GIC reports, otherwise we'll have configured
356 * interrupts incorrectly.
357 */
358 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
359 }
360
361 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
362 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
363 }
364
cps_smp_finish(void)365 static void cps_smp_finish(void)
366 {
367 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
368
369 #ifdef CONFIG_MIPS_MT_FPAFF
370 /* If we have an FPU, enroll ourselves in the FPU-full mask */
371 if (cpu_has_fpu)
372 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
373 #endif /* CONFIG_MIPS_MT_FPAFF */
374
375 local_irq_enable();
376 }
377
378 #ifdef CONFIG_HOTPLUG_CPU
379
cps_cpu_disable(void)380 static int cps_cpu_disable(void)
381 {
382 unsigned cpu = smp_processor_id();
383 struct core_boot_config *core_cfg;
384
385 if (!cpu)
386 return -EBUSY;
387
388 if (!cps_pm_support_state(CPS_PM_POWER_GATED))
389 return -EINVAL;
390
391 core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
392 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
393 smp_mb__after_atomic();
394 set_cpu_online(cpu, false);
395 calculate_cpu_foreign_map();
396 cpumask_clear_cpu(cpu, &cpu_callin_map);
397
398 return 0;
399 }
400
401 static DECLARE_COMPLETION(cpu_death_chosen);
402 static unsigned cpu_death_sibling;
403 static enum {
404 CPU_DEATH_HALT,
405 CPU_DEATH_POWER,
406 } cpu_death;
407
play_dead(void)408 void play_dead(void)
409 {
410 unsigned int cpu, core, vpe_id;
411
412 local_irq_disable();
413 idle_task_exit();
414 cpu = smp_processor_id();
415 cpu_death = CPU_DEATH_POWER;
416
417 pr_debug("CPU%d going offline\n", cpu);
418
419 if (cpu_has_mipsmt || cpu_has_vp) {
420 core = cpu_data[cpu].core;
421
422 /* Look for another online VPE within the core */
423 for_each_online_cpu(cpu_death_sibling) {
424 if (cpu_data[cpu_death_sibling].core != core)
425 continue;
426
427 /*
428 * There is an online VPE within the core. Just halt
429 * this TC and leave the core alone.
430 */
431 cpu_death = CPU_DEATH_HALT;
432 break;
433 }
434 }
435
436 /* This CPU has chosen its way out */
437 complete(&cpu_death_chosen);
438
439 if (cpu_death == CPU_DEATH_HALT) {
440 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
441
442 pr_debug("Halting core %d VP%d\n", core, vpe_id);
443 if (cpu_has_mipsmt) {
444 /* Halt this TC */
445 write_c0_tchalt(TCHALT_H);
446 instruction_hazard();
447 } else if (cpu_has_vp) {
448 write_cpc_cl_vp_stop(1 << vpe_id);
449
450 /* Ensure that the VP_STOP register is written */
451 wmb();
452 }
453 } else {
454 pr_debug("Gating power to core %d\n", core);
455 /* Power down the core */
456 cps_pm_enter_state(CPS_PM_POWER_GATED);
457 }
458
459 /* This should never be reached */
460 panic("Failed to offline CPU %u", cpu);
461 }
462
wait_for_sibling_halt(void * ptr_cpu)463 static void wait_for_sibling_halt(void *ptr_cpu)
464 {
465 unsigned cpu = (unsigned long)ptr_cpu;
466 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
467 unsigned halted;
468 unsigned long flags;
469
470 do {
471 local_irq_save(flags);
472 settc(vpe_id);
473 halted = read_tc_c0_tchalt();
474 local_irq_restore(flags);
475 } while (!(halted & TCHALT_H));
476 }
477
cps_cpu_die(unsigned int cpu)478 static void cps_cpu_die(unsigned int cpu)
479 {
480 unsigned core = cpu_data[cpu].core;
481 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
482 ktime_t fail_time;
483 unsigned stat;
484 int err;
485
486 /* Wait for the cpu to choose its way out */
487 if (!wait_for_completion_timeout(&cpu_death_chosen,
488 msecs_to_jiffies(5000))) {
489 pr_err("CPU%u: didn't offline\n", cpu);
490 return;
491 }
492
493 /*
494 * Now wait for the CPU to actually offline. Without doing this that
495 * offlining may race with one or more of:
496 *
497 * - Onlining the CPU again.
498 * - Powering down the core if another VPE within it is offlined.
499 * - A sibling VPE entering a non-coherent state.
500 *
501 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
502 * with which we could race, so do nothing.
503 */
504 if (cpu_death == CPU_DEATH_POWER) {
505 /*
506 * Wait for the core to enter a powered down or clock gated
507 * state, the latter happening when a JTAG probe is connected
508 * in which case the CPC will refuse to power down the core.
509 */
510 fail_time = ktime_add_ms(ktime_get(), 2000);
511 do {
512 mips_cm_lock_other(core, 0);
513 mips_cpc_lock_other(core);
514 stat = read_cpc_co_stat_conf();
515 stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
516 mips_cpc_unlock_other();
517 mips_cm_unlock_other();
518
519 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
520 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
521 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
522 break;
523
524 /*
525 * The core ought to have powered down, but didn't &
526 * now we don't really know what state it's in. It's
527 * likely that its _pwr_up pin has been wired to logic
528 * 1 & it powered back up as soon as we powered it
529 * down...
530 *
531 * The best we can do is warn the user & continue in
532 * the hope that the core is doing nothing harmful &
533 * might behave properly if we online it later.
534 */
535 if (WARN(ktime_after(ktime_get(), fail_time),
536 "CPU%u hasn't powered down, seq. state %u\n",
537 cpu, stat >> CPC_Cx_STAT_CONF_SEQSTATE_SHF))
538 break;
539 } while (1);
540
541 /* Indicate the core is powered off */
542 bitmap_clear(core_power, core, 1);
543 } else if (cpu_has_mipsmt) {
544 /*
545 * Have a CPU with access to the offlined CPUs registers wait
546 * for its TC to halt.
547 */
548 err = smp_call_function_single(cpu_death_sibling,
549 wait_for_sibling_halt,
550 (void *)(unsigned long)cpu, 1);
551 if (err)
552 panic("Failed to call remote sibling CPU\n");
553 } else if (cpu_has_vp) {
554 do {
555 mips_cm_lock_other(core, vpe_id);
556 stat = read_cpc_co_vp_running();
557 mips_cm_unlock_other();
558 } while (stat & (1 << vpe_id));
559 }
560 }
561
562 #endif /* CONFIG_HOTPLUG_CPU */
563
564 static struct plat_smp_ops cps_smp_ops = {
565 .smp_setup = cps_smp_setup,
566 .prepare_cpus = cps_prepare_cpus,
567 .boot_secondary = cps_boot_secondary,
568 .init_secondary = cps_init_secondary,
569 .smp_finish = cps_smp_finish,
570 .send_ipi_single = gic_send_ipi_single,
571 .send_ipi_mask = gic_send_ipi_mask,
572 #ifdef CONFIG_HOTPLUG_CPU
573 .cpu_disable = cps_cpu_disable,
574 .cpu_die = cps_cpu_die,
575 #endif
576 };
577
mips_cps_smp_in_use(void)578 bool mips_cps_smp_in_use(void)
579 {
580 extern struct plat_smp_ops *mp_ops;
581 return mp_ops == &cps_smp_ops;
582 }
583
register_cps_smp_ops(void)584 int register_cps_smp_ops(void)
585 {
586 if (!mips_cm_present()) {
587 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
588 return -ENODEV;
589 }
590
591 /* check we have a GIC - we need one for IPIs */
592 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
593 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
594 return -ENODEV;
595 }
596
597 register_smp_ops(&cps_smp_ops);
598 return 0;
599 }
600