1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/kdebug.h>
15 #include <linux/module.h>
16 #include <linux/vmalloc.h>
17 #include <linux/fs.h>
18 #include <linux/bootmem.h>
19 #include <asm/fpu.h>
20 #include <asm/page.h>
21 #include <asm/cacheflush.h>
22 #include <asm/mmu_context.h>
23 #include <asm/pgtable.h>
24
25 #include <linux/kvm_host.h>
26
27 #include "interrupt.h"
28 #include "commpage.h"
29
30 #define CREATE_TRACE_POINTS
31 #include "trace.h"
32
33 #ifndef VECTORSPACING
34 #define VECTORSPACING 0x100 /* for EI/VI mode */
35 #endif
36
37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
38 struct kvm_stats_debugfs_item debugfs_entries[] = {
39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
58 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
59 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
60 {NULL}
61 };
62
kvm_mips_reset_vcpu(struct kvm_vcpu * vcpu)63 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
64 {
65 int i;
66
67 for_each_possible_cpu(i) {
68 vcpu->arch.guest_kernel_asid[i] = 0;
69 vcpu->arch.guest_user_asid[i] = 0;
70 }
71
72 return 0;
73 }
74
75 /*
76 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
77 * Config7, so we are "runnable" if interrupts are pending
78 */
kvm_arch_vcpu_runnable(struct kvm_vcpu * vcpu)79 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
80 {
81 return !!(vcpu->arch.pending_exceptions);
82 }
83
kvm_arch_vcpu_should_kick(struct kvm_vcpu * vcpu)84 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
85 {
86 return 1;
87 }
88
kvm_arch_hardware_enable(void)89 int kvm_arch_hardware_enable(void)
90 {
91 return 0;
92 }
93
kvm_arch_hardware_setup(void)94 int kvm_arch_hardware_setup(void)
95 {
96 return 0;
97 }
98
kvm_arch_check_processor_compat(void * rtn)99 void kvm_arch_check_processor_compat(void *rtn)
100 {
101 *(int *)rtn = 0;
102 }
103
kvm_mips_init_tlbs(struct kvm * kvm)104 static void kvm_mips_init_tlbs(struct kvm *kvm)
105 {
106 unsigned long wired;
107
108 /*
109 * Add a wired entry to the TLB, it is used to map the commpage to
110 * the Guest kernel
111 */
112 wired = read_c0_wired();
113 write_c0_wired(wired + 1);
114 mtc0_tlbw_hazard();
115 kvm->arch.commpage_tlb = wired;
116
117 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
118 kvm->arch.commpage_tlb);
119 }
120
kvm_mips_init_vm_percpu(void * arg)121 static void kvm_mips_init_vm_percpu(void *arg)
122 {
123 struct kvm *kvm = (struct kvm *)arg;
124
125 kvm_mips_init_tlbs(kvm);
126 kvm_mips_callbacks->vm_init(kvm);
127
128 }
129
kvm_arch_init_vm(struct kvm * kvm,unsigned long type)130 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
131 {
132 if (atomic_inc_return(&kvm_mips_instance) == 1) {
133 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
134 __func__);
135 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
136 }
137
138 return 0;
139 }
140
kvm_mips_free_vcpus(struct kvm * kvm)141 void kvm_mips_free_vcpus(struct kvm *kvm)
142 {
143 unsigned int i;
144 struct kvm_vcpu *vcpu;
145
146 /* Put the pages we reserved for the guest pmap */
147 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
148 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
149 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
150 }
151 kfree(kvm->arch.guest_pmap);
152
153 kvm_for_each_vcpu(i, vcpu, kvm) {
154 kvm_arch_vcpu_free(vcpu);
155 }
156
157 mutex_lock(&kvm->lock);
158
159 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
160 kvm->vcpus[i] = NULL;
161
162 atomic_set(&kvm->online_vcpus, 0);
163
164 mutex_unlock(&kvm->lock);
165 }
166
kvm_mips_uninit_tlbs(void * arg)167 static void kvm_mips_uninit_tlbs(void *arg)
168 {
169 /* Restore wired count */
170 write_c0_wired(0);
171 mtc0_tlbw_hazard();
172 /* Clear out all the TLBs */
173 kvm_local_flush_tlb_all();
174 }
175
kvm_arch_destroy_vm(struct kvm * kvm)176 void kvm_arch_destroy_vm(struct kvm *kvm)
177 {
178 kvm_mips_free_vcpus(kvm);
179
180 /* If this is the last instance, restore wired count */
181 if (atomic_dec_return(&kvm_mips_instance) == 0) {
182 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
183 __func__);
184 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
185 }
186 }
187
kvm_arch_dev_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)188 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
189 unsigned long arg)
190 {
191 return -ENOIOCTLCMD;
192 }
193
kvm_arch_create_memslot(struct kvm * kvm,struct kvm_memory_slot * slot,unsigned long npages)194 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
195 unsigned long npages)
196 {
197 return 0;
198 }
199
kvm_arch_prepare_memory_region(struct kvm * kvm,struct kvm_memory_slot * memslot,const struct kvm_userspace_memory_region * mem,enum kvm_mr_change change)200 int kvm_arch_prepare_memory_region(struct kvm *kvm,
201 struct kvm_memory_slot *memslot,
202 const struct kvm_userspace_memory_region *mem,
203 enum kvm_mr_change change)
204 {
205 return 0;
206 }
207
kvm_arch_commit_memory_region(struct kvm * kvm,const struct kvm_userspace_memory_region * mem,const struct kvm_memory_slot * old,const struct kvm_memory_slot * new,enum kvm_mr_change change)208 void kvm_arch_commit_memory_region(struct kvm *kvm,
209 const struct kvm_userspace_memory_region *mem,
210 const struct kvm_memory_slot *old,
211 const struct kvm_memory_slot *new,
212 enum kvm_mr_change change)
213 {
214 unsigned long npages = 0;
215 int i;
216
217 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
218 __func__, kvm, mem->slot, mem->guest_phys_addr,
219 mem->memory_size, mem->userspace_addr);
220
221 /* Setup Guest PMAP table */
222 if (!kvm->arch.guest_pmap) {
223 if (mem->slot == 0)
224 npages = mem->memory_size >> PAGE_SHIFT;
225
226 if (npages) {
227 kvm->arch.guest_pmap_npages = npages;
228 kvm->arch.guest_pmap =
229 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
230
231 if (!kvm->arch.guest_pmap) {
232 kvm_err("Failed to allocate guest PMAP");
233 return;
234 }
235
236 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
237 npages, kvm->arch.guest_pmap);
238
239 /* Now setup the page table */
240 for (i = 0; i < npages; i++)
241 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
242 }
243 }
244 }
245
kvm_arch_vcpu_create(struct kvm * kvm,unsigned int id)246 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
247 {
248 int err, size, offset;
249 void *gebase;
250 int i;
251
252 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
253
254 if (!vcpu) {
255 err = -ENOMEM;
256 goto out;
257 }
258
259 err = kvm_vcpu_init(vcpu, kvm, id);
260
261 if (err)
262 goto out_free_cpu;
263
264 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
265
266 /*
267 * Allocate space for host mode exception handlers that handle
268 * guest mode exits
269 */
270 if (cpu_has_veic || cpu_has_vint)
271 size = 0x200 + VECTORSPACING * 64;
272 else
273 size = 0x4000;
274
275 /* Save Linux EBASE */
276 vcpu->arch.host_ebase = (void *)read_c0_ebase();
277
278 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
279
280 if (!gebase) {
281 err = -ENOMEM;
282 goto out_uninit_cpu;
283 }
284 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
285 ALIGN(size, PAGE_SIZE), gebase);
286
287 /* Save new ebase */
288 vcpu->arch.guest_ebase = gebase;
289
290 /* Copy L1 Guest Exception handler to correct offset */
291
292 /* TLB Refill, EXL = 0 */
293 memcpy(gebase, mips32_exception,
294 mips32_exceptionEnd - mips32_exception);
295
296 /* General Exception Entry point */
297 memcpy(gebase + 0x180, mips32_exception,
298 mips32_exceptionEnd - mips32_exception);
299
300 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
301 for (i = 0; i < 8; i++) {
302 kvm_debug("L1 Vectored handler @ %p\n",
303 gebase + 0x200 + (i * VECTORSPACING));
304 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
305 mips32_exceptionEnd - mips32_exception);
306 }
307
308 /* General handler, relocate to unmapped space for sanity's sake */
309 offset = 0x2000;
310 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
311 gebase + offset,
312 mips32_GuestExceptionEnd - mips32_GuestException);
313
314 memcpy(gebase + offset, mips32_GuestException,
315 mips32_GuestExceptionEnd - mips32_GuestException);
316
317 #ifdef MODULE
318 offset += mips32_GuestExceptionEnd - mips32_GuestException;
319 memcpy(gebase + offset, (char *)__kvm_mips_vcpu_run,
320 __kvm_mips_vcpu_run_end - (char *)__kvm_mips_vcpu_run);
321 vcpu->arch.vcpu_run = gebase + offset;
322 #else
323 vcpu->arch.vcpu_run = __kvm_mips_vcpu_run;
324 #endif
325
326 /* Invalidate the icache for these ranges */
327 flush_icache_range((unsigned long)gebase,
328 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
329
330 /*
331 * Allocate comm page for guest kernel, a TLB will be reserved for
332 * mapping GVA @ 0xFFFF8000 to this page
333 */
334 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
335
336 if (!vcpu->arch.kseg0_commpage) {
337 err = -ENOMEM;
338 goto out_free_gebase;
339 }
340
341 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
342 kvm_mips_commpage_init(vcpu);
343
344 /* Init */
345 vcpu->arch.last_sched_cpu = -1;
346
347 /* Start off the timer */
348 kvm_mips_init_count(vcpu);
349
350 return vcpu;
351
352 out_free_gebase:
353 kfree(gebase);
354
355 out_uninit_cpu:
356 kvm_vcpu_uninit(vcpu);
357
358 out_free_cpu:
359 kfree(vcpu);
360
361 out:
362 return ERR_PTR(err);
363 }
364
kvm_arch_vcpu_free(struct kvm_vcpu * vcpu)365 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
366 {
367 hrtimer_cancel(&vcpu->arch.comparecount_timer);
368
369 kvm_vcpu_uninit(vcpu);
370
371 kvm_mips_dump_stats(vcpu);
372
373 kfree(vcpu->arch.guest_ebase);
374 kfree(vcpu->arch.kseg0_commpage);
375 kfree(vcpu);
376 }
377
kvm_arch_vcpu_destroy(struct kvm_vcpu * vcpu)378 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
379 {
380 kvm_arch_vcpu_free(vcpu);
381 }
382
kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu * vcpu,struct kvm_guest_debug * dbg)383 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
384 struct kvm_guest_debug *dbg)
385 {
386 return -ENOIOCTLCMD;
387 }
388
kvm_arch_vcpu_ioctl_run(struct kvm_vcpu * vcpu,struct kvm_run * run)389 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
390 {
391 int r = 0;
392 sigset_t sigsaved;
393
394 if (vcpu->sigset_active)
395 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
396
397 if (vcpu->mmio_needed) {
398 if (!vcpu->mmio_is_write)
399 kvm_mips_complete_mmio_load(vcpu, run);
400 vcpu->mmio_needed = 0;
401 }
402
403 lose_fpu(1);
404
405 local_irq_disable();
406 /* Check if we have any exceptions/interrupts pending */
407 kvm_mips_deliver_interrupts(vcpu,
408 kvm_read_c0_guest_cause(vcpu->arch.cop0));
409
410 __kvm_guest_enter();
411
412 /* Disable hardware page table walking while in guest */
413 htw_stop();
414
415 r = vcpu->arch.vcpu_run(run, vcpu);
416
417 /* Re-enable HTW before enabling interrupts */
418 htw_start();
419
420 __kvm_guest_exit();
421 local_irq_enable();
422
423 if (vcpu->sigset_active)
424 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
425
426 return r;
427 }
428
kvm_vcpu_ioctl_interrupt(struct kvm_vcpu * vcpu,struct kvm_mips_interrupt * irq)429 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
430 struct kvm_mips_interrupt *irq)
431 {
432 int intr = (int)irq->irq;
433 struct kvm_vcpu *dvcpu = NULL;
434
435 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
436 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
437 (int)intr);
438
439 if (irq->cpu == -1)
440 dvcpu = vcpu;
441 else
442 dvcpu = vcpu->kvm->vcpus[irq->cpu];
443
444 if (intr == 2 || intr == 3 || intr == 4) {
445 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
446
447 } else if (intr == -2 || intr == -3 || intr == -4) {
448 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
449 } else {
450 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
451 irq->cpu, irq->irq);
452 return -EINVAL;
453 }
454
455 dvcpu->arch.wait = 0;
456
457 if (waitqueue_active(&dvcpu->wq))
458 wake_up_interruptible(&dvcpu->wq);
459
460 return 0;
461 }
462
kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu * vcpu,struct kvm_mp_state * mp_state)463 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
464 struct kvm_mp_state *mp_state)
465 {
466 return -ENOIOCTLCMD;
467 }
468
kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu * vcpu,struct kvm_mp_state * mp_state)469 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
470 struct kvm_mp_state *mp_state)
471 {
472 return -ENOIOCTLCMD;
473 }
474
475 static u64 kvm_mips_get_one_regs[] = {
476 KVM_REG_MIPS_R0,
477 KVM_REG_MIPS_R1,
478 KVM_REG_MIPS_R2,
479 KVM_REG_MIPS_R3,
480 KVM_REG_MIPS_R4,
481 KVM_REG_MIPS_R5,
482 KVM_REG_MIPS_R6,
483 KVM_REG_MIPS_R7,
484 KVM_REG_MIPS_R8,
485 KVM_REG_MIPS_R9,
486 KVM_REG_MIPS_R10,
487 KVM_REG_MIPS_R11,
488 KVM_REG_MIPS_R12,
489 KVM_REG_MIPS_R13,
490 KVM_REG_MIPS_R14,
491 KVM_REG_MIPS_R15,
492 KVM_REG_MIPS_R16,
493 KVM_REG_MIPS_R17,
494 KVM_REG_MIPS_R18,
495 KVM_REG_MIPS_R19,
496 KVM_REG_MIPS_R20,
497 KVM_REG_MIPS_R21,
498 KVM_REG_MIPS_R22,
499 KVM_REG_MIPS_R23,
500 KVM_REG_MIPS_R24,
501 KVM_REG_MIPS_R25,
502 KVM_REG_MIPS_R26,
503 KVM_REG_MIPS_R27,
504 KVM_REG_MIPS_R28,
505 KVM_REG_MIPS_R29,
506 KVM_REG_MIPS_R30,
507 KVM_REG_MIPS_R31,
508
509 KVM_REG_MIPS_HI,
510 KVM_REG_MIPS_LO,
511 KVM_REG_MIPS_PC,
512
513 KVM_REG_MIPS_CP0_INDEX,
514 KVM_REG_MIPS_CP0_CONTEXT,
515 KVM_REG_MIPS_CP0_USERLOCAL,
516 KVM_REG_MIPS_CP0_PAGEMASK,
517 KVM_REG_MIPS_CP0_WIRED,
518 KVM_REG_MIPS_CP0_HWRENA,
519 KVM_REG_MIPS_CP0_BADVADDR,
520 KVM_REG_MIPS_CP0_COUNT,
521 KVM_REG_MIPS_CP0_ENTRYHI,
522 KVM_REG_MIPS_CP0_COMPARE,
523 KVM_REG_MIPS_CP0_STATUS,
524 KVM_REG_MIPS_CP0_CAUSE,
525 KVM_REG_MIPS_CP0_EPC,
526 KVM_REG_MIPS_CP0_PRID,
527 KVM_REG_MIPS_CP0_CONFIG,
528 KVM_REG_MIPS_CP0_CONFIG1,
529 KVM_REG_MIPS_CP0_CONFIG2,
530 KVM_REG_MIPS_CP0_CONFIG3,
531 KVM_REG_MIPS_CP0_CONFIG4,
532 KVM_REG_MIPS_CP0_CONFIG5,
533 KVM_REG_MIPS_CP0_CONFIG7,
534 KVM_REG_MIPS_CP0_ERROREPC,
535
536 KVM_REG_MIPS_COUNT_CTL,
537 KVM_REG_MIPS_COUNT_RESUME,
538 KVM_REG_MIPS_COUNT_HZ,
539 };
540
kvm_mips_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)541 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
542 const struct kvm_one_reg *reg)
543 {
544 struct mips_coproc *cop0 = vcpu->arch.cop0;
545 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
546 int ret;
547 s64 v;
548 s64 vs[2];
549 unsigned int idx;
550
551 switch (reg->id) {
552 /* General purpose registers */
553 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
554 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
555 break;
556 case KVM_REG_MIPS_HI:
557 v = (long)vcpu->arch.hi;
558 break;
559 case KVM_REG_MIPS_LO:
560 v = (long)vcpu->arch.lo;
561 break;
562 case KVM_REG_MIPS_PC:
563 v = (long)vcpu->arch.pc;
564 break;
565
566 /* Floating point registers */
567 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
568 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
569 return -EINVAL;
570 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
571 /* Odd singles in top of even double when FR=0 */
572 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
573 v = get_fpr32(&fpu->fpr[idx], 0);
574 else
575 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
576 break;
577 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
578 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
579 return -EINVAL;
580 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
581 /* Can't access odd doubles in FR=0 mode */
582 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
583 return -EINVAL;
584 v = get_fpr64(&fpu->fpr[idx], 0);
585 break;
586 case KVM_REG_MIPS_FCR_IR:
587 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
588 return -EINVAL;
589 v = boot_cpu_data.fpu_id;
590 break;
591 case KVM_REG_MIPS_FCR_CSR:
592 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
593 return -EINVAL;
594 v = fpu->fcr31;
595 break;
596
597 /* MIPS SIMD Architecture (MSA) registers */
598 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
599 if (!kvm_mips_guest_has_msa(&vcpu->arch))
600 return -EINVAL;
601 /* Can't access MSA registers in FR=0 mode */
602 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
603 return -EINVAL;
604 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
605 #ifdef CONFIG_CPU_LITTLE_ENDIAN
606 /* least significant byte first */
607 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
608 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
609 #else
610 /* most significant byte first */
611 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
612 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
613 #endif
614 break;
615 case KVM_REG_MIPS_MSA_IR:
616 if (!kvm_mips_guest_has_msa(&vcpu->arch))
617 return -EINVAL;
618 v = boot_cpu_data.msa_id;
619 break;
620 case KVM_REG_MIPS_MSA_CSR:
621 if (!kvm_mips_guest_has_msa(&vcpu->arch))
622 return -EINVAL;
623 v = fpu->msacsr;
624 break;
625
626 /* Co-processor 0 registers */
627 case KVM_REG_MIPS_CP0_INDEX:
628 v = (long)kvm_read_c0_guest_index(cop0);
629 break;
630 case KVM_REG_MIPS_CP0_CONTEXT:
631 v = (long)kvm_read_c0_guest_context(cop0);
632 break;
633 case KVM_REG_MIPS_CP0_USERLOCAL:
634 v = (long)kvm_read_c0_guest_userlocal(cop0);
635 break;
636 case KVM_REG_MIPS_CP0_PAGEMASK:
637 v = (long)kvm_read_c0_guest_pagemask(cop0);
638 break;
639 case KVM_REG_MIPS_CP0_WIRED:
640 v = (long)kvm_read_c0_guest_wired(cop0);
641 break;
642 case KVM_REG_MIPS_CP0_HWRENA:
643 v = (long)kvm_read_c0_guest_hwrena(cop0);
644 break;
645 case KVM_REG_MIPS_CP0_BADVADDR:
646 v = (long)kvm_read_c0_guest_badvaddr(cop0);
647 break;
648 case KVM_REG_MIPS_CP0_ENTRYHI:
649 v = (long)kvm_read_c0_guest_entryhi(cop0);
650 break;
651 case KVM_REG_MIPS_CP0_COMPARE:
652 v = (long)kvm_read_c0_guest_compare(cop0);
653 break;
654 case KVM_REG_MIPS_CP0_STATUS:
655 v = (long)kvm_read_c0_guest_status(cop0);
656 break;
657 case KVM_REG_MIPS_CP0_CAUSE:
658 v = (long)kvm_read_c0_guest_cause(cop0);
659 break;
660 case KVM_REG_MIPS_CP0_EPC:
661 v = (long)kvm_read_c0_guest_epc(cop0);
662 break;
663 case KVM_REG_MIPS_CP0_PRID:
664 v = (long)kvm_read_c0_guest_prid(cop0);
665 break;
666 case KVM_REG_MIPS_CP0_CONFIG:
667 v = (long)kvm_read_c0_guest_config(cop0);
668 break;
669 case KVM_REG_MIPS_CP0_CONFIG1:
670 v = (long)kvm_read_c0_guest_config1(cop0);
671 break;
672 case KVM_REG_MIPS_CP0_CONFIG2:
673 v = (long)kvm_read_c0_guest_config2(cop0);
674 break;
675 case KVM_REG_MIPS_CP0_CONFIG3:
676 v = (long)kvm_read_c0_guest_config3(cop0);
677 break;
678 case KVM_REG_MIPS_CP0_CONFIG4:
679 v = (long)kvm_read_c0_guest_config4(cop0);
680 break;
681 case KVM_REG_MIPS_CP0_CONFIG5:
682 v = (long)kvm_read_c0_guest_config5(cop0);
683 break;
684 case KVM_REG_MIPS_CP0_CONFIG7:
685 v = (long)kvm_read_c0_guest_config7(cop0);
686 break;
687 case KVM_REG_MIPS_CP0_ERROREPC:
688 v = (long)kvm_read_c0_guest_errorepc(cop0);
689 break;
690 /* registers to be handled specially */
691 case KVM_REG_MIPS_CP0_COUNT:
692 case KVM_REG_MIPS_COUNT_CTL:
693 case KVM_REG_MIPS_COUNT_RESUME:
694 case KVM_REG_MIPS_COUNT_HZ:
695 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
696 if (ret)
697 return ret;
698 break;
699 default:
700 return -EINVAL;
701 }
702 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
703 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
704
705 return put_user(v, uaddr64);
706 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
707 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
708 u32 v32 = (u32)v;
709
710 return put_user(v32, uaddr32);
711 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
712 void __user *uaddr = (void __user *)(long)reg->addr;
713
714 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
715 } else {
716 return -EINVAL;
717 }
718 }
719
kvm_mips_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)720 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
721 const struct kvm_one_reg *reg)
722 {
723 struct mips_coproc *cop0 = vcpu->arch.cop0;
724 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
725 s64 v;
726 s64 vs[2];
727 unsigned int idx;
728
729 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
730 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
731
732 if (get_user(v, uaddr64) != 0)
733 return -EFAULT;
734 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
735 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
736 s32 v32;
737
738 if (get_user(v32, uaddr32) != 0)
739 return -EFAULT;
740 v = (s64)v32;
741 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
742 void __user *uaddr = (void __user *)(long)reg->addr;
743
744 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
745 } else {
746 return -EINVAL;
747 }
748
749 switch (reg->id) {
750 /* General purpose registers */
751 case KVM_REG_MIPS_R0:
752 /* Silently ignore requests to set $0 */
753 break;
754 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
755 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
756 break;
757 case KVM_REG_MIPS_HI:
758 vcpu->arch.hi = v;
759 break;
760 case KVM_REG_MIPS_LO:
761 vcpu->arch.lo = v;
762 break;
763 case KVM_REG_MIPS_PC:
764 vcpu->arch.pc = v;
765 break;
766
767 /* Floating point registers */
768 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
769 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
770 return -EINVAL;
771 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
772 /* Odd singles in top of even double when FR=0 */
773 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
774 set_fpr32(&fpu->fpr[idx], 0, v);
775 else
776 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
777 break;
778 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
779 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
780 return -EINVAL;
781 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
782 /* Can't access odd doubles in FR=0 mode */
783 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
784 return -EINVAL;
785 set_fpr64(&fpu->fpr[idx], 0, v);
786 break;
787 case KVM_REG_MIPS_FCR_IR:
788 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
789 return -EINVAL;
790 /* Read-only */
791 break;
792 case KVM_REG_MIPS_FCR_CSR:
793 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
794 return -EINVAL;
795 fpu->fcr31 = v;
796 break;
797
798 /* MIPS SIMD Architecture (MSA) registers */
799 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
800 if (!kvm_mips_guest_has_msa(&vcpu->arch))
801 return -EINVAL;
802 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
803 #ifdef CONFIG_CPU_LITTLE_ENDIAN
804 /* least significant byte first */
805 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
806 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
807 #else
808 /* most significant byte first */
809 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
810 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
811 #endif
812 break;
813 case KVM_REG_MIPS_MSA_IR:
814 if (!kvm_mips_guest_has_msa(&vcpu->arch))
815 return -EINVAL;
816 /* Read-only */
817 break;
818 case KVM_REG_MIPS_MSA_CSR:
819 if (!kvm_mips_guest_has_msa(&vcpu->arch))
820 return -EINVAL;
821 fpu->msacsr = v;
822 break;
823
824 /* Co-processor 0 registers */
825 case KVM_REG_MIPS_CP0_INDEX:
826 kvm_write_c0_guest_index(cop0, v);
827 break;
828 case KVM_REG_MIPS_CP0_CONTEXT:
829 kvm_write_c0_guest_context(cop0, v);
830 break;
831 case KVM_REG_MIPS_CP0_USERLOCAL:
832 kvm_write_c0_guest_userlocal(cop0, v);
833 break;
834 case KVM_REG_MIPS_CP0_PAGEMASK:
835 kvm_write_c0_guest_pagemask(cop0, v);
836 break;
837 case KVM_REG_MIPS_CP0_WIRED:
838 kvm_write_c0_guest_wired(cop0, v);
839 break;
840 case KVM_REG_MIPS_CP0_HWRENA:
841 kvm_write_c0_guest_hwrena(cop0, v);
842 break;
843 case KVM_REG_MIPS_CP0_BADVADDR:
844 kvm_write_c0_guest_badvaddr(cop0, v);
845 break;
846 case KVM_REG_MIPS_CP0_ENTRYHI:
847 kvm_write_c0_guest_entryhi(cop0, v);
848 break;
849 case KVM_REG_MIPS_CP0_STATUS:
850 kvm_write_c0_guest_status(cop0, v);
851 break;
852 case KVM_REG_MIPS_CP0_EPC:
853 kvm_write_c0_guest_epc(cop0, v);
854 break;
855 case KVM_REG_MIPS_CP0_PRID:
856 kvm_write_c0_guest_prid(cop0, v);
857 break;
858 case KVM_REG_MIPS_CP0_ERROREPC:
859 kvm_write_c0_guest_errorepc(cop0, v);
860 break;
861 /* registers to be handled specially */
862 case KVM_REG_MIPS_CP0_COUNT:
863 case KVM_REG_MIPS_CP0_COMPARE:
864 case KVM_REG_MIPS_CP0_CAUSE:
865 case KVM_REG_MIPS_CP0_CONFIG:
866 case KVM_REG_MIPS_CP0_CONFIG1:
867 case KVM_REG_MIPS_CP0_CONFIG2:
868 case KVM_REG_MIPS_CP0_CONFIG3:
869 case KVM_REG_MIPS_CP0_CONFIG4:
870 case KVM_REG_MIPS_CP0_CONFIG5:
871 case KVM_REG_MIPS_COUNT_CTL:
872 case KVM_REG_MIPS_COUNT_RESUME:
873 case KVM_REG_MIPS_COUNT_HZ:
874 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
875 default:
876 return -EINVAL;
877 }
878 return 0;
879 }
880
kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu * vcpu,struct kvm_enable_cap * cap)881 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
882 struct kvm_enable_cap *cap)
883 {
884 int r = 0;
885
886 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
887 return -EINVAL;
888 if (cap->flags)
889 return -EINVAL;
890 if (cap->args[0])
891 return -EINVAL;
892
893 switch (cap->cap) {
894 case KVM_CAP_MIPS_FPU:
895 vcpu->arch.fpu_enabled = true;
896 break;
897 case KVM_CAP_MIPS_MSA:
898 vcpu->arch.msa_enabled = true;
899 break;
900 default:
901 r = -EINVAL;
902 break;
903 }
904
905 return r;
906 }
907
kvm_arch_vcpu_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)908 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
909 unsigned long arg)
910 {
911 struct kvm_vcpu *vcpu = filp->private_data;
912 void __user *argp = (void __user *)arg;
913 long r;
914
915 switch (ioctl) {
916 case KVM_SET_ONE_REG:
917 case KVM_GET_ONE_REG: {
918 struct kvm_one_reg reg;
919
920 if (copy_from_user(®, argp, sizeof(reg)))
921 return -EFAULT;
922 if (ioctl == KVM_SET_ONE_REG)
923 return kvm_mips_set_reg(vcpu, ®);
924 else
925 return kvm_mips_get_reg(vcpu, ®);
926 }
927 case KVM_GET_REG_LIST: {
928 struct kvm_reg_list __user *user_list = argp;
929 u64 __user *reg_dest;
930 struct kvm_reg_list reg_list;
931 unsigned n;
932
933 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
934 return -EFAULT;
935 n = reg_list.n;
936 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
937 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
938 return -EFAULT;
939 if (n < reg_list.n)
940 return -E2BIG;
941 reg_dest = user_list->reg;
942 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
943 sizeof(kvm_mips_get_one_regs)))
944 return -EFAULT;
945 return 0;
946 }
947 case KVM_NMI:
948 /* Treat the NMI as a CPU reset */
949 r = kvm_mips_reset_vcpu(vcpu);
950 break;
951 case KVM_INTERRUPT:
952 {
953 struct kvm_mips_interrupt irq;
954
955 r = -EFAULT;
956 if (copy_from_user(&irq, argp, sizeof(irq)))
957 goto out;
958
959 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
960 irq.irq);
961
962 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
963 break;
964 }
965 case KVM_ENABLE_CAP: {
966 struct kvm_enable_cap cap;
967
968 r = -EFAULT;
969 if (copy_from_user(&cap, argp, sizeof(cap)))
970 goto out;
971 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
972 break;
973 }
974 default:
975 r = -ENOIOCTLCMD;
976 }
977
978 out:
979 return r;
980 }
981
982 /* Get (and clear) the dirty memory log for a memory slot. */
kvm_vm_ioctl_get_dirty_log(struct kvm * kvm,struct kvm_dirty_log * log)983 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
984 {
985 struct kvm_memslots *slots;
986 struct kvm_memory_slot *memslot;
987 unsigned long ga, ga_end;
988 int is_dirty = 0;
989 int r;
990 unsigned long n;
991
992 mutex_lock(&kvm->slots_lock);
993
994 r = kvm_get_dirty_log(kvm, log, &is_dirty);
995 if (r)
996 goto out;
997
998 /* If nothing is dirty, don't bother messing with page tables. */
999 if (is_dirty) {
1000 slots = kvm_memslots(kvm);
1001 memslot = id_to_memslot(slots, log->slot);
1002
1003 ga = memslot->base_gfn << PAGE_SHIFT;
1004 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1005
1006 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1007 ga_end);
1008
1009 n = kvm_dirty_bitmap_bytes(memslot);
1010 memset(memslot->dirty_bitmap, 0, n);
1011 }
1012
1013 r = 0;
1014 out:
1015 mutex_unlock(&kvm->slots_lock);
1016 return r;
1017
1018 }
1019
kvm_arch_vm_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)1020 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1021 {
1022 long r;
1023
1024 switch (ioctl) {
1025 default:
1026 r = -ENOIOCTLCMD;
1027 }
1028
1029 return r;
1030 }
1031
kvm_arch_init(void * opaque)1032 int kvm_arch_init(void *opaque)
1033 {
1034 if (kvm_mips_callbacks) {
1035 kvm_err("kvm: module already exists\n");
1036 return -EEXIST;
1037 }
1038
1039 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1040 }
1041
kvm_arch_exit(void)1042 void kvm_arch_exit(void)
1043 {
1044 kvm_mips_callbacks = NULL;
1045 }
1046
kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)1047 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1048 struct kvm_sregs *sregs)
1049 {
1050 return -ENOIOCTLCMD;
1051 }
1052
kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)1053 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1054 struct kvm_sregs *sregs)
1055 {
1056 return -ENOIOCTLCMD;
1057 }
1058
kvm_arch_vcpu_postcreate(struct kvm_vcpu * vcpu)1059 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1060 {
1061 }
1062
kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu * vcpu,struct kvm_fpu * fpu)1063 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1064 {
1065 return -ENOIOCTLCMD;
1066 }
1067
kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu * vcpu,struct kvm_fpu * fpu)1068 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1069 {
1070 return -ENOIOCTLCMD;
1071 }
1072
kvm_arch_vcpu_fault(struct kvm_vcpu * vcpu,struct vm_fault * vmf)1073 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1074 {
1075 return VM_FAULT_SIGBUS;
1076 }
1077
kvm_vm_ioctl_check_extension(struct kvm * kvm,long ext)1078 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1079 {
1080 int r;
1081
1082 switch (ext) {
1083 case KVM_CAP_ONE_REG:
1084 case KVM_CAP_ENABLE_CAP:
1085 r = 1;
1086 break;
1087 case KVM_CAP_COALESCED_MMIO:
1088 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1089 break;
1090 case KVM_CAP_MIPS_FPU:
1091 r = !!cpu_has_fpu;
1092 break;
1093 case KVM_CAP_MIPS_MSA:
1094 /*
1095 * We don't support MSA vector partitioning yet:
1096 * 1) It would require explicit support which can't be tested
1097 * yet due to lack of support in current hardware.
1098 * 2) It extends the state that would need to be saved/restored
1099 * by e.g. QEMU for migration.
1100 *
1101 * When vector partitioning hardware becomes available, support
1102 * could be added by requiring a flag when enabling
1103 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1104 * to save/restore the appropriate extra state.
1105 */
1106 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1107 break;
1108 default:
1109 r = 0;
1110 break;
1111 }
1112 return r;
1113 }
1114
kvm_cpu_has_pending_timer(struct kvm_vcpu * vcpu)1115 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1116 {
1117 return kvm_mips_pending_timer(vcpu);
1118 }
1119
kvm_arch_vcpu_dump_regs(struct kvm_vcpu * vcpu)1120 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1121 {
1122 int i;
1123 struct mips_coproc *cop0;
1124
1125 if (!vcpu)
1126 return -1;
1127
1128 kvm_debug("VCPU Register Dump:\n");
1129 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1130 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1131
1132 for (i = 0; i < 32; i += 4) {
1133 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1134 vcpu->arch.gprs[i],
1135 vcpu->arch.gprs[i + 1],
1136 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1137 }
1138 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1139 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1140
1141 cop0 = vcpu->arch.cop0;
1142 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1143 kvm_read_c0_guest_status(cop0),
1144 kvm_read_c0_guest_cause(cop0));
1145
1146 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1147
1148 return 0;
1149 }
1150
kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)1151 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1152 {
1153 int i;
1154
1155 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1156 vcpu->arch.gprs[i] = regs->gpr[i];
1157 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1158 vcpu->arch.hi = regs->hi;
1159 vcpu->arch.lo = regs->lo;
1160 vcpu->arch.pc = regs->pc;
1161
1162 return 0;
1163 }
1164
kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)1165 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1166 {
1167 int i;
1168
1169 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1170 regs->gpr[i] = vcpu->arch.gprs[i];
1171
1172 regs->hi = vcpu->arch.hi;
1173 regs->lo = vcpu->arch.lo;
1174 regs->pc = vcpu->arch.pc;
1175
1176 return 0;
1177 }
1178
kvm_mips_comparecount_func(unsigned long data)1179 static void kvm_mips_comparecount_func(unsigned long data)
1180 {
1181 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1182
1183 kvm_mips_callbacks->queue_timer_int(vcpu);
1184
1185 vcpu->arch.wait = 0;
1186 if (waitqueue_active(&vcpu->wq))
1187 wake_up_interruptible(&vcpu->wq);
1188 }
1189
1190 /* low level hrtimer wake routine */
kvm_mips_comparecount_wakeup(struct hrtimer * timer)1191 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1192 {
1193 struct kvm_vcpu *vcpu;
1194
1195 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1196 kvm_mips_comparecount_func((unsigned long) vcpu);
1197 return kvm_mips_count_timeout(vcpu);
1198 }
1199
kvm_arch_vcpu_init(struct kvm_vcpu * vcpu)1200 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1201 {
1202 kvm_mips_callbacks->vcpu_init(vcpu);
1203 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1204 HRTIMER_MODE_REL);
1205 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1206 return 0;
1207 }
1208
kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu * vcpu,struct kvm_translation * tr)1209 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1210 struct kvm_translation *tr)
1211 {
1212 return 0;
1213 }
1214
1215 /* Initial guest state */
kvm_arch_vcpu_setup(struct kvm_vcpu * vcpu)1216 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1217 {
1218 return kvm_mips_callbacks->vcpu_setup(vcpu);
1219 }
1220
kvm_mips_set_c0_status(void)1221 static void kvm_mips_set_c0_status(void)
1222 {
1223 uint32_t status = read_c0_status();
1224
1225 if (cpu_has_dsp)
1226 status |= (ST0_MX);
1227
1228 write_c0_status(status);
1229 ehb();
1230 }
1231
1232 /*
1233 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1234 */
kvm_mips_handle_exit(struct kvm_run * run,struct kvm_vcpu * vcpu)1235 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1236 {
1237 uint32_t cause = vcpu->arch.host_cp0_cause;
1238 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1239 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1240 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1241 enum emulation_result er = EMULATE_DONE;
1242 int ret = RESUME_GUEST;
1243
1244 /* re-enable HTW before enabling interrupts */
1245 htw_start();
1246
1247 /* Set a default exit reason */
1248 run->exit_reason = KVM_EXIT_UNKNOWN;
1249 run->ready_for_interrupt_injection = 1;
1250
1251 /*
1252 * Set the appropriate status bits based on host CPU features,
1253 * before we hit the scheduler
1254 */
1255 kvm_mips_set_c0_status();
1256
1257 local_irq_enable();
1258
1259 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1260 cause, opc, run, vcpu);
1261
1262 /*
1263 * Do a privilege check, if in UM most of these exit conditions end up
1264 * causing an exception to be delivered to the Guest Kernel
1265 */
1266 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1267 if (er == EMULATE_PRIV_FAIL) {
1268 goto skip_emul;
1269 } else if (er == EMULATE_FAIL) {
1270 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1271 ret = RESUME_HOST;
1272 goto skip_emul;
1273 }
1274
1275 switch (exccode) {
1276 case T_INT:
1277 kvm_debug("[%d]T_INT @ %p\n", vcpu->vcpu_id, opc);
1278
1279 ++vcpu->stat.int_exits;
1280 trace_kvm_exit(vcpu, INT_EXITS);
1281
1282 if (need_resched())
1283 cond_resched();
1284
1285 ret = RESUME_GUEST;
1286 break;
1287
1288 case T_COP_UNUSABLE:
1289 kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc);
1290
1291 ++vcpu->stat.cop_unusable_exits;
1292 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1293 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1294 /* XXXKYMA: Might need to return to user space */
1295 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1296 ret = RESUME_HOST;
1297 break;
1298
1299 case T_TLB_MOD:
1300 ++vcpu->stat.tlbmod_exits;
1301 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1302 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1303 break;
1304
1305 case T_TLB_ST_MISS:
1306 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1307 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1308 badvaddr);
1309
1310 ++vcpu->stat.tlbmiss_st_exits;
1311 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1312 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1313 break;
1314
1315 case T_TLB_LD_MISS:
1316 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1317 cause, opc, badvaddr);
1318
1319 ++vcpu->stat.tlbmiss_ld_exits;
1320 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1321 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1322 break;
1323
1324 case T_ADDR_ERR_ST:
1325 ++vcpu->stat.addrerr_st_exits;
1326 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1327 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1328 break;
1329
1330 case T_ADDR_ERR_LD:
1331 ++vcpu->stat.addrerr_ld_exits;
1332 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1333 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1334 break;
1335
1336 case T_SYSCALL:
1337 ++vcpu->stat.syscall_exits;
1338 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1339 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1340 break;
1341
1342 case T_RES_INST:
1343 ++vcpu->stat.resvd_inst_exits;
1344 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1345 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1346 break;
1347
1348 case T_BREAK:
1349 ++vcpu->stat.break_inst_exits;
1350 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1351 ret = kvm_mips_callbacks->handle_break(vcpu);
1352 break;
1353
1354 case T_TRAP:
1355 ++vcpu->stat.trap_inst_exits;
1356 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1357 ret = kvm_mips_callbacks->handle_trap(vcpu);
1358 break;
1359
1360 case T_MSAFPE:
1361 ++vcpu->stat.msa_fpe_exits;
1362 trace_kvm_exit(vcpu, MSA_FPE_EXITS);
1363 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1364 break;
1365
1366 case T_FPE:
1367 ++vcpu->stat.fpe_exits;
1368 trace_kvm_exit(vcpu, FPE_EXITS);
1369 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1370 break;
1371
1372 case T_MSADIS:
1373 ++vcpu->stat.msa_disabled_exits;
1374 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
1375 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1376 break;
1377
1378 default:
1379 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1380 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1381 kvm_read_c0_guest_status(vcpu->arch.cop0));
1382 kvm_arch_vcpu_dump_regs(vcpu);
1383 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1384 ret = RESUME_HOST;
1385 break;
1386
1387 }
1388
1389 skip_emul:
1390 local_irq_disable();
1391
1392 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1393 kvm_mips_deliver_interrupts(vcpu, cause);
1394
1395 if (!(ret & RESUME_HOST)) {
1396 /* Only check for signals if not already exiting to userspace */
1397 if (signal_pending(current)) {
1398 run->exit_reason = KVM_EXIT_INTR;
1399 ret = (-EINTR << 2) | RESUME_HOST;
1400 ++vcpu->stat.signal_exits;
1401 trace_kvm_exit(vcpu, SIGNAL_EXITS);
1402 }
1403 }
1404
1405 if (ret == RESUME_GUEST) {
1406 /*
1407 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1408 * is live), restore FCR31 / MSACSR.
1409 *
1410 * This should be before returning to the guest exception
1411 * vector, as it may well cause an [MSA] FP exception if there
1412 * are pending exception bits unmasked. (see
1413 * kvm_mips_csr_die_notifier() for how that is handled).
1414 */
1415 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1416 read_c0_status() & ST0_CU1)
1417 __kvm_restore_fcsr(&vcpu->arch);
1418
1419 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1420 read_c0_config5() & MIPS_CONF5_MSAEN)
1421 __kvm_restore_msacsr(&vcpu->arch);
1422 }
1423
1424 /* Disable HTW before returning to guest or host */
1425 htw_stop();
1426
1427 return ret;
1428 }
1429
1430 /* Enable FPU for guest and restore context */
kvm_own_fpu(struct kvm_vcpu * vcpu)1431 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1432 {
1433 struct mips_coproc *cop0 = vcpu->arch.cop0;
1434 unsigned int sr, cfg5;
1435
1436 preempt_disable();
1437
1438 sr = kvm_read_c0_guest_status(cop0);
1439
1440 /*
1441 * If MSA state is already live, it is undefined how it interacts with
1442 * FR=0 FPU state, and we don't want to hit reserved instruction
1443 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1444 * play it safe and save it first.
1445 *
1446 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1447 * get called when guest CU1 is set, however we can't trust the guest
1448 * not to clobber the status register directly via the commpage.
1449 */
1450 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1451 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1452 kvm_lose_fpu(vcpu);
1453
1454 /*
1455 * Enable FPU for guest
1456 * We set FR and FRE according to guest context
1457 */
1458 change_c0_status(ST0_CU1 | ST0_FR, sr);
1459 if (cpu_has_fre) {
1460 cfg5 = kvm_read_c0_guest_config5(cop0);
1461 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1462 }
1463 enable_fpu_hazard();
1464
1465 /* If guest FPU state not active, restore it now */
1466 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1467 __kvm_restore_fpu(&vcpu->arch);
1468 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1469 }
1470
1471 preempt_enable();
1472 }
1473
1474 #ifdef CONFIG_CPU_HAS_MSA
1475 /* Enable MSA for guest and restore context */
kvm_own_msa(struct kvm_vcpu * vcpu)1476 void kvm_own_msa(struct kvm_vcpu *vcpu)
1477 {
1478 struct mips_coproc *cop0 = vcpu->arch.cop0;
1479 unsigned int sr, cfg5;
1480
1481 preempt_disable();
1482
1483 /*
1484 * Enable FPU if enabled in guest, since we're restoring FPU context
1485 * anyway. We set FR and FRE according to guest context.
1486 */
1487 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1488 sr = kvm_read_c0_guest_status(cop0);
1489
1490 /*
1491 * If FR=0 FPU state is already live, it is undefined how it
1492 * interacts with MSA state, so play it safe and save it first.
1493 */
1494 if (!(sr & ST0_FR) &&
1495 (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU |
1496 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU)
1497 kvm_lose_fpu(vcpu);
1498
1499 change_c0_status(ST0_CU1 | ST0_FR, sr);
1500 if (sr & ST0_CU1 && cpu_has_fre) {
1501 cfg5 = kvm_read_c0_guest_config5(cop0);
1502 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1503 }
1504 }
1505
1506 /* Enable MSA for guest */
1507 set_c0_config5(MIPS_CONF5_MSAEN);
1508 enable_fpu_hazard();
1509
1510 switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) {
1511 case KVM_MIPS_FPU_FPU:
1512 /*
1513 * Guest FPU state already loaded, only restore upper MSA state
1514 */
1515 __kvm_restore_msa_upper(&vcpu->arch);
1516 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1517 break;
1518 case 0:
1519 /* Neither FPU or MSA already active, restore full MSA state */
1520 __kvm_restore_msa(&vcpu->arch);
1521 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1522 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1523 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1524 break;
1525 default:
1526 break;
1527 }
1528
1529 preempt_enable();
1530 }
1531 #endif
1532
1533 /* Drop FPU & MSA without saving it */
kvm_drop_fpu(struct kvm_vcpu * vcpu)1534 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1535 {
1536 preempt_disable();
1537 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1538 disable_msa();
1539 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA;
1540 }
1541 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1542 clear_c0_status(ST0_CU1 | ST0_FR);
1543 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1544 }
1545 preempt_enable();
1546 }
1547
1548 /* Save and disable FPU & MSA */
kvm_lose_fpu(struct kvm_vcpu * vcpu)1549 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1550 {
1551 /*
1552 * FPU & MSA get disabled in root context (hardware) when it is disabled
1553 * in guest context (software), but the register state in the hardware
1554 * may still be in use. This is why we explicitly re-enable the hardware
1555 * before saving.
1556 */
1557
1558 preempt_disable();
1559 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1560 set_c0_config5(MIPS_CONF5_MSAEN);
1561 enable_fpu_hazard();
1562
1563 __kvm_save_msa(&vcpu->arch);
1564
1565 /* Disable MSA & FPU */
1566 disable_msa();
1567 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1568 clear_c0_status(ST0_CU1 | ST0_FR);
1569 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA);
1570 } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1571 set_c0_status(ST0_CU1);
1572 enable_fpu_hazard();
1573
1574 __kvm_save_fpu(&vcpu->arch);
1575 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1576
1577 /* Disable FPU */
1578 clear_c0_status(ST0_CU1 | ST0_FR);
1579 }
1580 preempt_enable();
1581 }
1582
1583 /*
1584 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1585 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1586 * exception if cause bits are set in the value being written.
1587 */
kvm_mips_csr_die_notify(struct notifier_block * self,unsigned long cmd,void * ptr)1588 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1589 unsigned long cmd, void *ptr)
1590 {
1591 struct die_args *args = (struct die_args *)ptr;
1592 struct pt_regs *regs = args->regs;
1593 unsigned long pc;
1594
1595 /* Only interested in FPE and MSAFPE */
1596 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1597 return NOTIFY_DONE;
1598
1599 /* Return immediately if guest context isn't active */
1600 if (!(current->flags & PF_VCPU))
1601 return NOTIFY_DONE;
1602
1603 /* Should never get here from user mode */
1604 BUG_ON(user_mode(regs));
1605
1606 pc = instruction_pointer(regs);
1607 switch (cmd) {
1608 case DIE_FP:
1609 /* match 2nd instruction in __kvm_restore_fcsr */
1610 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1611 return NOTIFY_DONE;
1612 break;
1613 case DIE_MSAFP:
1614 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1615 if (!cpu_has_msa ||
1616 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1617 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1618 return NOTIFY_DONE;
1619 break;
1620 }
1621
1622 /* Move PC forward a little and continue executing */
1623 instruction_pointer(regs) += 4;
1624
1625 return NOTIFY_STOP;
1626 }
1627
1628 static struct notifier_block kvm_mips_csr_die_notifier = {
1629 .notifier_call = kvm_mips_csr_die_notify,
1630 };
1631
kvm_mips_init(void)1632 int __init kvm_mips_init(void)
1633 {
1634 int ret;
1635
1636 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1637
1638 if (ret)
1639 return ret;
1640
1641 register_die_notifier(&kvm_mips_csr_die_notifier);
1642
1643 /*
1644 * On MIPS, kernel modules are executed from "mapped space", which
1645 * requires TLBs. The TLB handling code is statically linked with
1646 * the rest of the kernel (tlb.c) to avoid the possibility of
1647 * double faulting. The issue is that the TLB code references
1648 * routines that are part of the the KVM module, which are only
1649 * available once the module is loaded.
1650 */
1651 kvm_mips_gfn_to_pfn = gfn_to_pfn;
1652 kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1653 kvm_mips_is_error_pfn = is_error_pfn;
1654
1655 return 0;
1656 }
1657
kvm_mips_exit(void)1658 void __exit kvm_mips_exit(void)
1659 {
1660 kvm_exit();
1661
1662 kvm_mips_gfn_to_pfn = NULL;
1663 kvm_mips_release_pfn_clean = NULL;
1664 kvm_mips_is_error_pfn = NULL;
1665
1666 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1667 }
1668
1669 module_init(kvm_mips_init);
1670 module_exit(kvm_mips_exit);
1671
1672 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
1673