1 /* MN103E010 Processor initialisation
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11 #include <linux/kernel.h>
12 #include <asm/fpu.h>
13 #include <asm/rtc.h>
14 #include <asm/busctl-regs.h>
15
16 /*
17 * initialise the on-silicon processor peripherals
18 */
processor_init(void)19 asmlinkage void __init processor_init(void)
20 {
21 int loop;
22
23 /* set up the exception table first */
24 for (loop = 0x000; loop < 0x400; loop += 8)
25 __set_intr_stub(loop, __common_exception);
26
27 __set_intr_stub(EXCEP_ITLBMISS, itlb_miss);
28 __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss);
29 __set_intr_stub(EXCEP_IAERROR, itlb_aerror);
30 __set_intr_stub(EXCEP_DAERROR, dtlb_aerror);
31 __set_intr_stub(EXCEP_BUSERROR, raw_bus_error);
32 __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault);
33 __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled);
34 __set_intr_stub(EXCEP_SYSCALL0, system_call);
35
36 __set_intr_stub(EXCEP_NMI, nmi_handler);
37 __set_intr_stub(EXCEP_WDT, nmi_handler);
38 __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler);
39 __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler);
40 __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler);
41 __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler);
42 __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler);
43 __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler);
44 __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler);
45
46 IVAR0 = EXCEP_IRQ_LEVEL0;
47 IVAR1 = EXCEP_IRQ_LEVEL1;
48 IVAR2 = EXCEP_IRQ_LEVEL2;
49 IVAR3 = EXCEP_IRQ_LEVEL3;
50 IVAR4 = EXCEP_IRQ_LEVEL4;
51 IVAR5 = EXCEP_IRQ_LEVEL5;
52 IVAR6 = EXCEP_IRQ_LEVEL6;
53
54 mn10300_dcache_flush_inv();
55 mn10300_icache_inv();
56
57 /* disable all interrupts and set to priority 6 (lowest) */
58 for (loop = 0; loop < NR_IRQS; loop++)
59 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
60
61 /* clear the timers */
62 TM0MD = 0;
63 TM1MD = 0;
64 TM2MD = 0;
65 TM3MD = 0;
66 TM4MD = 0;
67 TM5MD = 0;
68 TM6MD = 0;
69 TM6MDA = 0;
70 TM6MDB = 0;
71 TM7MD = 0;
72 TM8MD = 0;
73 TM9MD = 0;
74 TM10MD = 0;
75 TM11MD = 0;
76
77 calibrate_clock();
78 }
79
80 /*
81 * determine the memory size and base from the memory controller regs
82 */
get_mem_info(unsigned long * mem_base,unsigned long * mem_size)83 void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size)
84 {
85 unsigned long base, size;
86
87 *mem_base = 0;
88 *mem_size = 0;
89
90 base = SDBASE(0);
91 if (base & SDBASE_CE) {
92 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
93 size = ~size + 1;
94 base &= SDBASE_CBA;
95
96 printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base);
97 *mem_size += size;
98 *mem_base = base;
99 }
100
101 base = SDBASE(1);
102 if (base & SDBASE_CE) {
103 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
104 size = ~size + 1;
105 base &= SDBASE_CBA;
106
107 printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base);
108 *mem_size += size;
109 if (*mem_base == 0)
110 *mem_base = base;
111 }
112 }
113